INTEL I960

ADVANCE INFORMATION
i960® RP/RD I/O PROCESSOR AT 3.3 VOLTS
•
•
•
•
33 MHz, 3.3 Volt Version (80960RP 33/3.3)
66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core
Complies with PCI Local Bus Specification Revision 2.1
5 Volt PCI Signalling Environment
■ High Performance 80960JF Core
■
■
■
■
■ DMA Controller
— Sustained One Instruction/Clock
Execution
— 4 Kbyte Two-Way Set-Associative
Instruction Cache
— 2 Kbyte Direct-Mapped Data Cache
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Programmable Bus Widths:
8-, 16-, 32-Bit
— 1 Kbyte Internal Data RAM
— Local Register Cache
(Eight Available Stack Frames)
— Two 32-Bit On-Chip Timer Units
PCI-to-PCI Bridge Unit
— Primary and Secondary PCI Interfaces
— Two 64-Byte Posting Buffers
— Delayed and Posted Transaction
Support
— Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
Two Address Translation Units
— Connects Local Bus to PCI Buses
— Inbound/Outbound Address Translation
Support
— Direct Outbound Addressing Support
Messaging Unit
— Four Message Registers
— Two Doorbell Registers
— Four Circular Queues
— 1004 Index Registers
Memory Controller
— 256 Mbytes of 32- or 36-Bit DRAM
— Interleaved or Non-Interleaved DRAM
— Fast Page-Mode DRAM Support
— Extended Data Out and Burst
— Extended Data Out DRAM Support
— Two Independent Banks for SRAM / ROM
/ Flash (16 Mbytes/Bank; 8- or 32-Bit)
© INTEL CORPORATION, 1997
—
—
—
—
—
■
■
■
■
Three Independent Channels
PCI Memory Controller Interface
32-Bit Local Bus Addressing
64-Bit PCI Bus Addressing
Independent Interface to Primary and
Secondary PCI Buses
— 132 Mbyte/sec Burst Transfers to PCI
and Local Buses
— Direct Addressing to and from PCI
Buses
— Unaligned Transfers Supported in
Hardware
— Two Channels Dedicated to Primary
PCI Bus
— One Channel Dedicated to Secondary
PCI Bus
I/O APIC Bus Interface Unit
— Multiprocessor Interrupt Management
for Intel Architecture CPUs
(Pentium® and Pentium® Pro
Processors)
— Dynamic Interrupt Distribution
— Multiple I/O Subsystem Support
I2C Bus Interface Unit
— Serial Bus
— Master/Slave Capabilities
— System Management Functions
Secondary PCI Arbitration Unit
— Supports Six Secondary PCI Devices
— Multi-priority Arbitration Algorithm
— External Arbitration Support Mode
Private PCI Device Support
■ SuperBGA* Package
— 352 Ball-Grid Array (HL-PBGA)
September, 1997
Order Number: 273001-002
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
©INTEL CORPORATION, 1997
i960® Rx I/O Processor at 3.3 V
1.0 ABOUT THIS DOCUMENT ....................................................................................................................... 1
1.1 Solutions960® Program ...................................................................................................................... 1
1.2 Terminology ........................................................................................................................................ 1
1.3 Additional Information Sources ........................................................................................................... 1
2.0 FUNCTIONAL OVERVIEW ....................................................................................................................... 2
2.1 Key Functional Units ........................................................................................................................... 3
2.1.1 PCI-to-PCI Bridge Unit ............................................................................................................. 3
2.1.2 Private PCI Device Support ..................................................................................................... 3
2.1.3 DMA Controller ........................................................................................................................ 3
2.1.4 Address Translation Unit .......................................................................................................... 3
2.1.5 Messaging Unit ........................................................................................................................ 3
2.1.6 Memory Controller ................................................................................................................... 3
2.1.7 I2C Bus Interface Unit .............................................................................................................. 3
2.1.8 I/O APIC Bus Interface Unit ..................................................................................................... 3
2.1.9 Secondary PCI Arbitration Unit ................................................................................................ 4
2.2 i960 Core Features (80960JF) ........................................................................................................... 4
2.2.1 Burst Bus ................................................................................................................................. 5
2.2.2 Timer Unit ................................................................................................................................ 5
2.2.3 Priority Interrupt Controller ....................................................................................................... 5
2.2.4 Faults and Debugging .............................................................................................................. 5
2.2.5 On-Chip Cache and Data RAM ................................................................................................ 5
2.2.6 Local Register Cache ............................................................................................................... 5
2.2.7 Test Features ........................................................................................................................... 5
2.2.8 Memory-Mapped Control Registers ......................................................................................... 6
2.2.9 Instructions, Data Types and Memory Addressing Modes ...................................................... 6
3.0 PACKAGE INFORMATION ....................................................................................................................... 8
3.1 Package Introduction .......................................................................................................................... 8
3.1.1 Functional Signal Definitions .................................................................................................... 8
3.1.2 352-Lead HL-PBGA Package ................................................................................................ 21
3.2 Package Thermal Specifications ...................................................................................................... 31
3.2.1 Thermal Specifications ........................................................................................................... 31
3.2.1.1 Ambient Temperature ............................................................................................... 31
3.2.1.2 Case Temperature .................................................................................................... 31
3.2.1.3 Thermal Resistance .................................................................................................. 31
3.2.2 Thermal Analysis ................................................................................................................... 32
3.3 Sources for Heatsinks and Accessories ........................................................................................... 33
4.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 34
4.1 Absolute Maximum Ratings .............................................................................................................. 34
4.2 VCC5 Pin Requirements (VDIFF) ........................................................................................................ 34
4.3 Targeted DC Specifications .............................................................................................................. 35
4.4 Targeted AC Specifications .............................................................................................................. 37
4.4.1 Relative Output Timings ......................................................................................................... 39
4.4.2 Memory Controller Relative Output Timings .......................................................................... 39
4.4.3 Boundary Scan Test Signal Timings ...................................................................................... 42
4.4.4 APIC Bus Interface Signal Timings ........................................................................................ 42
4.4.5 I2C Interface Signal Timings .................................................................................................. 43
4.5 AC Test Conditions ........................................................................................................................... 44
4.6 AC Timing Waveforms ...................................................................................................................... 44
4.7 Memory Controller Output Timing Waveforms ................................................................................. 48
5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 55
6.0 DEVICE IDENTIFICATION ON RESET ................................................................................................... 64
iii
i960® Rx I/O Processor at 3.3 V
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
iv
i960® Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2
80960JF Core Block Diagram ........................................................................................................ 4
352L HL-PBGA Package Diagram (Top and Side View) ............................................................. 21
352L HL-PBGA Package Diagram (Bottom View) ....................................................................... 22
Thermocouple Attachment - No Heat Sink .................................................................................. 31
Thermocouple Attachment - With Heat Sink ................................................................................ 31
VCC5 Current-Limiting Resistor ................................................................................................... 34
AC Test Load ............................................................................................................................... 44
S_CLK, TCLK Waveform ............................................................................................................. 44
TOV Output Delay Waveform ....................................................................................................... 45
TOF Output Float Waveform ......................................................................................................... 45
TIS and TIH Input Setup and Hold Waveform ............................................................................... 46
TLXL and TLXA Relative Timings Waveform ................................................................................. 46
DT/R# and DEN# Timings Waveform .......................................................................................... 47
I2C Interface Signal Timings ........................................................................................................ 47
Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ... 48
Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus . 49
FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States .......................................... 50
FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ........................................... 51
EDO DRAM, Read Cycle ............................................................................................................. 52
EDO DRAM, Write Cycle ............................................................................................................. 52
BEDO DRAM, Read Cycle ........................................................................................................... 53
BEDO DRAM, Write Cycle ........................................................................................................... 53
32-Bit Bus, SRAM Read Accesses with 0 Wait States ................................................................ 54
32-Bit Bus, SRAM Write Accesses with 0 Wait States ................................................................ 54
Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus .............. 55
Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ...................... 56
Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ................................ 57
Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus ........................ 58
Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read,
16-Bit 80960 Local Bus ................................................................................................................ 59
Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit 80960 Local Bus ........................................................................... 60
HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 61
80960 Core Cold Reset Waveform .............................................................................................. 62
80960 Local Bus Warm Reset Waveform .................................................................................... 63
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Related Documentation ................................................................................................................. 1
80960Rx Instruction Set ................................................................................................................ 7
Signal Type Definition .................................................................................................................... 8
Signal Descriptions ........................................................................................................................ 9
Power Requirement, Processor Control and Test Signal Descriptions ....................................... 13
Interrupt Unit Signal Descriptions .................................................................................... ............ 14
PCI Signal Descriptions ............................................................................................... ................ 15
Memory Controller Signal Descriptions ....................................................................................... 18
DMA, APIC, I2C Units Signal Descriptions .................................................................................. 19
Clock Signal ................................................................................................................................. 20
ICE Signal Descriptions ............................................................................................................... 20
352-Lead HL-PBGA Package — Signal Name Order (Sheet 1 of 4) ........................................... 23
352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet 1 of 4) ......................................... 27
352-Lead HL-PBGA Package Thermal Characteristics ............................................................... 32
Heatsink Information .................................................................................................................... 33
Operating Conditions ................................................................................................................... 34
VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ....................................... 34
DC Characteristics ....................................................................................................................... 35
ICC Characteristics ....................................................................................................................... 36
Input Clock Timings ..................................................................................................................... 37
Synchronous Output Timings ...................................................................................................... 37
Synchronous Input Timings ......................................................................................................... 38
Relative Output Timings .............................................................................................................. 39
Fast Page Mode Non-interleaved DRAM Output Timings ........................................................... 39
Fast Page Mode Interleaved DRAM Output Timings ................................................................... 40
EDO DRAM Output Timings ........................................................................................................ 40
BEDO DRAM Output Timings ...................................................................................................... 41
SRAM/ROM Output Timings ........................................................................................................ 41
Boundary Scan Test Signal Timings ............................................................................................ 42
APIC Bus Interface Signal Timings .............................................................................................. 42
I2C Interface Signal Timings ........................................................................................................ 43
Processor Device ID Register - PDIDR ...................................................................................... 64
i960® Rx I/O Processor at 3.3 V
vi
i960® Rx I/O Processor at 3.3 V
1.0
ABOUT THIS DOCUMENT
This is the ADVANCE INFORMATION data sheet for
the low-power (3.3 V) versions of Intel’s i960® Rx I/O
Processor family, including:
• 80960RD 66/3.3
• 80960RP 33/3.3
Throughout this document, these family members
are referred to as 80960Rx when the information is
common to both. For product-specific information,
such as electrical characteristics, the family member
names are used.
This does not contain specifications for the 5 Volt
version (80960RP 33/5.0). For specifications on that
product, refer to the i960® RP I/O Processor Data
Sheet (272737).
This data sheet contains a functional overview,
mechanical data (package signal locations and
simulated thermal characteristics), targeted electrical
specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than
parametric performance is published in the i960® RP
Microprocessor User’s Guide (272736).
1.1
Solutions960® Program
Intel’s Solutions960® program features a wide
variety of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For
more information on these products, contact your
local Intel representative.
1.2
Terminology
In this document, the following terms are used:
• local bus refers to the 80960Rx’s internal local
bus, not the PCI local bus.
• Primary and Secondary PCI buses are the
80960Rx’s internal PCI buses which conform to
PCI SIG specifications.
• 80960 core refers to the 80960JF processor which
is integrated into the 80960Rx.
1.3
Additional Information Sources
Intel documentation is available from your local Intel
Sales Representative or Intel Literature Sales.
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect IL 60056-7641
1-800-879-4683
Table 1. Related Documentation
Document Title
i960® RP Microprocessor User’s Guide
i960® RP Processor: A Single-Chip Intelligent I/O Subsystem
Technical Brief
i960® Jx Microprocessor User’s Guide
80960RP Specification Update
PCI Local Bus Specification Revision 2.1
PCI-to-PCI Bridge Architecture Specification Revision 1.0
I2C Peripherals for Microcontrollers
ADVANCE INFORMATION
Order / Contact
Intel Order # 272736
Intel Order # 272738
Intel Order # 272483
Intel Order # 272918
PCI Special Interest Group 1-800-433-5177
PCI Special Interest Group 1-800-433-5177
Philips Semiconductor
1
i960® Rx I/O Processor at 3.3 V
2.0
The PCI-to-PCI bridge unit is the connection path
between two independent 32-bit PCI buses and
provides the ability to overcome PCI electrical load
limits. The addition of the i960 core processor brings
intelligence to the bridge.
FUNCTIONAL OVERVIEW
As indicated in Figure 1, the 80960Rx combines
many features with the 80960JF to create an intelligent I/O processor. Subsections following the figure
briefly describe the main features; for detailed functional descriptions, refer to the i960® RP Microprocessor User’s Guide (272736).
The 80960Rx, object code compatible with the i960
core processor, is capable of sustained execution at
the rate of one instruction per clock.
The PCI bus is an industry standard, high performance, low latency system bus that operates up to
132 Mbyte/s. The 80960Rx, a multi-function PCI
device, is fully compliant with the PCI Local Bus
Specification Revision 2.1. Function 0 is the PCI-toPCI bridge unit; Function 1 is the address translation
unit.
Local Memory
The local bus, a 32-bit multiplexed burst bus, is a
high-speed interface to system memory and I/O. A
full complement of control signals simplifies the
connection of the 80960Rx to external components.
Physical and logical memory attributes are
programmed via memory-mapped control registers
(MMRs), an extension not found on the i960 Kx, Sx
or Cx processors. Physical and logical configuration
registers enable the processor to operate with all
combinations of bus width and data object alignment.
I2C Serial Bus
I/O APIC Bus
I2C Bus
Interface Unit
I/O APIC Bus
Interface Unit
i960® JF
Memory
Controller
Core
Processor
Internal
Arbitration
Local Bus
Primary ATU
Two DMA
Channels
Address
Translation
Unit
Secondary ATU
Message
Unit
One DMA
Channel
Address
Translation
Unit
PCI-to-PCI
Bridge Unit
Secondary PCI Bus
Primary PCI Bus
Secondary
PCI Arbitration
Unit
Figure 1. i960® Rx I/O Processor at 3.3 V Functional Block Diagram
2
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
2.1
Key Functional Units
2.1.1
PCI-to-PCI Bridge Unit
The PCI-to-PCI bridge unit (referred to as “bridge”)
connects two independent PCI buses. It is fully
compliant with the PCI-to-PCI Bridge Architecture
Specification Revision 1.0 published by the PCI
Special Interest Group. It allows certain bus transactions on one PCI bus to be forwarded to the other
PCI bus. Dedicated data queues support high performance bandwidth on the PCI buses. The i960® Rx
I/O Processor at 3.3 V supports PCI 64-bit Dual
Address Cycle (DAC) addressing.
The bridge has dedicated PCI configuration space
that is accessible through the primary PCI bus.
Address translation is controlled through programmable registers accessible from both the PCI interface and the 80960 core. Dual access to registers
allows flexibility in mapping the two address spaces.
2.1.5
The Messaging Unit (MU) provides data transfer
between the PCI system and the 80960Rx. It uses
interrupts to notify each system when new data
arrives. The MU has four messaging mechanisms.
Each allows a host processor or external PCI device
and the 80960Rx to communicate through message
passing and interrupt generation. The four mechanisms are Message Registers, Doorbell Registers,
Circular Queues, and Index Registers.
2.1.6
2.1.2
Private PCI Device Support
A key design feature is that the 80960Rx explicitly
supports private PCI devices on the secondary PCI
bus without being detected by PCI configuration software. The bridge and Address Translation Unit work
together to hide private devices from PCI configuration cycles and allow these devices to use a private
PCI address space. The Address Translation Unit
uses normal PCI configuration cycles to configure
these devices.
2.1.3
DMA Controller
The DMA Controller supports low-latency, highthroughput data transfers between PCI bus agents
and 80960 local memory. Three separate DMA
channels accommodate data transfers: two for
primary PCI bus, one for the secondary PCI bus.
The DMA Controller supports chaining and
unaligned data transfers. It is programmable only
through the i960 core processor.
2.1.4
Messaging Unit
Memory Controller
The Memory Controller allows direct control of
external memory systems, including DRAM, SRAM,
ROM and Flash Memory. It provides a direct connect
interface to memory that typically does not require
external logic. It features programmable chip selects,
a wait state generator and byte parity. External
memory can be configured as PCI addressable
memory or private processor memory.
2.1.7
I2C Bus Interface Unit
The I2C (Inter-Integrated Circuit) Bus Interface Unit
allows the 80960 core to serve as a master and
slave device residing on the I2C bus. The I2C bus is
a serial bus developed by Philips Semiconductor
consisting of a two pin interface. The bus allows the
80960Rx to interface to other I2C peripherals and
microcontrollers for system management functions.
It requires a minimum of hardware for an economical
system to relay status and reliability information on
the I/O subsystem to an external device. For more
information, see I2C Peripherals for Microcontrollers
(Philips Semiconductor)
Address Translation Unit
The Address Translation Unit (ATU) allows PCI
transactions direct access to the 80960Rx local
memory. The 80960Rx has direct access to both PCI
buses. The ATU supports transactions between PCI
address space and 80960Rx address space.
ADVANCE INFORMATION
2.1.8
I/O APIC Bus Interface Unit
The I/O APIC Bus Interface Unit provides an interface to the three-wire Advanced Programmable
Interrupt Controller (APIC) bus that allows I/O APIC
emulation in software. Interrupt messages can be
sent on the bus and EOI messages can be received.
3
i960® Rx I/O Processor at 3.3 V
2.1.9
• Independent Multiply/Divide Unit
Secondary PCI Arbitration Unit
The Secondary PCI Arbitration Unit provides PCI
arbitration for the secondary PCI bus. It includes a
fairness algorithm with programmable priorities and
six PCI Request and Grant signal pairs. This arbitration unit can also be disabled to allow for external
arbitration.
2.2
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set-associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
i960 Core Features (80960JF)
The processing power of the 80960Rx comes from
the 80960JF processor core. The 80960JF is a new,
scalar implementation of the 80960 Core Architecture. Figure 2 shows a block diagram of the 80960JF
Core processor.
• 1 Kbyte integrated data RAM delivers zero wait
state program data
The 80960 core operates out of its own 32-bit
address space, which is independent of the PCI
address space. The local bus memory can be:
• Made visible to the PCI address space
Factors that contribute to the 80960 family core’s
performance include:
• Single-clock execution of most instructions
• Kept private to the 80960 core
• Allocated as a combination of the two
32-bit buses
address / data
S_CLK
PLL, Clocks,
Power Mgmt
Instruction Cache
4 Kbyte Two-Way Set Associative
TAP
5
Instruction Sequencer
Constants
DST
DST
DST
SRC2
SRC1
SRC2
Register File
SRC1
SRC2
Effective
Address
Address/
Data Bus
32
Two 32-Bit
Timers
Memory
Interface
Unit
32-bit Addr
32-bit Data
Interrupt
Port
9
Memory-Mapped
Register Interface
1 Kbyte
Data RAM
DST
Global / Local
Execution
and
Address
Generation
Unit
SRC1
Multiply
Divide
Unit
Control
Control
Programmable
Interrupt Controller
8-Set
Local Register
Cache
SRC1
Bus
Control Unit
Bus Request
Queues
Boundary Scan
Controller
128
Physical Region
Configuration
2 Kbyte
Direct Mapped
Data Cache
3 Independent 32-Bit SRC1, SRC2, and DST Buses
Figure 2. 80960JF Core Block Diagram
4
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
2.2.1
Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960Rx to external memory and peripherals.
The Bus Control Unit fetches instructions and transfers data on the local bus at the rate of up to four 32bit words per six clock cycles. The external
address/data bus is multiplexed.
Users may configure the 80960Rx’s bus controller to
match an application’s fundamental memory organization. Physical bus width is programmable for up to
eight regions. Data caching is programmed through
a group of logical memory templates and a defaults
register. The Bus Control Unit’s features include:
• Multiplexed external bus minimizes pin count
• 32-, 16- and 8-bit bus widths simplify I/O interfaces
• External ready control for address-to-data, data-todata and data-to-next-address wait state types
• Little endian byte ordering
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
2.2.4
Faults and Debugging
The 80960Rx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities.
Via software, the 80960Rx may be configured to
detect as many as seven different trace event types.
Alternatively, mark and fmark instructions can
generate trace events explicitly in the instruction
stream. Hardware breakpoint registers are also
available to trap on execution and data addresses.
• Unaligned bus accesses performed transparently
• Three-deep load/store queue decouples the bus
from the 80960 core
2.2.5
On-Chip Cache and Data RAM
Upon reset, the 80960Rx conducts an internal self
test. Before executing its first instruction, it performs
an external bus confidence test by performing a
checksum on the first words of the Initialization Boot
Record.
Memory subsystems often impose substantial wait
state penalties. The 80960Rx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus. It also includes a
4 Kbyte instruction cache, a 2 Kbyte data cache and
1 Kbyte data RAM.
2.2.2
2.2.6
Timer Unit
The timer unit (TU) contains two independent 32-bit
timers that are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the Timer Unit registers. These memorymapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and autoreload capabilities for continuous operation. Each
timer has an independent interrupt request to the
80960Rx’s interrupt controller. The TU can generate
a fault when unauthorized writes from user mode are
detected.
2.2.3
Priority Interrupt Controller
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960Rx exploits several techniques to minimize latency:
Local Register Cache
The 80960Rx rapidly allocates and deallocates local
register sets during context switches. The processor
needs to flush a register set to the stack only when it
saves more than seven sets to its local register
cache.
2.2.7
Test Features
The 80960Rx incorporates numerous features that
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
The 80960Rx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
ADVANCE INFORMATION
5
i960® Rx I/O Processor at 3.3 V
One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset without using the boundary scan mechanism.
• Five Register Indirect modes
ONCE mode is useful for board-level testing. This
feature allows a mounted 80960Rx to electrically
“remove” itself from a circuit board. This mode allows
system-level testing where a remote tester can
exercise the processor system.
Table 2 shows the available instructions.
• Index with displacement mode
• IP with displacement mode
The test logic does not interfere with component or
system behavior and ensures that components
function correctly, and also the connections between
various components are correct.
The JTAG Boundary Scan feature is an alternative
to conventional “bed-of-nails” testing. It can examine
connections that might otherwise be inaccessible to
a test system.
2.2.8
Memory-Mapped Control Registers
The 80960Rx is compliant with 80960 family architecture and has the added advantage of memorymapped, internal control registers not found on the
80960Kx, Sx or Cx processors. This feature provides
software an interface to easily read and modify
internal control registers.
Each memory-mapped, 32-bit register is accessed
via regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.
2.2.9
Instructions, Data Types and Memory
Addressing Modes
As with all 80960 family processors, the 80960Rx
instruction set supports several different data types
and formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960Rx provides a full set of addressing
modes for C and assembly:
• Two Absolute modes
6
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 2. 80960Rx Instruction Set
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Load
Add
And
Set Bit
Store
Subtract
Not And
Clear Bit
Move
Multiply
And Not
Not Bit
Conditional Select
Divide
Or
Alter Bit
Load Address
Remainder
Exclusive Or
Scan For Bit
Modulo
Not Or
Span Over Bit
Shift
Or Not
Extract
Extended Shift
Nor
Modify
Extended Multiply
Exclusive Nor
Scan Byte for Equal
Extended Divide
Not
Byte Swap
Add with Carry
Nand
Subtract with Carry
Conditional Add
Conditional Subtract
Rotate
Comparison
Branch
Call/Return
Fault
Compare
Unconditional Branch
Call
Conditional Fault
Conditional Compare
Conditional Branch
Call Extended
Synchronize Faults
Compare and
Increment
Compare and Branch
Call System
Return
Compare and
Decrement
Branch and Link
Test Condition Code
Check Bit
Processor
Management
Debug
Atomic
Modify Trace Controls
Flush Local Registers
Atomic Add
Mark
Modify Arithmetic
Controls
Atomic Modify
Force Mark
Modify Process
Controls
Halt
System Control
Cache Control
Interrupt Control
ADVANCE INFORMATION
7
i960® Rx I/O Processor at 3.3 V
3.0
PACKAGE INFORMATION
3.1
Package Introduction
Table 3. Signal Type Definition
Symbol
The 80960Rx is offered in a SuperBGA* Ball Grid
Array (HL-PBGA) package. This is a perimeter array
package with four rows of ball connections in the
outer area of the package. See Figure 4, 352L HLPBGA Package Diagram (Bottom View) (pg. 22).
Section 3.1.1, Functional Signal Definitions
describes signal function; Section 3.1.2, 352-Lead
HL-PBGA Package defines the signal and ball locations.
I
Input signal only.
O
Output signal only.
I/O
Signal can be either an input or output.
OD
Open Drain signal.
–
Signal must be connected as described.
S (...)
Functional Signal Definitions
Table 3 presents the legend for interpreting the Type
Field in the following tables. Table 4 defines signals
associated with the bus interface. Table 5 defines
signals associated with basic control and test functions. Table 6 defines signals associated with the
Interrupt Unit. Table 7 defines PCI signals. Table 8
defines Memory Controller signals. Table 9 defines
DMA, APIC and I2C signals. Table 10 defines clock
signals. Table 11 defines ICE signals.
Synchronous. Inputs must meet setup
and hold times relative to S_CLK.
S(E) Edge sensitive input
S(L) Level sensitive input
A (...)
3.1.1
Description
Asynchronous. Inputs may be
asynchronous relative to S_CLK.
A(E) Edge sensitive input
A(L) Level sensitive input
R (...)
While the P_RST# signal is asserted,
the signal:
R(1) is driven to VCC
R(0) is driven to VSS
R(Q) is a valid output
R(Z) Floats
R(H) is pulled up to VCC
R(X) is driven to an unknown state
H (...)
While the 80960Rx is in the hold state,
the signal:
H(1) is driven to VCC
H(0) is driven to VSS
H(Q) Maintains previous state or
continues to be a valid output
H(Z) Floats
P (...)
While the 80960Rx is halted, the signal:
P(1) is driven to VCC
P(0) is driven to VSS
P(Q) Maintains previous state or
continues to be a valid output
K (...)
While the Secondary PCI Bus is being
parked, the signal:
K(Z) Floats
K(Q) Maintains previous state or
continues to be a valid output
8
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 1 of 5)
NAME
AD31:0
TYPE
DESCRIPTION
I/O
S(L)
R(Z)
H(Z)
P(Q)
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32bit data to and from memory. During an address (Ta) cycle, bits 2-31 contain
a physical word address (bits 0-1 indicate SIZE; see below). During a data
(Td) cycle, read or write data is present on one or more contiguous bytes,
comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations,
unused signals are driven to determinate values.
SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies
the number of data transfers during the bus transaction on the local bus.
When the DMA or ATUs initiate data transfers, transfer size shown below is
not valid.
AD1
0
0
1
1
AD0
0
1
0
1
Bus Transfers
1 Transfer
2 Transfers
3 Transfers
4 Transfers
When the 80960Rx enters Halt mode and the previous bus operation was:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:2 are driven with the last address value on the AD bus.
Typically, AD1:0 reflect the SIZE information of the last bus transaction
(either instruction fetch or load/store) that was executed before entering Halt
mode.
ADS#
O
R(1)
H(Z)
P(1)
ADDRESS STROBE indicates a valid address and the start of a new bus
access. The processor asserts ADS# for the entire Ta cycle. External bus
control logic typically samples ADS# at the end of the cycle.
ALE
O
R(0)
H(Z)
P(0)
ADDRESS LATCH ENABLE indicates the transfer of a physical address.
ALE is asserted during a Ta cycle and deasserted before the beginning of the
Td state. It is active HIGH and floats to a high impedance state during a hold
cycle (Th).
BLAST#
O
H(Z)
P(1)
BURST LAST indicates the last transfer in a bus access. BLAST# is
asserted in the last data transfer of burst and non-burst accesses. BLAST#
remains active while wait states are detected via the LRDYRCV# or
RDYRCV# signal on the memory controller. BLAST# becomes inactive after
the final data transfer in a bus cycle. BLAST# has a weak internal pullup
which is active during reset to ensure normal operation when the signal is
not connected.
0 = Last Data Transfer
1 = Not the Last Data Transfer
ADVANCE INFORMATION
9
i960® Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 2 of 5)
NAME
BE3:0#
DEN#
TYPE
DESCRIPTION
O
R(1)
H(Z)
P(1)
BYTE ENABLES select which of up to four data bytes on the bus participate
in the current bus access. Byte enable encoding depends on the bus width
of the memory region accessed:
O
H(Z)
P(1)
32-bit bus:
BE3# enables data on AD31:24
BE2# enables data on AD23:16
BE1# enables data on AD15:8
BE0# enables data on AD7:0
16-bit bus:
BE3# becomes Byte High Enable (enables data on AD15:8)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
(increments with the assertion of LRDY# or RDYRCV#)
BE0# becomes Byte Low Enable (enables data on AD7:0)
8-bit bus:
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
(increments with the assertion of LRDY# or RDYRCV#)
BE0# becomes Address Bit 0 (A0)
(increments with the assertion of LRDY# or RDYRCV#)
The processor asserts byte enables, byte high enable and byte low enable
during Ta. Since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst (32-bit bus only) from the
i960 core processor; they do toggle for DMA and ATU cycles. They remain
active through the last Td cycle.
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is
asserted at the start of the first data cycle in a bus access and deasserted at
the end of the last data cycle. DEN# is used with DT/R# to provide control for
data transceivers connected to the data bus. DEN# has a weak internal
pullup which is active during reset to ensure normal operation when the
signal is not connected.
0 = Data Cycle
1 = Not a Data Cycle
10
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 3 of 5)
NAME
D/C#/
RST_MODE#
TYPE
I/O
R(H)
H(Z)
P(Q)
DESCRIPTION
DATA/CODE/RESET_MODE indicates that a bus access is a data access
or an instruction access. D/C# has the same timing as W/R#.
0 = Instruction Access
1 = Data Access
The RST_MODE# signal is sampled at Primary PCI bus reset to determine
whether the 80960 core is to be held in reset. When RST_MODE# is high,
the 80960Rx begins initialization immediately following the deassertion of
P_RST. When RST_MODE is low, the 80960 core remains in reset until the
80960 core reset bit is cleared in the extended bridge control register. This
signal has a weak internal pullup that is active during reset to ensure normal
operation when the signal is left unconnected.
0 = RST_MODE enabled
1 = RST_MODE not enabled
While the 80960 core is in reset, all peripherals may be accessed from the
primary or secondary PCI buses depending on the status of the
WIDTH/HLTD1/RETRY/ signal.
DT/R#
O
R(0)
H(Z)
P(Q)
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and
from the address/data bus. It is low during Ta and Tw/Td cycles for a read; it
is high during Ta and Tw/Td cycles for a write. DT/R# never changes state
when DEN# is asserted.
0 = Receive
1 = Transmit
LOCK#/ONCE#
I/O
S(L)
R(H)
H(Z)
P(Q)
BUS LOCK indicates that an atomic read-modify-write operation is in
progress. The LOCK# output is asserted in the first clock of an atomic
operation and deasserted in the last data transfer of the sequence. The
processor does not grant HOLDA while asserting LOCK#. This prevents
external agents from accessing memory involved in semaphore operations.
0 = Atomic Read-Modify-Write in Progress
1 = No Atomic Read-Modify-Write in Progress
ONCE MODE: The processor samples the ONCE input during reset. When
ONCE# is asserted LOW at the end of reset, the processor enters ONCE
mode, stops all clocks and floats all output signals. LOCK#/ONCE# has a
weak internal pullup which is active during reset to ensure normal operation
when the signal is not connected.
0 = ONCE Mode Enabled
1 = ONCE Mode Not Enabled
LRDYRCV#
O
R(1)
H(Q)
P(Q)
LOCAL READY/RECOVER, generated by the 80960Rx’s memory controller
unit, is an output version of the READY/RECOVER (RDYRCV#) signal.
Refer to the RDYRCV# signal description.
ADVANCE INFORMATION
11
i960® Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 4 of 5)
NAME
HOLD
TYPE
DESCRIPTION
I
S(L)
HOLD is a request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it
asserts HOLDA, floats the address/data and control lines and enters the Th
state. When HOLD is deasserted, the processor deasserts HOLDA and
enters either the Ti or Ta state, resuming control of the address/data and
control lines. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration
(pg. 61).
0 = No Hold Request
1 = Hold Requested
HOLDA
O
R(0)
H(1)
P(Q)
HOLD ACKNOWLEDGE indicates to an external bus master that the
processor has relinquished bus control. The processor can grant HOLD
requests and enter the Th state and while halted as well as during regular
operation. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration (pg.
61).
0 = No Hold Acknowledged
1 = Hold Acknowledged
RDYRCV#
I
S(L)
READY/RECOVER is only used in systems that use an external memory
controller (and do not use the 80960Rx’s memory controller unit). This signal
indicates that data on AD lines can be sampled or removed. When
RDYRCV# is not asserted during a Td cycle, the Td cycle extends to the next
cycle by inserting a wait state (Tw).
0 = Sample Data
1 = Do Not Sample Data
RDYRCV# has an alternate function during the recovery (Tr) state. The
processor continues to insert recovery states until it samples the signal
HIGH. This gives slow external devices more time to float their buffers
before the processor drives addresses.
0 = Insert Wait States
1 = Recovery Complete
When using the internal memory controller, connect this signal to VCC
through a 2.7 KΩ resistor.
W/R#
WIDTH/
HLTD0
O
R(0)
H(Z)
P(Q)
WRITE/READ specifies during a Ta cycle whether the operation is a write or
read. It is latched on-chip and remains valid during Td cycles.
I/O
R(H)
H(Z)
P(Q)
WIDTH denotes the physical memory attributes for a bus transaction in
conjunction with WIDTH/HLTD1/RETRY:
0 = Read
1 = Write
WIDTH/HLTD1/RETRY
0
0
1
1
WIDTH/HLTD0
0
1
0
1
8 Bits Wide
16 Bits Wide
32 Bits Wide
Undefined
WIDTH/HLTD0 For proper operation, do not connect this signal to ground.
This signal has a weak internal pullup which is active during reset to ensure
normal operation.
HLTD0 signal name has no function in the 80960Rx; the signal name is
included for 80960JF naming convention compatibility.
12
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 5 of 5)
NAME
TYPE
WIDTH/
HLTD1/
RETRY
I/O
R(H)
H(Z)
P(Q)
DESCRIPTION
WIDTH denotes the physical memory attributes for a bus transaction in
conjunction with the WIDTH/HLTD0 signal. Refer to description above.
RETRY is sampled at Primary PCI bus reset to determine when the Primary
PCI interface is disabled. When high, the Primary PCI interface disables PCI
configuration cycles by signaling a RETRY until the Extended Bridge Control
Register’s Configuration Cycle Disable bit is cleared. When low, the Primary
PCI interface allows configuration cycles to occur. WIDTH/HLTD1/RETRY
has a weak internal pullup which is active during reset to ensure normal
operation when the signal is not connected.
HLTD1 signal name has no function in the 80960Rx; the signal name is
included for 80960JF naming convention compatibility.
Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 1 of 2)
NAME
FAIL#
TYPE
O
R(0)
H(Q)
DESCRIPTION
FAIL indicates a failure of the processor’s built-in self-test performed during initialization. FAIL# is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
• When self-test passes, the processor deasserts FAIL# and commences operation
from user code.
• When self-test fails, the processor asserts FAIL# and then stops executing. Selftest failing does not cause the bridge to stop execution.
0 = Self Test Failed
1 = Self Test Passed
L_RST#
O
STEST
I
S(L)
LOCAL BUS RESET notifies external devices that the local bus has reset.
SELF TEST enables or disables the processor’s internal self-test feature at initialization. STEST is examined at the end of P_RST#. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = Self Test Disabled
1 = Self Test Enabled
TCK
I
TEST CLOCK is a CPU input that provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TDI
I
S(L)
TEST DATA INPUT is the serial input signal for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
This signal has a weak internal pullup which is active during reset to ensure normal
operation when the signal is not connected.
TDO
O
R(Q)
H(Q)
P(Q)
TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access
Port. At other times, TDO floats.
TMS
I
S(L)
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of
the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal
pullup which is active during reset to ensure normal operation when the signal is not
connected.
ADVANCE INFORMATION
13
i960® Rx I/O Processor at 3.3 V
Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)
NAME
TRST#
TYPE
DESCRIPTION
I
A(L)
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor (1.5 KΩ) between this signal and VSS. When
TAP is not used, this signal must be connected to VSS; however, no resistor is
required. The signal has a weak internal pullup which must be overcome during reset
to ensure normal operation.
VCC
–
POWER. Connect to a 3.3 Volt VCC board plane.
VCC5
–
5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the 5 V-tolerant
I/O buffers. Connect this signal to +5 V for use with signals which exceed 3.3 V.
When all inputs are from 3.3 V components, connect this signal to 3.3 V.
VSS
–
GROUND. Connect to a VSS board plane.
N.C.
–
NO CONNECT. Do not make electrical connections to these balls.
VCCPLL3:1
I
PLL POWER. For external connection to a 3.3 V VCC board plane. Power to PLLs
requires external filtering.
Table 6. Interrupt Unit Signal Descriptions
TYPE
DESCRIPTION
NMI#
NAME
I
A(L)
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI# is the highest priority interrupt source and is level-detect. When NMI# is
unused, it is recommended that you connect it to VCC .
S_INT[A:D]#/
XINT3:0#
I
A(L)
SECONDARY PCI BUS INTERRUPT1 requests an interrupt. S_INTx# assertion
and deassertion is asynchronous to S_CLK. A device asserts S_INTx# when
requesting attention from its device driver. When S_INTx# is asserted, it remains
asserted until the device driver clears the pending request. S_INTx# Interrupts
are level sensitive.
EXTERNAL INTERRUPT. External devices use this signal to request an interrupt
service. These signals operate in dedicated mode, where each signal is assigned
a dedicated interrupt level.
The S_INT[A:D]#/XINT3:0# signals can be directed as follows:
Sec. PCI
S_INTA#
S_INTB#
S_INTC#
S_INTD#
XINT7:4#
I
A(L)
Primary PCI
⇒
⇒
⇒
⇒
P_INTA#
80960 Core Processor
or
XINT0#
P_INTB#
or
XINT1#
P_INTC#
or
XINT2#
P_INTD#
or
XINT3#
EXTERNAL INTERRUPT. External devices use this signal to request an interrupt
service. These signals operate in dedicated mode, where each signal is assigned
a dedicated interrupt level.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
14
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 1 of 3)
DESCRIPTION1
NAME
TYPE
P_AD31:0
I/O
K(Q)
R(Z)
PRIMARY PCI ADDRESS/DATA is the primary multiplexed PCI address
and data bus.
P_C/BE3:0#
I/O
K(Q)
R(Z)
PRIMARY PCI BUS COMMAND and BYTE ENABLE signals are
multiplexed on the same PCI signals. During an address phase,
P_C/BE3:0# define the bus command. During a data phase, P_C/BE3:0#
are used as byte enables.
P_DEVSEL#
I/O
PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that has
successfully decoded the address. As an input, it indicates whether or not
an agent has been selected.
R(Z)
P_FRAME#
I/O
PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the beginning
and duration of an access on the Primary PCI bus.
R(Z)
P_GNT#
I
R(Z)
PRIMARY PCI BUS GRANT indicates to the agent that access to the bus
has been granted. This is a point-to-point signal.
P_IDSEL
I
S(L)
PRIMARY PCI BUS INITIALIZATION DEVICE SELECT selects the
80960Rx during a Configuration Read or Write command on the primary
PCI bus.
P_INT[A:D]#
O
OD
R(Z)
PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion and
deassertion of P_INTx# is asynchronous to S_CLK. A device asserts its
P_INTx# line when requesting attention from its device driver. Once the
P_INTx# signal is asserted, it remains asserted until the device driver
clears the pending request. P_INTx# Interrupts are level sensitive.
P_IRDY#
I/O
R(Z)
PRIMARY PCI BUS INITIATOR READY indicates the initiating agent’s
(bus master’s) ability to complete the current data phase of the transaction.
P_LOCK#
I
S(L)
PRIMARY PCI BUS LOCK indicates an atomic operation that may require
multiple transactions to complete.
P_PAR
I/O
K(Q)
R(Z)
PRIMARY PCI BUS PARITY. This signal ensures even parity across
P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal.
P_PERR#
I/O
R(Z)
PRIMARY PCI BUS PARITY ERROR is used for reporting data parity
errors during all PCI transactions except a special cycle.
P_REQ#
O
K(Q)
R(Z)
PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent
desires use of the bus. This is a point to point signal.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
ADVANCE INFORMATION
15
i960® Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 2 of 3)
NAME
P_RST#
TYPE
DESCRIPTION1
I
A(L)
PRIMARY RESET brings 80960Rx to a consistent state. When P_RST# is
asserted:
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as P_SERR# are floated.
• S_RST# asserts.
P_RST# may be asynchronous to S_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
P_SERR#
I/O
OD
R(Z)
P_STOP#
I/O
PRIMARY PCI BUS SYSTEM ERROR reports address and data parity
errors on the special cycle command, or any other system error where the
result would be catastrophic.
PRIMARY PCI BUS STOP indicates that the current target is requesting
the master to stop the current transaction on the primary PCI bus.
R(Z)
P_TRDY#
I/O
R(Z)
PRIMARY PCI BUS TARGET READY indicates the target agent's
(selected device's) ability to complete the current data phase of the transaction.
S_AD31:0
I/O
R(0)
SECONDARY PCI ADDRESS/DATA is the secondary multiplexed PCI
address and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
S_C/BE3:0#
I/O
R(0)
SECONDARY PCI BUS COMMAND and BYTE ENABLE signals are
multiplexed on the same PCI signals. During an address phase,
S_C/BE3:0# define the bus command. During a data phase, S_C/BE3:0#
are used as byte enables.
S_DEVSEL#
I/O
R(Z)
SECONDARY PCI BUS DEVICE SELECT is driven by a target agent that
has successfully decoded the address. As an input, it indicates whether or
not an agent has been selected.
S_FRAME#
I/O
R(Z)
SECONDARY PCI BUS CYCLE FRAME is asserted to indicate the
beginning and duration of an access on the Secondary PCI bus.
S_GNT0#/
S_REQ#
O
R(Z)
SECONDARY PCI BUS GRANT0 is a grant signal sent to device 0 on the
secondary PCI bus when the internal Secondary PCI Bus Arbiter is
enabled.
SECONDARY PCI BUS REQUEST is the request signal for the 80960Rx
when the arbiter is disabled.
S_GNT5:1#
O
R(Q)
SECONDARY PCI BUS GRANT are grant signals sent to devices 1-5 on
the secondary PCI bus.
S_IDSEL
I
S(L)
SECONDARY PCI BUS INITIALIZATION DEVICE SELECT selects the
80960Rx during a Configuration Read or Write command on the secondary
PCI bus.
S_IRDY#
I/O
R(Z)
SECONDARY PCI BUS INITIATOR READY indicates the initiating agent's
(bus master's) ability to complete the current data phase of the transaction.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
16
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i960® Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 3 of 3)
NAME
DESCRIPTION1
TYPE
S_LOCK#
I/O
R(Z)
SECONDARY PCI BUS LOCK indicates the need to perform an atomic
operation on the secondary PCI bus.
S_PAR
I/O
R(0)
SECONDARY PCI BUS PARITY. This signal ensures even parity across
S_AD31:0 and S_C/BE3:0. All PCI devices must provide a parity signal.
S_PERR#
I/O
R(Z)
SECONDARY PCI BUS PARITY ERROR is used for reporting data parity
errors during all PCI transactions except a special cycle.
S_REQ0#/
S_GNT#
I
SECONDARY PCI BUS REQUEST0 is a request signal from device 0 on
the secondary PCI bus when the internal Secondary PCI Bus Arbiter is
enabled.
SECONDARY PCI BUS GRANT is the grant signal for the 80960Rx when
the arbiter is disabled.
O
R(Q)
SECONDARY PCI BUS RESET is an output based on P_RST#. It brings
PCI-specific registers, sequencers, and signals to a consistent state. When
P_RST# is asserted, it causes S_RST# to assert, and:
S_RST#
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as S_SERR# are floated.
S_RST# may be asynchronous to S_CLK when asserted or deasserted.
S_SERR#
I/O
OD
R(Z)
SECONDARY PCI BUS SYSTEM ERROR reports address and data parity
errors on the special cycle command, or any other system error where the
result would be catastrophic.
S_STOP#
I/O
R(Z)
SECONDARY PCI BUS STOP indicates that the current target is
requesting the master to stop the current transaction on the secondary PCI
bus.
S_TRDY#
I/O
R(Z)
SECONDARY PCI BUS TARGET READY indicates the target agent's
(selected device's) ability to complete the current data phase of the transaction.
S_REQ4:1#
I
S(L)
SECONDARY PCI BUS REQUEST 4:1 are request signals from devices
1-4 on the secondary PCI bus.
S_REQ5#/
S_ARB_EN
I
S(L)
SECONDARY PCI BUS REQUEST 5 is the request signal from device 5 on
the secondary PCI bus.
SECONDARY PCI BUS ARBITER ENABLE defines the power-up status
of the internal secondary arbitration unit. A valid high at the deassertion of
P_RST# enables the internal secondary arbiter. A valid low at the
deassertion of P_RST# disables the internal secondary arbiter.
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision
2.1 for a more complete definition.
ADVANCE INFORMATION
17
i960® Rx I/O Processor at 3.3 V
Table 8. Memory Controller Signal Descriptions (Sheet 1 of 2)
NAME
CAS7:0#
TYPE
DESCRIPTION
O
R(1)
H(Q)
P(Q)
COLUMN ADDRESS STROBE signals are used for DRAM accesses and are
asserted when the MA11:0 signals contain a valid column address. CAS7:0#
signals are asserted during refresh.
Non-Interleaved Operation:
CAS0#,CAS4# = BE0#
CAS1#,CAS5# = BE1#
CAS2#,CAS6# = BE2#
CAS3#,CAS7# = BE3#
Interleaved Operation:
CAS0# = BE0#
CAS1# = BE1#
CAS2# = BE2#
CAS3# = BE3#
CAS4# = BE0#
CAS5# = BE1#
CAS6# = BE2#
CAS7# = BE3#
lane access
lane access
lane access
lane access
Even leaf lane access
Even leaf lane access
Even leaf lane access
Even leaf lane access
Odd leaf lane access
Odd leaf lane access
Odd leaf lane access
Odd leaf lane access
CE1:0#
O
R(1)
H(Q)
P(Q)
CHIP ENABLE signals indicate an access to one of the two SRAM/ FLASH/
ROM memory banks. CE0# and CE1# are never asserted at the same time.
These signals are valid during the entire memory operation. CE0# is asserted
for accesses to memory bank 0. CE1# is asserted for accesses to memory
bank 1.
DALE1:0
O
R(0)
H(Q)
P(Q)
DRAM ADDRESS LATCH ENABLE signals support external address demultiplexing of the MA11:0 address lines for interleaved DRAM systems. Use
these to directly interface to ‘373’ type latches. These signals are only valid for
accesses to interleaved memory systems. DALE0 is asserted during a valid
even leaf address. DALE1 is asserted during a valid odd leaf address.
DP3:0
I/O
R(X)
H(Q)
P(Q)
DATA PARITY carries the parity information for DRAM accesses. Each parity
bit corresponds to a group of 8 data bus signals as follows:
DP0 — AD7:0
DP1 — AD15:8
DP2 — AD23:16
DP3 — AD31:24
The memory controller generates parity information for local bus writes during
data cycles. During read data cycles, the memory controller checks parity and
provides notification of parity errors on the clock following the data cycle.
Parity checking and polarity are user-programmable. Parity generation and
checking are valid only for data lines that have their associated enable bits
asserted.
DWE1:0#
O
R(1)
H(Q)
P(Q)
DRAM WRITE ENABLE signals distinguish between read and write accesses
to DRAM. DWE1:0# lines are asserted for writes and deasserted for reads.
CAS7:0# determine valid bytes lanes during the access. These two outputs
are functionally equivalent for all DRAM accesses; these provide increased
drive capability for heavily loaded systems.
LEAF1:0#
O
R(1)
H(Q)
P(Q)
LEAF ENABLE signals control the data output enables of the memory system
during an interleaved DRAM read access. Use these to directly interface to
either DRAM or transceiver output enable signals. LEAF0# is asserted during
an even leaf access. LEAF1# is asserted during an odd leaf access.
18
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 8. Memory Controller Signal Descriptions (Sheet 2 of 2)
NAME
MA11:0
TYPE
O
R(X)
H(Q)
P(Q)
DESCRIPTION
MULTIPLEXED ADDRESS signals are multi-purpose depending on the
device that is selected.
For memory banks 0 and 1, these signals output address bits A13:2. These
address bits are incremented for each data transfer of a burst access.
For DRAM bank, these signals output the row/column multiplexed address
bits 11:0. The relationship between the AD31:0 lines and the MA11:0 lines
depends on the bank size, type and arrangement of the DRAM that is
accessed.
MWE3:0#
RAS3:0#
O
R(1)
H(Q)
P(Q)
MEMORY WRITE ENABLE signals for write accesses to SRAM/FLASH
devices. The MWE’s rising edge strobes valid data into these devices.
O
R(1)
H(Q)
P(Q)
ROW ADDRESS STROBE signals are used for DRAM accesses and are
asserted when the MA11:0 signals contain a valid row address. RAS3:0#
always deasserts after the last data transfer in a DRAM access.
MWE0# is asserted for
MWE1# is asserted for
MWE2# is asserted for
MWE3# is asserted for
writes to the BE0# lane
writes to the BE1# lane
writes to the BE2# lane
writes to the BE3# lane
Non-Interleaved Operation:
RAS0# = Bank0 access
RAS1# = Bank1 access
RAS2# = Bank2 access
RAS3# = Bank3 access
Interleaved Operation:
RAS0,2# = Even leaf
RAS1,3# = Odd leaf
Table 9. DMA, APIC, I2C Units Signal Descriptions (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
DACK#
O
R(1)
H(Q)
P(Q)
DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this
signal to indicate (1) it can receive new data from an external device or (2) it
has data to send to an external device.
DREQ#
I
S(L)
DMA DEMAND MODE REQUEST External devices use this signal to indicate
(1) new data is ready for transfer to the DMA controller or (2) buffers are
available to receive data from the DMA controller.
PICCLK
I
PICD1:0
I/O
OD
R(Z)
H(Q)
P(Q)
APIC BUS CLOCK provides synchronous operation of the APIC bus.
APIC DATA lines comprise the data portion of the APIC 3-wire bus.
ADVANCE INFORMATION
19
i960® Rx I/O Processor at 3.3 V
Table 9. DMA, APIC, I2C Units Signal Descriptions (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION
2
SCL
I/O
OD
R(Z)
H(Q)
P(Q)
I C CLOCK provides synchronous I2C bus operation.
SDA
I/O
OD
R(Z)
H(Q)
P(Q)
I2C DATA used for data transfer and arbitration on the I2C bus.
WAIT#
O
R(1)
H(Q)
P(Q)
WAIT is an output that allows the DMA controller to insert wait states during
DMA accesses to an external memory system.
Table 10. Clock Signal
NAME
S_CLK
TYPE
DESCRIPTION
I
SYNCHRONOUS PCI BUS CLOCK Provides the processor’s fundamental time
base. All input/output timings are relative to S_CLK.
Table 11. ICE Signal Descriptions
TYPE
DESCRIPTION
ICEADS#
NAME
O
ICE ADDRESS/DATA STATUS indicates a valid address and the start of a new
bus access. ICEADS# is active for accesses to external microcode.
ICEBRK#
I
ICE BREAK forces the processor to transition from emulation to interrogation
mode.
ICEBUS7:0
I/O
ICE BUS is a bidirectional 8-bit bus linking the processor and the emulator.
Used in various modes.
ICECLK
O
ICE CLOCK output signal to which all ICE bus signals are synchronized.
ICELOCK#
I
ICE LOCK is sampled during 80960 core reset to protect ICE configuration.
ICEMSG#
I
ICE MESSAGE signal used to acknowledge data from the processor to the
emulator. Used only during interrogation mode.
ICESEL#
I
ICESEL enables or disables the ICE unit.
ICEVLD#
O
ICE VALID indicates the processor is driving the ICEBUS with valid data.
MSGFRM#
O
ICE MESSAGE FRAME indicates that trace messages are being issued to the
ICEBUS. Used in emulation mode only.
20
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
3.1.2
352-Lead HL-PBGA Package
Body Size
35 ± 0.10 mm
i960®
i
GC80960RxZZ
FFFFFFFF SS
Q QQQQ
M © ‘9x ‘9x
35 ± 0.10 mm
Ball A1 Corner
1.63 mm
Ball Footprint
31.75 mm
0.63 ± 0.07 mm
Package Height
Ball spacing is 1.27 mm
1.54 ± 0.13 mm
0.91 ± 0.06 mm
Ball width is 0.75 ± 0.15 mm
NOTES:
1. All dimensions and tolerances conform to ANSI Y14.5M 1982.
2. All dimensions are in millimeters.
3. Tin/Lead mix: 63%/37%.
4. Pad plating method: Electrolytic.
5. Encapsulant size: 22.38 x 22.38 mm (max).
Figure 3. 352L HL-PBGA Package Diagram (Top and Side View)
ADVANCE INFORMATION
21
i960® Rx I/O Processor at 3.3 V
AF
AE
AD
AC
AA Y W V
U
T
R
P N M
L
K
J
H G
F
E
D
C
B
A
AB
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
AF
AE
AC
AD
AA Y W V
U
T
R
P N M
L
K
J
H G
F
E
D
C
B
A
AB
Figure 4. 352L HL-PBGA Package Diagram (Bottom View)
22
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet 1 of 4)
Signal
Ball #
Signal
Ball #
Signal
Ball #
AD0
A18
CAS0#
F1
ICESEL#
AC2
AD1
B18
CAS1#
F2
ICEVLD#
AB1
AD2
C17
CAS2#
G3
LEAF0
L2
AD3
A17
CAS3#
G1
LEAF1
M3
AD4
B17
CAS4#
G2
LOCK#/ONCE#
AD4
AD5
C16
CAS5#
H3
LRDYRCV#
C19
AD6
A16
CAS6#
H1
LRST#
AD6
AD7
B16
CAS7#
H2
MA0
C7
AD8
C15
CE0#
L3
MA1
A7
AD9
A15
CE1#
L1
MA2
B7
AD10
B15
D/C#/RST_MODE#
AF4
MA3
C6
AD11
C14
DACK#
AD3
MA4
B6
AD12
A14
DALE0
M1
MA5
C5
AD13
B14
DALE1
M2
MA6
A5
AD14
C13
DEN#
A23
MA7
B5
AD15
A13
DP0
C2
MA8
C4
AD16
B13
DP1
D3
MA9
B4
AD17
C12
DP2
D1
MA10
C3
AD18
A12
DP3
D2
MA11
B3
AD19
B12
DREQ#
AD2
MSGFRM#
AC3
AD20
C11
DT/R#
B23
MWE0#
J3
AD21
A11
DWE0#
K1
MWE1#
J1
AD22
B11
DWE1#
K2
MWE2#
J2
AD23
C10
FAIL#
AD5
MWE3#
K3
AD24
A10
HOLD
V1
NC
A20
AD25
B10
HOLDA
V3
NC
AE4
AD26
C9
ICEADS#
AC1
NC
B20
AD27
A9
ICEBRK#
AA1
NC
C18
AD28
B9
ICEBUS0
V2
NMI#
T3
AD29
C8
ICEBUS1
W3
P_AD0
AD24
AD30
A8
ICEBUS2
W1
P_AD1
AE23
AD31
B8
ICEBUS3
W2
P_AD2
AF23
ADS#
B21
ICEBUS4
Y3
P_AD3
AD23
AE22
ALE
C20
ICEBUS5
Y1
P_AD4
BE0#
A22
ICEBUS6
Y2
P_AD5
AF22
BE1#
B22
ICEBUS7
AA3
P_AD6
AD22
BE2#
C21
ICECLK
AB2
P_AD7
AE21
BE3#
A21
ICELOCK#
AB3
P_AD8
AD21
BLAST#
C23
ICEMSG#
AA2
P_AD9
AE20
ADVANCE INFORMATION
23
i960® Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet 2 of 4)
24
Signal
Ball #
Signal
Ball #
Signal
Ball #
P_AD10
AF20
P_RST#
AE7
S_AD27
K24
P_AD11
AD20
P_SERR#
AE17
S_AD28
K26
P_AD12
AE19
P_STOP#
AE16
S_AD29
K25
P_AD13
AF19
P_TRDY#
AD16
S_AD30
J24
P_AD14
AD19
PICCLK
U3
S_AD31
J26
P_AD15
AE18
PICD0
T1
S_C/BE0#
AA24
P_AD16
AE14
PICD1
T2
S_C/BE1#
V24
P_AD17
AF14
RAS0#
E3
S_C/BE2#
R26
P_AD18
AD14
RAS1#
E1
S_C/BE3#
M25
P_AD19
AE13
RAS2#
E2
S_CLK
F25
P_AD20
AF13
RAS3#
F3
S_DEVSEL#
T24
P_AD21
AD13
RDYRCV#
B19
S_FRAME#
R24
P_AD22
AE12
S_AD0
AE24
S_GNT0#/S_REQ#
H26
P_AD23
AF12
S_AD1
AD25
S_GNT1#
G24
P_AD24
AF11
S_AD2
AC24
S_GNT2#
G25
P_AD25
AD11
S_AD3
AC26
S_GNT3#
F26
P_AD26
AE10
S_AD4
AC25
S_GNT4#
E26
P_AD27
AF10
S_AD5
AB24
S_GNT5#
D24
P_AD28
AD10
S_AD6
AB26
S_IDSEL
M26
P_AD29
AE9
S_AD7
AB25
S_INTA#/XINT0#
N1
P_AD30
AF9
S_AD8
AA26
S_INTB#/XINT1#
N2
P_AD31
AD9
S_AD9
AA25
S_INTC#/XINT2#
P3
P_C/BE0#
AF21
S_AD10
Y24
S_INTD#/XINT3#
P1
P_C/BE1#
AF18
S_AD11
Y26
S_IRDY#
T25
P_C/BE2#
AD15
S_AD12
Y25
S_LOCK#
U26
P_C/BE3#
AE11
S_AD13
W24
S_PAR
V26
P_DEVSEL#
AF16
S_AD14
W26
S_PERR#
U24
P_FRAME#
AF15
S_AD15
W25
S_REQ0#/S_GNT#
H24
P_GNT#
AF8
S_AD16
R25
S_REQ1#
H25
P_IDSEL
AD12
S_AD17
P24
S_REQ2#
G26
P_INTA#
AF6
S_AD18
P26
S_REQ3#
F24
P_INTB#
AE6
S_AD19
P25
S_REQ4#
E24
P_INTC#
AD7
S_AD20
N24
S_REQ5#/S_ARB_EN
E25
P_INTD#
AF7
S_AD21
N26
S_RST#
J25
P_IRDY#
AE15
S_AD22
N25
S_SERR#
V25
P_LOCK#
AD17
S_AD23
M24
S_STOP#
U25
P_PAR
AD18
S_AD24
L24
S_TRDY#
T26
P_PERR#
AF17
S_AD25
L26
SCL
U1
P_REQ#
AE8
S_AD26
L25
SDA
U2
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet 3 of 4)
Signal
Ball #
Signal
Ball #
Signal
Ball #
STEST
AE3
VCC
B25
V SS
AC7
TCK
B24
VCC
B26
VSS
AC9
TDI
D26
VCC
C1
VSS
AC11
TDO
D25
VCC
C26
V SS
AC13
TMS
C24
VCC
D5
V SS
AC15
TRST#
C25
VCC
D7
V SS
AC17
VCC
A1
VCC
D9
V SS
AC19
V CC
A2
VCC
D11
V SS
AC21
V CC
A24
VCC
D13
V SS
AC23
V CC
A25
VCC
D15
V SS
D4
V CC
A26
VCC
D17
V SS
D6
V CC
AA23
VCC
D19
V SS
D8
V CC
AB4
VCC
D21
V SS
D10
V CC
AC6
VCC
E23
VSS
D12
V CC
AC8
VCC
F4
VSS
D14
V CC
AC10
VCC
G23
VSS
D16
V CC
AC12
VCC
H4
VSS
D18
V CC
AC14
VCC
J23
VSS
D20
V CC
AC16
VCC
K4
VSS
D22
V CC
AC18
VCC
L23
VSS
D23
V CC
AC20
VCC
M4
VSS
E4
V CC
AC22
VCC
N23
VSS
F23
V CC
AD1
VCC
P4
V SS
G4
VCC /VSS (1)
AD8
VCC
R23
V SS
H23
V CC
AD26
VCC
T4
VSS
J4
V CC
AE1
VCC
U23
V SS
K23
VCC
AE2
VCC
V4
VSS
L4
VCC
AE25
VCC
W23
V SS
M23
VCC
AE26
VCC
Y4
V SS
N4
VCC
AF1
VCC5
A3
V SS
P23
VCC
AF2
VCCPLL1
A19
V SS
R4
VCC
AF3
VCCPLL2
A6
V SS
T23
VCC
AF24
VCCPLL3
A4
V SS
U4
VCC
AF25
VSS
AA4
V SS
V23
VCC
AF26
VSS
AB23
V SS
W4
VCC
B1
VSS
AC4
V SS
Y23
V CC
B2
VSS
AC5
W/R#
C22
NOTES:
1. Ball AD8 must be tied to either VCC or VSS.
ADVANCE INFORMATION
25
i960® Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet 4 of 4)
Signal
Ball #
Signal
Ball #
Signal
Ball #
WAIT#
N3
XINT4#
P2
XINT7#
R2
WIDTH/HLTD0
AF5
XINT5#
R3
WIDTH/HLTD1/RETRY
AE5
XINT6#
R1
26
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet 1 of 4)
Ball #
Signal
Ball #
Signal
Ball #
Signal
A1
V CC
B10
AD25
C19
LRDYRCV#
A2
V CC
B11
AD22
C20
ALE
A3
VCC5
B12
AD19
C21
BE2#
A4
VCCPLL3
B13
AD16
C22
W/R#
A5
MA6
B14
AD13
C23
BLAST#
A6
VCCPLL2
B15
AD10
C24
TMS
A7
MA1
B16
AD7
C25
TRST#
A8
AD30
B17
AD4
C26
VCC
A9
AD27
B18
AD1
D1
DP2
A10
AD24
B19
RDYRCV#
D2
DP3
A11
AD21
B20
NC
D3
DP1
A12
AD18
B21
ADS#
D4
VSS
A13
AD15
B22
BE1#
D5
VCC
A14
AD12
B23
DT/R#
D6
VSS
A15
AD9
B24
TCK
D7
VCC
A16
AD6
B25
VCC
D8
VSS
A17
AD3
B26
VCC
D9
VCC
A18
AD0
C1
VCC
D10
V SS
A19
VCCPLL1
C2
DP0
D11
VCC
A20
NC
C3
MA10
D12
V SS
A21
BE3#
C4
MA8
D13
VCC
A22
BE0#
C5
MA5
D14
V SS
A23
DEN#
C6
MA3
D15
VCC
A24
VCC
C7
MA0
D16
V SS
A25
VCC
C8
AD29
D17
VCC
A26
VCC
C9
AD26
D18
V SS
B1
V CC
C10
AD23
D19
VCC
B2
V CC
C11
AD20
D20
V SS
B3
MA11
C12
AD17
D21
VCC
B4
MA9
C13
AD14
D22
V SS
B5
MA7
C14
AD11
D23
V SS
B6
MA4
C15
AD8
D24
S_GNT5#
B7
MA2
C16
AD5
D25
TDO
B8
AD31
C17
AD2
D26
TDI
B9
AD28
C18
NC
E1
RAS1#
ADVANCE INFORMATION
27
i960® Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet 2 of 4)
Ball #
Signal
Ball #
E2
RAS2#
E3
RAS0#
E4
E23
E24
E25
E26
S_GNT4#
F1
F2
28
Signal
Ball #
J23
VCC
N26
S_AD21
J24
S_AD30
P1
S_INTD#/XINT3#
VSS
J25
S_RST#
P2
XINT4#
VCC
J26
S_AD31
P3
S_INTC#/XINT2#
S_REQ4#
K1
DWE0#
P4
VCC
S_REQ5#/S_ARB_EN
K2
DWE1#
P23
VSS
K3
MWE3#
P24
S_AD17
CAS0#
K4
VCC
P25
S_AD19
CAS1#
K23
VSS
P26
S_AD18
F3
RAS3#
K24
S_AD27
R1
XINT6#
F4
VCC
K25
S_AD29
R2
XINT7#
F23
VSS
K26
S_AD28
R3
XINT5#
F24
S_REQ3#
L1
CE1#
R4
VSS
F25
S_CLK
L2
LEAF0#
R23
VCC
F26
S_GNT3#
L3
CE0#
R24
S_FRAME#
G1
CAS3#
L4
VSS
R25
S_AD16
G2
CAS4#
L23
VCC
R26
S_C/BE2#
G3
CAS2#
L24
S_AD24
T1
PICD0
G4
VSS
L25
S_AD26
T2
PICD1
G23
VCC
L26
S_AD25
T3
NMI#
G24
S_GNT1#
M1
DALE0
T4
V CC
G25
S_GNT2#
M2
DALE1
T23
VSS
G26
S_REQ2#
M3
LEAF1#
T24
S_DEVSEL#
H1
CAS6#
M4
VCC
T25
S_IRDY#
H2
CAS7#
M23
VSS
T26
S_TRDY#
H3
CAS5#
M24
S_AD23
U1
SCL
H4
VCC
M25
S_C/BE3#
U2
SDA
H23
V SS
M26
S_IDSEL
U3
PICCLK
H24
S_REQ0#/S_GNT#
N1
S_INTA#/XINT0#
U4
VSS
H25
S_REQ1#
N2
S_INTB#/XINT1#
U23
VCC
H26
S_GNT0#/S_REQ#
N3
WAIT#
U24
S_PERR#
J1
MWE1#
N4
VSS
U25
S_STOP#
J2
MWE2#
N23
VCC
U26
S_LOCK#
J3
MWE0#
N24
S_AD20
V1
HOLD
J4
VSS
N25
S_AD22
V2
ICEBUS0
Signal
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet 3 of 4)
Ball #
Signal
Ball #
Signal
Ball #
Signal
V3
HOLDA
AB4
VCC
AD3
DACK#
V4
VCC
AB23
VSS
AD4
LOCK#/ONCE#
V23
VSS
AB24
S_AD5
AD5
FAIL#
V24
S_C/BE1#
AB25
S_AD7
AD6
LRST#
V25
S_SERR#
AB26
S_AD6
AD7
P_INTC#
V26
S_PAR
AC1
ICEADS#
AD8
VCC/VSS (1)
W1
ICEBUS2
AC2
ICESEL#
AD9
P_AD31
W2
ICEBUS3
AC3
MSGFRM#
AD10
P_AD28
W3
ICEBUS1
AC4
VSS
AD11
P_AD25
W4
VSS
AC5
VSS
AD12
P_IDSEL
W23
V CC
AC6
VCC
AD13
P_AD21
W24
S_AD13
AC7
VSS
AD14
P_AD18
W25
S_AD15
AC8
VCC
AD15
P_C/BE2#
W26
S_AD14
AC9
VSS
AD16
P_TRDY#
Y1
ICEBUS5
AC10
VCC
AD17
P_LOCK#
Y2
ICEBUS6
AC11
VSS
AD18
P_PAR
Y3
ICEBUS4
AC12
VCC
AD19
P_AD14
Y4
V CC
AC13
VSS
AD20
P_AD11
Y23
VSS
AC14
VCC
AD21
P_AD8
Y24
S_AD10
AC15
VSS
AD22
P_AD6
Y25
S_AD12
AC16
VCC
AD23
P_AD3
Y26
S_AD11
AC17
VSS
AD24
P_AD0
AA1
ICEBRK#
AC18
VCC
AD25
S_AD1
AA2
ICEMSG#
AC19
VSS
AD26
VCC
AA3
ICEBUS7
AC20
VCC
AE1
VCC
AA4
VSS
AC21
VSS
AE2
VCC
AA23
V CC
AC22
VCC
AE3
STEST
AA24
S_C/BE0#
AC23
VSS
AE4
NC
AA25
S_AD9
AC24
S_AD2
AE5
WIDTH/HLTD1/RETRY
AA26
S_AD8
AC25
S_AD4
AE6
P_INTB#
AB1
ICEVLD#
AC26
S_AD3
AE7
P_RST#
AB2
ICECLK
AD1
VCC
AE8
P_REQ#
AB3
ICELOCK#
AD2
DREQ#
AE9
P_AD29
NOTES:
1. Ball AD8 must be tied to either VCC or VSS.
ADVANCE INFORMATION
29
i960® Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet 4 of 4)
Ball #
Signal
Ball #
Signal
Ball #
Signal
AE10
P_AD26
AE25
VCC
AF14
P_AD17
AE11
P_C/BE3#
AE26
VCC
AF15
P_FRAME#
AE12
P_AD22
AF1
VCC
AF16
P_DEVSEL#
AE13
P_AD19
AF2
VCC
AF17
P_PERR#
AE14
P_AD16
AF3
VCC
AF18
P_C/BE1#
AE15
P_IRDY#
AF4
D/C#/RST_MODE#
AF19
P_AD13
AE16
P_STOP#
AF5
WIDTH/HLTD0
AF20
P_AD10
AE17
P_SERR#
AF6
P_INTA#
AF21
P_C/BE0#
AE18
P_AD15
AF7
P_INTD#
AF22
P_AD5
AE19
P_AD12
AF8
P_GNT#
AF23
P_AD2
AE20
P_AD9
AF9
P_AD30
AF24
VCC
AE21
P_AD7
AF10
P_AD27
AF25
VCC
AE22
P_AD4
AF11
P_AD24
AF26
VCC
AE23
P_AD1
AF12
P_AD23
AE24
S_AD0
AF13
P_AD20
30
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
3.2
Package Thermal Specifications
The device is specified for operation when TC (case
temperature) is within the range of 0° C to 95° C.
Case temperature may be measured in any
environment to determine whether the processor is
within specified operating range. Measure the case
temperature at the center of the top surface,
opposite the ballpad.
3.2.1
Thermal Specifications
This section defines the terms used for thermal
analysis.
• Attach the thermocouple bead or junction at a 90°
angle by an adhesive bond (such as thermal epoxy
or heat-tolerant tape) to the package top surface
as shown in Figure 5. When a heat sink is
attached, drill a hole through the heat sink to allow
contact with the package above the center of the
die. The hole diameter should be no larger than
3.8 mm as shown in Figure 6.
Thermocouple Wire
Thermocouple Bead
Epoxy Fillet
3.2.1.1 Ambient Temperature
Ambient temperature, TA, is the temperature of the
ambient air surrounding the package. In a system
environment, ambient temperature is the temperature of the air upstream from the package.
Figure 5. Thermocouple Attachment No Heat Sink
Thermocouple
3.2.1.2 Case Temperature
3.8 mm Diameter Hole
Heat Sink
To ensure functionality and reliability, the device is
specified for proper operation when the case
temperature, TC, is within the specified range in
Table 16, Operating Conditions (pg. 34).
When measuring case temperature, attention to
detail is required to ensure accuracy. If a thermocouple is used, calibrate it before taking measurements. Errors may result when the measured
surface temperature is affected by the surrounding
ambient air temperature. Such errors may be due to
a poor thermal contact between thermocouple
junction and the surface, heat loss by radiation, or
conduction through thermocouple leads.
To minimize measurement errors:
• Use a 35 gauge K-type thermocouple or equivalent.
Figure 6. Thermocouple Attachment With Heat Sink
3.2.1.3 Thermal Resistance
The thermal resistance value for the case-toambient, θCA, is used as a measure of the cooling
solution’s thermal performance.
• Attach the thermocouple bead or junction to the
package top surface at a location corresponding to
the center of the die (Figure 5). The center of the
die gives a more accurate measurement and less
variation as the boundary condition changes.
ADVANCE INFORMATION
31
i960® Rx I/O Processor at 3.3 V
3.2.2
Compute P by multiplying ICC and VCC. Valuesfor
θJC and θCA are given in Table 14.
Thermal Analysis
This thermal analysis is based on the following
assumptions:
Junction temperature (TJ ) is commonly used in
reliability calculations. TJ can be calculated from θJC
(thermal resistance from junction to case) using the
following equation:
• Power dissipation is a constant 5 W.
• Maximum case temperature is 95° C.
Table 14 lists the case-to-ambient thermal resistances of the 80960RP for different air flow rates
with and without a heat sink.
TJ = TC + P (θJC )
Similarly, when TA is known, the corresponding case
temperature (TC) can be calculated as follows:
To calculate TA, the maximum ambient temperature
to conform to a particular case temperature:
TC = TA + P (θCA)
The θJA (Junction to Ambient) for this package is
currently estimated at 9.74° C/Watt with no airflow.
TA = TC - P (θCA)
θJA = θJC + θCA
Table 14. 352-Lead HL-PBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
50
(0.25)
100
(0.50)
200
(1.01)
300
(1.52)
400
(2.03)
600
(3.04)
800
(4.06)
θJC (Junction-to-Case)
0.60
0.60
0.60
0.60
0.60
0.60
0.60
0.60
θCA (Case-to-Ambient)
Without Heatsink
9.14
7.64
6.58
6.11
5.79
5.61
5.49
5.47
θCA (Case-to-Ambient)
With Heatsink2
7.31
6.00
5.21
4.80
4.52
4.37
4.26
4.23
θJA
θCA
θJC
NOTES:
1. This table applies to a HL-PBGA device soldered directly onto a board.
2. See Table 15 for heatsink information.
32
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
3.3
Sources for Heatsinks and Accessories
The following is a list of suggested sources for heatsinks and accessories. This is neither an endorsement nor
a warranty of the performance of any of the listed products and/or companies.
Table 15. Heatsink Information
Manufacturer
Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
Tel: (214) 243-4321
FAX: (214) 241-4656
Part No.
Heatsink: 2338B
BGA Clip: 20812-2
32 X 34 X 12.6
T705
NA
Heatsink:
364424B00032
40.5 X 40 X 11
Parker Chromerics
77 Dragon Court
Woburn, MA 01888
Tel: (617) 935-4850
FAX: (617) 933-4318
AAVID Thermal Technologies, Inc.
One Kool Path
P.O. Box 400
Laconia, N.H. 13247-0400
Tel: (603) 528-3400
FAX: (603) 527-2129
Heatsink
Dimensions
(mm)
ADVANCE INFORMATION
Product Description
Thermalloy Heatsink;
use with BGA Clip and
Parker Chromerics
Thermflow tape
Thermflow tape;
use with Thermalloy BGA
Clip
AAVID Heatsink;
use with pre-applied thermal
adhesive tape
(Ther-A-Grip)
33
i960® Rx I/O Processor at 3.3 V
4.0
ELECTRICAL SPECIFICATIONS
4.1
Absolute Maximum Ratings
Parameter
Maximum Rating
–55° C to + 125° C
Storage Temperature
Case Temperature Under Bias
0° C to + 95° C
–0.5 V to + 4.6 V
Supply Voltage wrt. VSS
Supply Voltage wrt. VSS on VCC5 –0.5 V to + 6.5 V
NOTICE: This data sheet contains information on
products in the sampling and initial production
phases of development. The specifications are
subject to change without notice. Contact your
local Intel representative before finalizing a design.
WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.
–0.5 V to VCC + 0.5 V
Voltage on Any Ball wrt. VSS
Table 16. Operating Conditions
Symbol
Parameter
Min
Max
Units
VCC
Supply Voltage
3.0
3.6
V
VCC5
Input Protection Bias
3.0
5.25
V
FS_CLK
Input Clock Frequency
16
33.33
MHz
TC
Case Temperature Under Bias
GC80960Rx (352 HL-PBGA)
0
95
°C
4.2
VCC5 Pin Requirements (V DIFF)
In mixed voltage systems that drive 80960Rx
processor inputs in excess of 3.3 V, the VCC5 pin
must be connected to the system’s 5 V supply. To
limit current flow into the VCC5 pin, there is a limit to
the voltage differential between the VCC5 pin and the
other VCC pins. The voltage differential between the
80960Rx VCC5 pin and its 3.3 V VCC pins should
never exceed 2.25 V. This limit applies to power-up,
power-down, and steady-state operation. Table 17
outlines this requirement.
Meeting this requirement ensures proper operation
and guarantees that the current draw into the VCC5
pin does not exceed the ICC5 specification.
If the voltage difference requirements cannot be met
due to system design limitations, an alternate
solution may be employed. As shown in Figure 7, a
minimum of 100 Ω series resistor may be used to
Notes
limit the current into the VCC5 pin. This resistor
ensures that current drawn by the VCC5 pin does not
exceed the maximum rating for this pin.
+5 V (±0.25 V)
VCC5 Pin
100 Ω
(±5%, 0.5 W)
Figure 7. VCC5 Current-Limiting Resistor
This resistor is not necessary in systems that can
guarantee the VDIFF specification.
In 3.3 V-only systems and systems that drive
80960Rx pins from 3.3 V logic, connect the VCC5 pin
directly to the 3.3 V VCC plane.
Table 17. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Symbol
VDIFF
34
Parameter
VCC5-VCC
Difference
Min
Max
Units
Notes
2.25
V
VCC5 input should not exceed VCC by more than 2.25 V
during power-up and power-down, or during steady-state
operation.
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
4.3
Targeted DC Specifications
Table 18. DC Characteristics
Symbol
Parameter
Min
Max
Units
Notes
VIL
Input Low Voltage
-0.5
0.8
V
(1)
VIH1
Input High Voltage for all signals
except SCLK
2.0
VCC + 0.5
V
(1)
VIH2
Input High Voltage for SCLK
2.1
VCC + 0.5
V
(1)
VOL1
Output Low Voltage Processor signals
VOH1
Output High Voltage Processor signals
VOL2
Output Low Voltage PCI signals
VOH2
Output High Voltage PCI signals
VOL3
Output Low Voltage Memory Controller
Normal drive
VOH3
Output High Voltage Memory
Controller Normal drive
VOL4
Output Low Voltage Memory Controller
High Drive
VOH4
Output High Voltage Memory
Controller High Drive
VOL5
Output Low Voltage APIC Data Lines
0.45
2.4
VCC - 0.5
0.55
V
IOL = 6 mA (3)
V
IOH = -2 mA (3)
IOH = -200 µA (3)
V
IOL = 6 mA (1)
V
IOH = -2 mA (1)
V
IOL = 6 mA (4)
V
IOH = -2 mA (4)
V
IOL = 7 mA
V
IOH = -2 mA
0.45
V
IOL = 10 mA
2.4
0.45
2.4
0.45
2.4
CIN
Input Capacitance - HL-PBGA
10
pF
FS_CLK = TF Min (1, 2)
COUT
I/O or Output Capacitance - HL-PBGA
10
pF
FS_CLK = TF Min (1, 2)
CCLK
S_CLK Capacitance - HL-PBGA
CIDSEL
IDSEL Ball Capacitance
LPIN
Ball Inductance
5
12
pF
FS_CLK = TF Min (1, 2)
8
pF
(1)
20
nH
(1)
NOTES:
1. As required by the PCI Local Bus Specification Revision 2.1.
2. Not tested.
3. Processor signals include AD31:0, ALE, ADS#, BE3:0#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#,
W/R#, DT/R#, DEN#, BLAST#, LRDYRCV#, LOCK#/ONCE#, HOLD, FAIL#, TDO, DACK#, WAIT#, SDA, SCL.
4. Memory Controller signals include MA11:0, DP3:0, RAS3:0#, CAS7:0#, MWE3:0#, DWE1:0#, DALE1:0, CE1:0#,
LEAF1:0#.
5. Memory Controller signals capable of high drive are MA11:0, CAS7:0#, RAS3:0#, DWE1:0#.
ADVANCE INFORMATION
35
i960® Rx I/O Processor at 3.3 V
Table 19. ICC Characteristics
Symbol
Parameter
Typ
Max
Units
Notes
± 80
µA
0 ≤ VIN ≤ VCC
-250
µA
VIN = 0.45 V (1)
ILI1
Input Leakage Current for each signal except
PCI Bus Signals, LOCK#/ONCE#,
WIDTH/HLTD0, WIDTH/HLTD1/RETRY,
BLAST#, D/C#/RST_MODE#, DEN#,TMS,
TRST#, TDI
ILI2
Input Leakage Current for LOCK#/ONCE#,
WIDTH/HLTD0, WIDTH/HLTD1/RETRY,
BLAST#, D/C#/RST_MODE#, DEN#, TMS,
TRST#, TDI
ILI3
Input Leakage Current for PCI Bus Signals
±5
µA
0 ≤ VIN ≤ VCC
ILO
Output Leakage Current
±5
µA
0.4 ≤ VOUT ≤ VCC
-140
ICC Active
Power Supply Current
80960RP 33/3.3
(Power Supply)
80960RD 66/3.3
ICC Active
(Thermal)
Thermal Current
80960RP 33/3.3
80960RD 66/3.3
A
(1,2)
A
(1,3)
A
(4)
(4)
1.00
1.30
0.75
0.95
Reset Mode
ICC Active
80960RP 33/3.3
(Power Modes)
80960RD 66/3.3
0.65
0.80
ONCE Mode
80960RP 33/3.3
80960RD 66/3.3
0.02
0.02
NOTES:
1. Measured with device operating and outputs loaded to the test condition in Figure 8.
2. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using one of the
worst case instruction mixes with VCC = 3.6 V and ambient temperature = 55 ° C. This parameter is characterized but not
tested.
3. ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with VCC = 3.3 V
and ambient temperature = 55 ° C. This parameter is characterized but not tested.
4. ICC Active (Power modes) refers to the ICC values that are tested when the device is in Reset mode or ONCE mode with
VCC = 3.6 V and ambient temperature = 55 ° C.
36
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
4.4
Targeted AC Specifications
Table 20. Input Clock Timings
Symbol
Parameter
Min
Max
Units
Notes
TF
S_CLK Frequency
16
33.33
MHz
TC
S_CLK Period
30
62.5
ns
(1)
±250
ps
Adjacent Clocks (2,3)
ns
Measured at 1.5 V (2,3)
TCS
S_CLK Period Stability
TCH
S_CLK High Time
12
TCL
S_CLK Low Time
12
TCR
S_CLK Rise Time
4
V/ns
0.4 V to 2.4 V (2,3)
TCF
S_CLK Fall Time
4
V/ns
2.4 V to 0.4 V (2,3)
ns
Measured at 1.5 V (2,3)
NOTES:
1. See Figure 9.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum
should not have any power peaking between 500 KHz and 1/3 of the S_CLK frequency.
3. Not tested.
Table 21. Synchronous Output Timings
Symbol
Parameter
Min
Max
Units
3
15.5
ns
(1,2,5)
ns
(2,5)
11
ns
(2,5)
2
12
ns
(2,5)
Output Valid Delay - DP3:0
3
19
ns
(2,5)
Output Float Delay
3
13
ns
(3,4,5)
TOV1
Output Valid Delay - All Local Bus Signals Except
ALE Inactive and DT/R#
TOV2
Output Valid Delay, DT/R#
TOV3
Output Valid Delay - PCI Signals Except P_REQ#,
S_GNT0#/S_REQ#, and S_GNT5:1#
2
TOV4
Output Valid Delay P_REQ#, S_GNT0#/S_REQ#,
and S_GNT5:1#
TOV5
TOF
0.5 TC +3 0.5 TC +15
Notes
NOTES:
1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see Table 23, Relative Output Timings (pg. 39).
2. See Figure 10, TOV Output Delay Waveform (pg. 45).
3. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is designed to be no
longer than the valid delay.
4. See Figure 11, TOF Output Float Waveform (pg. 45).
5. Outputs precharged to VCC5 maximium.
ADVANCE INFORMATION
37
i960® Rx I/O Processor at 3.3 V
Table 22. Synchronous Input Timings
Sym
Parameter
Min Max
Units
Notes
TIS1
Input Setup to S_CLK — NMI#, XINT7:4#, S_INT[A:D]#/XINT3:0#,
DP3:0#
6
ns
(1,2)
TIS1A
Input Setup to S_CLK — for all accesses except Expansion ROM
Accesses — AD31:0 only
6
ns
(1,2)
TIS1B
Input Setup to S_CLK during Expansion ROM Accesses —
AD31:0 only
8
ns
(1,2)
TIH1
Input Hold from S_CLK — AD31:0, NMI#, XINT7:4#,
S_INT[A:D]#/XINT3:0#, DP3:0#
2
ns
(1,2,4)
TIS2
Input Setup to S_CLK — RDYRCV# and HOLD
10
ns
(2)
TIH2
Input Hold from S_CLK — RDYRCV# and HOLD
2
ns
(2)
TIS3
Input Setup to S_CLK — LOCK#/ONCE#, STEST
7
ns
(1,2)
TIH3
Input Hold from S_CLK — LOCK#/ONCE#, STEST
3
ns
(1,2)
TIS4
Input Setup to S_CLK — DREQ#
12
ns
(2)
TIH4
Input Hold from S_CLK — DREQ#
7
ns
(2)
TIS5
Input Setup to S_CLK — PCI Signals Except P_GNT#,
S_REQ0#/S_GNT#, and S_REQ5:1#
7
ns
(2)
TIH5
Input Hold from S_CLK — PCI Signals
0
ns
(2,4)
TIS6
Input Setup to S_CLK — P_RST#
6
ns
(2,3)
TIH6
Input Hold to S_CLK — P_RST#
2
ns
(2,3)
TIS7
Input Setup to S_CLK — P_GNT#
10
ns
(2)
TIS8
Input Setup to S_CLK — S_REQ0#/S_GNT# and S_REQ5:1#
12
ns
(2)
TIS9
Input Setup to P_RST# —
WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#
7
ns
(1,2,4)
TIH9
Input Hold from P_RST# —
WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#
3
ns
(1,2,4)
NOTES:
1. Setup and hold times must be met for proper processor operation. NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# may be
synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge.
For asynchronous operation, NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# must be asserted for a minimum of two S_CLK
periods to guarantee recognition.
2. See Figure 12, TIS and TIH Input Setup and Hold Waveform (pg. 46).
3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge.
4. Guaranteed by design. May not be 100% tested.
38
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
4.4.1
Relative Output Timings
Table 23. Relative Output Timings
Symbol
Parameter
Min
Max
Units
Notes
TLXL
ALE Width
0.5TC-3
ns
(1,2,4)
TLXA
Address Hold from ALE Inactive
0.5TC-3
ns
Equal Loading (1,2,4)
TDXD
DT/R# Valid to DEN# Active
0.5TC-3
ns
Equal Loading (1,3,4)
NOTES:
1. Guaranteed by design. May not be 100% tested.
2. See Figure 13.
3. See Figure 14.
4. Outputs precharged to VCC5 maximium.
4.4.2
Memory Controller Relative Output Timings
Table 24. Fast Page Mode Non-interleaved DRAM Output Timings
Min
Max
Units
Notes
TOV6
Symbol
RAS3:0# Rising and Falling edge Output Valid
Delay
Description
2
9
ns
2
TOV7
CAS7:0# Rising Edge Output Valid Delay
2
8
ns
2
TOV8
CAS7:0# Falling Edge Output Valid Delay
0.5Tc+2
0.5Tc+8
ns
1,2
TOV9
MA11:0 Output Valid Delay-Row Address
0.5Tc+2
0.5Tc+10
ns
1,2
TOV10
MA11:0 Output Valid Delay-Column Address
2
10
ns
2
TOV11
DWE1:0# Rising and Falling edge Output Valid
Delay
2
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between VCC3 maximium and VSS.
ADVANCE INFORMATION
39
i960® Rx I/O Processor at 3.3 V
Table 25. Fast Page Mode Interleaved DRAM Output Timings
Symbol
Description
Min
Max
Units
Notes
TOV12
RAS3:0# Rising and Falling edge Output Valid Delay
2
9
ns
2
TOV13
CAS7:0# Rising Edge Output Valid Delay
2
8
ns
2
TOV14
CAS7:0# Falling Edge Output Valid Delay
0.5Tc+2
0.5Tc+8
ns
1,2
TOV15
MA11:0 Output Valid Delay-Row Address
0.5Tc+2
0.5Tc+10
ns
1,2
TOV16
MA11:0 Output Valid Delay-Column Address
2
10
ns
2
TOV17
DWE1:0# Rising and Falling Edge Output Valid Delay
2
11
ns
2
TOV18
DALE1:0 Initial Falling Edge Output Valid Delay
2
10
ns
2
TOV19
DALE1:0 Burst Falling Edge Output Valid Delay
0.5Tc+2
0.5Tc+10
ns
1,2
TOV20
DALE1:0 Rising Edge Output Valid Delay
2
10
ns
2
TOV21
LEAF1:0# Rising and Falling Edge Output Valid
Delay
2
10
ns
2
NOTE:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between VCC3 maximium and VSS.
Table 26. EDO DRAM Output Timings
Symbol
Description
Min
Max
Units Notes
TOV22
RAS3:0# Rising and Falling Edge Output Valid Delay
2
9
ns
2
TOV23
CAS7:0# Rising Edge Output Valid Delay Read Cycles
0.5Tc+2
0.5Tc+8
ns
1,2
TOV24
CAS7:0# Falling Edge Output Valid Delay Read Cycles
2
8
ns
2
TOV25
CAS7:0# Rising Edge Output Valid Delay Write Cycles
2
8
ns
2
TOV26
CAS7:0# Falling Edge Output Valid Delay Write Cycles
0.5Tc+2
0.5Tc+8
ns
1,2
TOV27
MA11:0 Output Valid Delay - Row Address
0.5Tc+2
0.5Tc+10
ns
1,2
TOV28
MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc+2
0.5Tc+10
ns
1,2
TOV29
MA11:0 Output Valid Delay - Column Address Write Cycles
2
10
ns
2
TOV30
DWE1:0# Rising and Falling Edge Output Valid Delay
2
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between VCC3 maximium and VSS.
40
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 27. BEDO DRAM Output Timings
Symbol
Description
Min
Max
Units
Notes
2
9
ns
2
CAS7:0# Rising Edge Output Valid Delay - Read Cycles
0.5Tc+2
0.5Tc+8
ns
1,2
CAS7:0# Falling Edge Output Valid Delay - Read Cycles
2
8
ns
2
2
8
ns
2
0.5Tc+2
0.5Tc+8
ns
1,2
0.5Tc +2 0.5Tc+10
ns
1,2
MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc +2 0.5Tc+10
ns
1,2
TOV31
RAS3:0# Rising and Falling Edge Output Valid Delay
TOV32
TOV33
TOV34
CAS7:0# Rising Edge Output Valid Delay - Write Cycles
TOV35
CAS7:0# Falling Edge Output Valid Delay - Write Cycles
TOV36
MA11:0 Output Valid Delay - Row Address
TOV37
TOV38
MA11:0 Output Valid Delay - Column Address Write Cycles
2
10
ns
2
TOV39
DWE1:0# Rising and Falling Edge Output Valid Delay
2
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between VCC3 maximium and VSS.
Table 28. SRAM/ROM Output Timings
Description
Min
Max
Units
Notes
TOV40
Symbol
CE1:0# Rising and Falling Edge Output Valid Delay
2
8
ns
2
TOV41
MWE3:0# Rising Edge Output Valid Delay
1
9
ns
2
TOV42
MWE3:0# Falling Edge Output Valid Delay
0.5Tc +1
0.5Tc +9
ns
1,2
TOV43
MA11:0 Output Valid Delay - Initial Address
0.5Tc +2
0.5Tc +10
ns
2
TOV44
MA11:0 Output Valid Delay - Burst Address
2
10
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK
period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.
2. Output switching between VCC3 maximium and VSS.
ADVANCE INFORMATION
41
i960® Rx I/O Processor at 3.3 V
4.4.3
Boundary Scan Test Signal Timings
Table 29. Boundary Scan Test Signal Timings
Symbol
Parameter
TBSF
TCK Frequency
Min
Max
Units
0
0.5TF
MHz
Notes
TBSCH
TCK High Time
15
ns
Measured at 1.5 V (1)
TBSCL
TCK Low Time
15
ns
Measured at 1.5 V (1)
TBSCR
TCK Rise Time
5
ns
0.8 V to 2.0 V (1)
TBSCF
TCK Fall Time
5
ns
2.0 V to 0.8 V (1)
TBSIS1
Input Setup to TCK — TDI,
TMS
4
ns
TBSIH1
Input Hold from TCK — TDI,
TMS
6
ns
TBSOV1
TDO Valid Delay
3
30
ns
Relative to falling edge of TCK (2)
TBSOF1
TDO Float Delay
3
30
ns
Relative to falling edge of TCK (2)
TBSOV2
All Outputs (Non-Test) Valid
Delay
3
30
ns
Relative to falling edge of TCK (2)
TBSOF2
All Outputs (Non-Test) Float
Delay
3
30
ns
Relative to falling edge of TCK (2)
TBSIS2
Input Setup to TCK — All
Inputs (Non-Test)
4
ns
TBSIH2
Input Hold from TCK — All
Inputs (Non-Test)
6
ns
NOTES:
1. Not tested.
2. Outputs precharged to VCC5 maximium.
4.4.4
APIC Bus Interface Signal Timings
Table 30. APIC Bus Interface Signal Timings (Sheet 1 of 2)
Min
Max
Units
TAPF
Symbol
PICCLK Frequency
Parameter
2
16.66
MHz
Notes
TAPC
PICCLK Period
60
500
ns
TAPCH
PICCLK High Time
9
TAPCL
PICCLK Low Time
9
TAPCR
PICCLK Rise Time
1
5
ns
(1)
TAPCF
PICCLK Fall Time
1
5
ns
(1)
ns
ns
NOTES:
1. Not tested.
42
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
Table 30. APIC Bus Interface Signal Timings (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
TAPIS1
Input Setup to PICCLK — PICD1:0
TAPIH1
Input Hold from PICCLK — PICD1:0
3
ns
2.5
ns
TAPOF
Output Float Delay from PICCLK — PICD1:0
4
16
ns
TAPOVI
Output Valid Delay from PICCLK — PICD1:0 (High to Low)
4
22
ns
Notes
(1)
NOTES:
1. Not tested.
4.4.5
I2C Interface Signal Timings
Table 31. I2C Interface Signal Timings
Symbol
Parameter
FSCL
SCL Clock Frequency
TBUF
Bus Free Time Between STOP and START
Condition
THDSTA
Hold Time (repeated) START Condition
TLOW
SCL Clock Low Time
THIGH
SCL Clock High Time
TSUSTA
Setup Time for a Repeated START Condition
THDDAT
Std. Mode
Fast Mode
Min
Max
Min
Max
0
100
0
400
Units
Notes
KHz
4.7
1.3
µs
(1)
4
0.6
µs
(1,3)
4.7
1.3
µs
(1,2)
4
0.6
µs
(1,2)
4.7
0.6
µs
(1)
Data Hold Time
0
0
µs
(1)
TSUDAT
Data Setup Time
250
100
ns
(1)
(1,4)
0.9
TR
SCL and SDA Rise Time
1000
20+0.1Cb
300
ns
TF
SCL and SDA Fall Time
300
20+0.1Cb
300
ns
(1,4)
TSUSTO
Setup Time for STOP Condition
µs
(1)
4
0.6
NOTES:
1. See Figure 15.
2. Not tested.
3. After this period, the first clock pulse is generated.
4. Cb = the total capacitance of one bus line, in pF.
ADVANCE INFORMATION
43
i960® Rx I/O Processor at 3.3 V
4.5
AC Test Conditions
The AC Specifications in Section 4.4, Targeted AC Specifications (pg. 37) are tested with the 50 pF load
indicated in Figure 8.
Output Ball
CL = 50 pF for all signals
CL
Figure 8. AC Test Load
4.6
AC Timing Waveforms
TCR
TCF
2.0V
1.5V
0.8V
TCH
TCL
TC
Figure 9. S_CLK, TCLK Waveform
44
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
1.5V
S_CLK
1.5V
TOVX Min
TOVX Max
1.5V
Valid
1.5V
Figure 10. TOV Output Delay Waveform
1.5V
S_CLK
1.5V
TOF
Figure 11. TOF Output Float Waveform
ADVANCE INFORMATION
45
i960® Rx I/O Processor at 3.3 V
1.5V
S_CLK
1.5V
1.5V
TIHX
TISX
Valid
1.5V
Figure 12. TIS and TIH Input Setup and Hold Waveform
TA
TW/TD
1.5V
S_CLK
1.5V
1.5V
TLXL
ALE
1.5V
Valid
1.5V
TLXA
AD31:0
1.5V
Valid
1.5V
Figure 13. TLXL and TLXA Relative Timings Waveform
46
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
TA
S_CLK
TW/TD
1.5V
1.5V
1.5V
TOVX
Valid
DT/R#
TDXD
DEN#
TOVX
Figure 14. DT/R# and DEN# Timings Waveform
SDA
TLOW
TBUF
TR
THDSTA
TF
TSP
SCL
THDSTA
Stop
THDDAT
Start
THIGH
TSUSTO
TSUDAT
TSUSTA
Repeated
Start
Stop
Figure 15. I2C Interface Signal Timings
ADVANCE INFORMATION
47
i960® Rx I/O Processor at 3.3 V
4.7
Memory Controller Output Timing Waveforms
TA
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
S_CLK
AD31:0
MA11:0
DATA
In
ADDR
ROW
COL
DATA
In
COL
DATA
In
COL
DATA
In
COL
ALE
ADS#
W/R#
BLAST#
DT/R#
DEN#
DWE0#
RAS0#
CAS3:0#
LRDYRCV#
RDYRCV#
Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus
48
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
TA
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
S_CLK
AD31:0
MA11:0
ADDR
ROW
DATA
OUT
COL
DATA
OUT
DATA
OUT
COL
COL
DATA
OUT
COL
ALE
ADS#
BE3:0#
W/R#
BLAST#
DT/R#
MWE0#
DWE0#
RAS0#
CAS3:0#
LRDYRCV#
RDYRCV#
Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus
ADVANCE INFORMATION
49
i960® Rx I/O Processor at 3.3 V
TA
TW
TW
TD
TD
TD
TD
D
IN
D
IN
D
IN
TR
S_CLK
AD[31:0]
D
IN
ADDR
RAS[n]#
RAS[n+1#]
MA[11:0]
ROW
COL
COL
DALE[0]#
CAS[3:0]#
LEAF[0]#
DALE[1]#
CAS[7:4]#
LEAF[1]#
DWE[1:0]#
Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States
50
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
TA
TW
TD
TD
TD
TD
TR
TR
S_CLK
AD[31:0]
DATA
OUT
ADDR
DATA
OUT
DATA
OUT
DATA
OUT
RAS[n]#
RAS[n+1]#
MA[11:0]
ROW
COL
COL
DALE[0]#
CAS[3:0]#
LEAF[0]#
DALE[1]#
CAS[7:4]#
LEAF[1]#
DWE[1:0]#
Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States
ADVANCE INFORMATION
51
i960® Rx I/O Processor at 3.3 V
TA
TW
TW
TD
TD
TD
TD
TR
S_CLK
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
CAS#
AD[31:0]
D
IN
ADDR
D
IN
D
IN
D
IN
Figure 20. EDO DRAM, Read Cycle
TA
TW
TD
TD
TD
TD
COL
COL
COL
COL
D
OUT
D
OUT
TR
S_CLK
RAS#
MA[11:0]
ROW
CAS#
AD[31:0]
ADDR
D
OUT
D
OUT
Figure 21. EDO DRAM, Write Cycle
52
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
A
3
2
1
D
D
D
D
Tr
S_CLK
RAS#
COL
ROW
MA[11:0]
COL
COL
COL
COL
CAS#
AD[31:0]
D
IN
ADDR
D
IN
D
IN
D
IN
Figure 22. BEDO DRAM, Read Cycle
A
1
D
D
D
D
COL
COL
COL
COL
D
OUT
D
OUT
Tr
S_CLK
RAS#
MA[11:0]
ROW
WRITE CAS#
AD[31:0]
ADDR
D
OUT
D
OUT
Figure 23. BEDO DRAM, Write Cycle
ADVANCE INFORMATION
53
i960® Rx I/O Processor at 3.3 V
TA
TD
TD
TD
TD
TR
S_CLK
CE[1]#
ADDR
MA[11:0]
ADDR ADDR ADDR
MWE[3:0]#
AD[31:0]
ADDR
D
IN
D
IN
D
IN
D
IN
Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States
TA
TD
TD
TD
TD
TR
S_CLK
CE[1]#
MA[11:0]
ADDR
ADDR ADDR ADDR
MWE[3:0]#
AD[31:0]
ADDR
D
OUT
D
OUT
D
OUT
D
OUT
Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States
54
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
5.0
BUS FUNCTIONAL WAVEFORMS
TA
TD
TR
TI
TI
TA
TD
TR
TI
TI
S_CLK
AD31:0
D
In
ADDR
Invalid
D
In
ADDR
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV#
RDYRCV#
Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus
ADVANCE INFORMATION
55
i960® Rx I/O Processor at 3.3 V
TA
TD
TD
TR
TA
TD
TD
TD
TD
TR
S_CLK
AD31:0
ADDR
D
In
D
In
ADDR
DATA
Out
DATA
Out
DATA
Out
DATA
Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV#
RDYRCV#
Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus
56
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
TA
TW
TW
TD
TW
TD
TW
TD
TW
TD
TR
S_CLK
AD31:0
ADDR
DATA
Out
DATA
Out
DATA
Out
DATA
Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV#
RDYRCV#
Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus
ADVANCE INFORMATION
57
i960® Rx I/O Processor at 3.3 V
TA
TD
TD
TR
TA
TD
TD
TD
TD
TR
S_CLK
AD31:0
ADDR
D
In
D
In
DATA
Out
ADDR
DATA
Out
DATA
Out
01
10
DATA
Out
ALE
ADS#
BE1/A1#
BE0/A0#
WIDTH1:0
01 or
11
00 or 10
00
00
11
00
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV#
RDYRCV#
Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus
58
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
TA
TW
TD
TD
TR
TR
TA
TW
TD
TD
TR
S_CLK
AD31:0
D
In
ADDR
D
In
DATA
Out
ADDR
DATA
Out
ALE
ADS#
BE1/A1#
0
1
0
1
BE3#
BE0#
01
WIDTH1:0
01
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV#
RDYRCV#
Figure 30. Burst Read and Write Transactions with 1, 0 Wait States
and Extra Tr State on Read, 16-Bit 80960 Local Bus
ADVANCE INFORMATION
59
i960® Rx I/O Processor at 3.3 V
TA
TD
TR
TA
TD
TR
TA
TD
TR
TA
TD
TR
S_CLK
AD31:0
A
D
In
A
D
In
A
D
In
A
D
In
ALE
ADS#
BE3:0#
WIDTH1:0
D/C#
1101
0000
0011
1110
10
Valid
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV#
RDYRCV#
Figure 31. Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus
60
ADVANCE INFORMATION
i960® Rx I/O Processor at 3.3 V
TH
TH
TI or TA
∼
TI or TR
∼
Valid
∼
∼
Valid
∼
Outputs:
AD31:0,
ALE, ADS#, BE3:0#
D/C#/RSTMODE#
LRDYRCV#, FAIL#
WIDTH/HLTD1,
WIDTH/HLTD1/RETRY,
W/R#, DT/R#, DEN#,
BLAST#, LOCK#/ONCE#
∼
∼
S_CLK
∼
HOLD
(Note)
∼
HOLDA
NOTE: HOLD is sampled on the rising edge of S_CLK. HOLDA is granted after the latency counter in the local
bus arbiter expires. The processor asserts HOLDA to grant the bus on the same edge in which it recognizes
HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly, the processor deasserts HOLDA on
the same edge in which it recognizes the deassertion of HOLD.
Figure 32. HOLD/HOLDA Waveform For Bus Arbitration
ADVANCE INFORMATION
61
ADS#, BE3:0#
BLAST#, DEN#
LRDYRCV
ALE, DT/R#,
HOLD, HOLDA, W/R#
1 ms power
and clock stable
∼
∼∼ ∼∼ ∼∼ ∼∼ ∼
∼∼ ∼∼∼∼ ∼
Valid
V and S_CLK stable to P_RST# High, minimum
CC
100 µs for PLL stabilization.
(Input)
Valid
(Output)
Built-in self test approximately 414,000 S_CLK
periods (if selected)
Idle (Note 2)
(Note 1)
First
Bus
Activity
2. If the processor fails built-in self-test, it initiates one dummy load bus access.
The load address indicates the point of self-test failure.
Notes:
1. The processor asserts FAIL# during built-in self-test. If self- test passes, the FAIL# is deasserted.The processor also asserts FAIL#
during the bus confidence test. If the bus confidence test passes, FAIL# is deasserted and the processor begins user program execution.
STEST
LOCK#/
ONCE#
D/C#/RST_MODE#,
WIDTH/HLTD0,
WIDTH/HLTD1/RETRY
P_RST#
AD31:0
FAIL#
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
VCC
∼
∼ ∼
∼∼∼
∼∼ ∼ ∼∼∼∼
∼
∼
∼ ∼
∼
∼
∼ ∼
∼∼ ∼
∼∼
62
S_CLK
i960® Rx I/O Processor at 3.3 V
Figure 33. 80960 Core Cold Reset Waveform
ADVANCE INFORMATION
Minimum L_RST# Low Time
16 S_CLK Cycles
Maximum L_RST# Low to Reset State
4 S_CLK Cycles
Valid
NOTE:
Local bus warm reset occurs when Bit 5 in the Extended Bridge Control Register (EBCR) is set;
L_RST# asserts when all ATU and/or DMA activity ceases on the PCI buses.
L_RST# asserts in a mimimum of 18 clock cycles after EBCR bit 5 is set.
L_RST#
S_RST#, P_RST#
STEST
LOCK#/ONCE#
HOLDA
HOLD
AD31:0
FAIL#
ALE, W/R#,DT/R#
∼ ∼
∼
∼
ADS#, BE3:0#,DEN#, BLAST#,
D/C#/RST_MODE#, WIDTH/HLTD0,
WIDTH/HLTD1/RETRY,LRDYRCV#
∼
∼ ∼
∼
∼
∼
∼ ∼
∼ ∼
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
∼
∼
∼ ∼
∼
∼
∼
∼∼
∼∼
∼
∼∼
∼ ∼
∼ ∼
∼∼
∼ ∼
∼∼
∼
∼ ∼
∼
ADVANCE INFORMATION
L_RST# High to First Bus
Activity, 46 S_CLK Cycles
∼
∼
S_CLK
i960® Rx I/O Processor at 3.3 V
Figure 34. 80960 Local Bus Warm Reset Waveform
63
i960® Rx I/O Processor at 3.3 V
6.0
DEVICE IDENTIFICATION ON RESET
During the manufacturing process, values characterizing the i960 Rx I/O processor type and stepping are
programmed into the memory-mapped registers. The i960 Rx I/O processor contains two read-only device ID
MMRs. One holds the Processor Device ID (PDIDR - 0000 1710H) and the other holds the i960 Core
Processor Device ID (DEVICEID - FF00 8710H). During initialization, the PDIDR is placed in g0.
The device identification values are compliant with the IEEE 1149.1 specification and Intel standards. Table 32
describes the fields of the two Device IDs.
Table 32. Processor Device ID Register - PDIDR
31
28
24
20
16
12
8
4
LBA
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
LBA:
1710H
PCI:
NA
Bit
0
Legend:
NA = Not Accessible
RO = Read Only
RV = Reserved
PR = Preserved
RW = Read/Write
RS = Read/Set
RC = Read Clear
LBA = 80960 Local Bus Address PCI = PCI Configuration Address Offset
Default
Description
31:28
X
Version - Indicates stepping changes.
27
X
VCC - Indicates device voltage type.
0 = 5.0 V
1 = 3.3 V
26:21
X
Product Type - Indicates the generation or “family member”.
20:17
X
Generation Type - Indicates the generation of the device.
16:12
X
Model Type - Indicates member within a series and specific model information.
11:01
X
Manufacturer ID - Indicates manufacturer ID assigned by IEEE.
0000 0001 001 = Intel Corporation
0
1
Constant
NOTE: Values programmed into this register vary with stepping. Refer to the i960® Rx I/O Processor Specification Update (272918) for the correct value.
64
ADVANCE INFORMATION