IDT 844251BG

ICS844251-14
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
General Description
Features
The ICS844251-14 is an Ethernet Clock Generator
and a member of the HiPerClocksTM family of high
HiPerClockS™
performance devices from IDT. The ICS844251-14
uses an 18pF parallel resonant crystal over the
range of 23.2MHz – 30MHz. For Ethernet
applications, a 25MHz crystal is used. The device has excellent
<1ps phase jitter performance, over the 1.875MHz – 20MHz
integration range. The ICS844251-14 is packaged in a small 8-pin
TSSOP, making it ideal for use in systems with limited board
space.
•
•
One differential LVDS output pair
•
Output frequency ranges: 145MHz – 187.5MHz and
580MHz – 750MHz
•
•
VCO range: 580MHz – 750MHz
•
•
•
Full 3.3V or 2.5V output supply modes
ICS
Crystal oscillator interface designed for 18pF, parallel resonant
crystal (23.2MHz – 30MHz)
RMS phase jitter at 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.53ps (typical)
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Common Configuration Table
Inputs
Crystal Frequency (MHz)
FREQ_SEL
M
N
Multiplication Value M/N
Output Frequency Range
(MHz)
25
1
25
1
25
625
26.67
1
25
1
25
666.67
25 (default)
0
25
4
6.25
156.25
Pin Assignment
Block Diagram
FREQ_SEL
Pulldown
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
580MHz - 750MHz
FREQ_SEL
0 (default)
1
M = ÷25 (fixed)
IDT™ / ICS™ LVDS CLOCK GENERATOR
1
N
÷4
÷1
Q
nQ
VDDA
GND
XTAL_OUT
XTAL_IN
1
8
2
3
4
7
6
5
VDD
Q
nQ
FREQ_SEL
ICS844251-14
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS844251BG-14 REV. A MAY 1, 2009
ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VDDA
Output
Analog supply pin.
2
GND
Power
Power supply ground.
3,
4
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5
FREQ_SEL
Input
6, 7
nQ, Q
Output
Differential output pair. LVDS interface levels.
8
VDD
Power
Core supply pin.
Pulldown
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLdown
Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ LVDS CLOCK GENERATOR
Test Conditions
2
Minimum
Typical
Maximum
Units
ICS844251BG-14 REV. A MAY 1, 2009
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
129.5°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
IDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.10
3.3
VDD
V
Power Supply Current
100
mA
Analog Supply Current
10
mA
Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
IDDA
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VDD – 0.10
2.5
VDD
V
Power Supply Current
95
mA
Analog Supply Current
10
mA
Maximum
Units
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V or 2.625V
IIL
Input Low Current
VDD = 3.465V or 2.625V, VIN = 0V
IDT™ / ICS™ LVDS CLOCK GENERATOR
Test Conditions
Minimum
VDD = 3.465V
2
VDD + 0.3
V
VDD = 2.625V
1.7
VDD + 0.3
V
VDD = 3.465V
-0.3
0.8
V
VDD = 2.625V
-0.3
0.7
V
150
µA
3
-5
Typical
µA
ICS844251BG-14 REV. A MAY 1, 2009
ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 3D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
247
1.275
Maximum
Units
454
mV
50
mV
1.525
V
50
mV
Maximum
Units
454
mV
50
mV
1.4
V
50
mV
Table 3E. LVDS DC Characteristics, VDD = VDDA = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
247
1.0
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
30
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Mode of Oscillation
Fundamental
Frequency
IDT™ / ICS™ LVDS CLOCK GENERATOR
Typical
23.2
4
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ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
Parameter Symbol
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 1
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
Minimum
Typical Maximum
Units
FREQ_SEL = 0
145
187.5
MHz
FREQ_SEL = 1
580
750
MHz
156.25MHz,
Integration Range: 1.875MHz – 20MHz
0.53
ps
625MHz,
Integration Range: 1.875MHz – 20MHz
0.45
ps
20% to 80%
70
550
ps
FREQ_SEL = 0
48
52
%
FREQ_SEL = 1
46
54
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C
Parameter Symbol
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 1
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical Maximum
Units
FREQ_SEL = 0
145
187.5
MHz
FREQ_SEL = 1
580
750
MHz
156.25MHz,
Integration Range: 1.875MHz – 20MHz
0.54
ps
625MHz,
Integration Range: 1.875MHz – 20MHz
0.45
ps
20% to 80%
70
550
ps
FREQ_SEL = 0
48
52
%
FREQ_SEL = 1
46
54
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
➝
Typical Phase Noise at 156.25MHz (3.3V)
Ethernet Filter
➝
Raw Phase Noise Data
➝
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.53ps (typical)
Phase Noise Result by adding a
Ethernet filter to raw data
Offset Frequency (Hz)
➝
Typical Phase Noise at 625MHz (3.3V)
Ethernet Filter
Raw Phase Noise Data
➝
Noise Power
➝
dBc
Hz
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.45ps
Phase Noise Result by adding a
Ethernet filter to raw data
Offset Frequency (Hz)
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Parameter Measurement Information
SCOPE
VDD
VDDA
LVDS
3.3V±5%
POWER SUPPLY
+ Float GND –
SCOPE
Qx
2.5V±5%
POWER SUPPLY
+ Float GND –
Qx
VDD
VDDA
LVDS
nQx
nQx
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
nQ
nQ
Q
80%
80%
t PW
VOD
t
20%
20%
Q
tF
tR
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Phase Noise Plot
Noise Power
VDD
out
LVDS
➤
DC Input
Phase Noise Mask
out
Offset Frequency
f2
➤
f1
➤
VOS/∆ VOS
RMS Jitter = Area Under the Masked Phase Noise Plot
OFFSET VOLTAGE SETUP
RMS Phase Jitter
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Parameter Measurement Information, continued
VDD
LVDS
100
➤
VOD/∆ VOD
out
➤
DC Input
➤
out
-
DIFFERENTIAL OUTPUT VOLTAGE SETUP
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844251-14
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure
1 illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
IDT™ / ICS™ LVDS CLOCK GENERATOR
3.3V or 2.5V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
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ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Crystal Input Interface
The ICS844251-14 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
3.3V, 2.5V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
3.3V or 2.5V
VDD
50Ω
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Schematic Example
Figure 5 shows an example of ICS844251-14 application
schematic. In this example, the device is operated at VDD = 3.3V.
The decoupling capacitor should be located as close as possible
to the power pin. The 18pF parallel resonant 25MHz crystal is
used. The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layouts, the C1 and C2
may be slightly adjusted for optimizing frequency accuracy. For the
LVDS output drivers, place a 100Ω resistor as close to the receiver
as possible.
VDD
VDD
R1
C5
0.01u
VDDA
10
C3
0.1u
U1
C4
10u
1
2
3
4
Zo = 50 Ohm
VDDA
GND
XTAL_OUT
XTAL_IN
VDD
Q
nQ
FREQ_SEL
8
7
6
5
Q
F
p
8
1
25 MHz
C1
27pF
R2
100
FREQ_SEL
nQ
X1
Zo = 50 Ohm
+
-
C2
27pF
Q
Logic Input Pin Examples
Set Logic
Input to
'1'
VDD
RU1
1K
Zo = 50 Ohm
Set Logic
Input to
'0'
VDD
R3
50
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
nQ
RD2
1K
C7
0.1uF
R4
50
Zo = 50 Ohm
+
-
Alternate
LVDS
Termination
Figure 5. ICS844251-14 Schematic Example
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844251-14.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844251-14 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (100mA + 10mA) = 381.15mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5.°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.381W *129.5°C/W = 119.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT™ / ICS™ LVDS CLOCK GENERATOR
0
1
2.5
129.5°C/W
125.5°C/W
123.5°C/W
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ICS844251BG-14 REV. A MAY 1, 2009
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Reliability Information
Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
129.5°C/W
125.5°C/W
123.5°C/W
Transistor Count
The transistor count for ICS844251-14 is: 2401
Package Outline and Package Dimensions
Table 8. Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
8
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
3.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Ordering Information
Table 9. Ordering Information
Part/Order Number
844251BG-14
844251BG-14T
844251BG-14LF
844251BG-14LFT
Marking
51B14
51B14
1B14L
1B14L
Package
8 Lead TSSOP
8 Lead TSSOP
“Lead-Free” 8 Lead TSSOP
“Lead-Free” 8 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Revision History Sheet
Rev
A
Table
Page
Description of Change
Date
11
Added schematic layout.
5/1/09
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS844251BG-14 REV. A MAY 1, 2009
ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contact IDT
[email protected]
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA