93L38 8-Bit Multiple Port Register General Description Features The 93L38 is an 8-bit multiple port register designed for high speed random access memory applications where the ability to simultaneously read and write is desirable. A common use would be as a register bank in a three address computer. Data can be written into any one of the eight bits and read from any two of the eight bits simultaneously. The circuit uses TTL technology and is compatible with all TTL families. Y Connection Diagram Logic Symbol Y Y Master/slave operation permitting simultaneous write/ read without race problems Simultaneously read two bits and write one bit in any one of eight bit positions Readily expandable to allow for larger word sizes Dual-In-Line Package TL/F/10202 – 2 TL/F/10202 – 1 Order Number 93L38DMQB or 93L38FMQB See NS Package Number J16A or W16A Pin Names A0–A2 DA B0–B2 C0–C2 CP SLE ZB ZC C1995 National Semiconductor Corporation TL/F/10202 VCC e Pin 16 GND e Pin 8 Description Write Address Inputs Data Input B Read Address Inputs C Read Address Inputs Clock Pulse Input (Active Rising Edge) Slave Enable Input (Active LOW) B Output C Output RRD-B30M105/Printed in U. S. A. 93L38 8-Bit Multiple Port Register July 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Operating Free Air Temperature Range Military 7V b 55§ C to a 125§ C Storage Temperature Range b 65§ C to a 150§ C 5.5V Recommended Operating Conditions Symbol 93L38 (MIL) Parameter Units Min Nom Max 4.5 5 5.5 VCC Supply Voltage VIH High Level Input Voltage V VIL Low Level Input Voltage 0.7 V IOH High Level Output Current b 400 mA IOL Low Level Output Current 4.8 mA TA Free Air Operating Temperature 125 §C ts (H) ts (L) Setup Time HIGH or LOW DA to CP 30 22 th (H) th (L) Hold Time HIGH or LOW DA to CP b 4.0 ts (H) ts (L) Setup Time HIGH or LOW An to CP 0 0 ns th (H) th (L) Hold Time HIGH or LOW An to CP 0 0 ns tw (H) tw (L) CP Pulse Width HIGH or LOW 40 30 ns 2 V b 55 ns 0 ns Electrical Characteristics over recommended operating free air temperature (unless othewise noted) Symbol VI Parameter Conditions Input Clamp Voltage VCC e Min, II e b10 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current IIL IOS ICC Min Typ (Note 1) Max Units b 1.5 V 2.4 V 0.3 V 1 mA VCC e Max, VI e 2.4V 50 mA Low Level Input Current VCC e Max, VI e 0.3V b2 mA Short Circuit Output Current VCC e Max (Note 2) b 25 mA Supply Current VCC e Max (Note 3) 70 mA b 2.5 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open and all input grounded. 2 Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for Test Waveforms and Output Load Symbol CL e 15 pF Parameter Min Units Max tPLH tPHL Propagation Delay Bn or Cn or Zn 68 95 ns tPLH tPHL Propagation Delay DA to Zn 70 92 ns tPLH tPHL Propagation Delay CP to Zn 65 57 ns Functional Description The signals are available on the output pins (ZB and ZC). The input bit selection and the two output bit selections can be accomplished independently or simultaneously. The data flows into the device, is demultiplexed according to the state of the write address lines and is clocked into the selected latch. The eight latches function as masters and store the input data. The two output latches are slaves and hold the data during the read operation. The state of each slave is determined by the state of the master selected by its associated set of read address inputs. The method of parallel expansion is shown in Figure A . One 93L38 is needed for each bit of the required word length. The read and write input lines should be connected in common on all of the devices. This register configuration provides two words of n-bits each at one time, where n devices are connected in parallel. The 93L38 8-bit multiple port register can be considered a 1-bit slice of eight high speed working registers. Data can be written into any one and read from any two of the eight locations simultaneously. Master/slave operation eliminates all race problems associated with simultaneous read/write activity from the same location. When the clock input (CP) is LOW data applied to the data input line (DA) enters the selected master. This selection is accomplished by coding the three write input select lines (A0–A2) appropriately. Data is stored synchronously with the rising edge of the clock pulse. The information for each of the two slaved (output) latches is selected by two sets of read address inputs (B0 – B2 and C0 – C2). The information enters the slave while the clock is HIGH and is stored while the clock is LOW. If Slave Enable is LOW (SLE), the slave latches are continuously enabled. TL/F/10202 – 4 FIGURE A. Parallel Expansion 3 TL/F/10202 – 3 Logic Diagram 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L38DMQB NS Package Number J16A 5 93L38 8-Bit Multiple Port Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 93L38FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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