DATASHEET
Twelve Output Differential Buffer for PCIe Gen3
9DB1233
Recommended Application
Features/Benefits
12 output PCIe Gen3 zero-delay/fanout buffer
•
3 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
•
12 OE# pins/Hardware control of each output
•
PLL or bypass mode/PLL can dejitter incoming clock
•
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
•
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
•
SMBus Interface/unused outputs can be disabled
•
Supports undriven differential outputs in Power Down mode
for power management
General Description
The 9DB1233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1233 is driven by a differential SRC output
pair from an IDT 932S421 or 932SQ420 or equivalent main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
Output Features
•
12 - 0.7V current mode differential HCSL output pairs
Key Specifications
•
•
•
•
Output cycle-cycle jitter < 50ps.
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Pin compatible with DB1200 Yellow Cover Device
Functional Block Diagram
12
OE_(11:0)#
SPREAD
COMPATIBLE
PLL
DIF_IN
DIF_IN#
M
U
X
12
DIF(11:0))
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
CONTROL
LOGIC
ADR_SEL
SMBDAT
SMBCLK
IREF
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
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9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
9DB1233
VDD
DIF_IN
DIF_IN#
GND
OE0#
DIF_0
DIF_0#
VDD
GND
OE1#
DIF_1
DIF_1#
OE2#
DIF_2
DIF_2#
GND
VDD
OE3#
DIF_3
DIF_3#
OE4#
DIF_4
DIF_4#
VDD
GND
OE5#
DIF_5
DIF_5#
**ADR_SEL
HIGH_BW#
VDD
SMBCLK
VDDA
AGND
IREF
VDD
OE11#
DIF_11
DIF_11#
VDD
GND
OE10#
DIF_10
DIF_10#
OE9#
DIF_9
DIF_9#
GND
VDD
OE8#
DIF_8
DIF_8#
OE7#
DIF_7
DIF_7#
VDD
GND
OE6#
DIF_6
DIF_6#
VTTPWRGD#/PD
BYPASS#/PLL
GND
SMBDAT
64-TSSOP
** Indicates 120K ohm Pulldown
Power Groups
Pin Number
VDD
GND
1
4
8, 17, 24, 41, 9, 16, 25, 40,
48, 57
49, 56
N/A
63
SMBus Address Selection (Pin 29)
ADR_SEL
Voltage
SMBus Adr (Wr/Rd)
Low
<0.8V
DC/DD
Mid
1.2<Vin<1.8V
D6/D7
High
Vin > 2.0V
D4/D5
Description
DIF_IN/DIF_IN#
DIF(11:0)
IREF
Analog VDD & GND
64
63
for PLL core
Note: Please treat pin 1 as an analog VDD.
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
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9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
PWR
IN
IN
PWR
Power supply, nominal 3.3V
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Ground pin.
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
Clock pin of SMBUS circuitry, 5V tolerant
1
2
3
4
VDD
DIF_IN
DIF_IN#
GND
5
OE0#
6
7
8
9
DIF_0
DIF_0#
VDD
GND
10
OE1#
11
12
DIF_1
DIF_1#
13
OE2#
14
15
16
17
DIF_2
DIF_2#
GND
VDD
18
OE3#
19
20
DIF_3
DIF_3#
21
OE4#
22
23
24
25
DIF_4
DIF_4#
VDD
GND
26
OE5#
27
28
DIF_5
DIF_5#
29
**ADR_SEL
IN
30
HIGH_BW#
IN
31
32
VDD
SMBCLK
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
PWR
IN
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
3
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Pin Description (cont.)
PIN #
PIN NAME
TYPE
33
34
SMBDAT
GND
I/O
PWR
35
BYPASS#/PLL
IN
36
VTTPWRGD#/PD
IN
37
38
DIF_6#
DIF_6
39
OE6#
40
41
42
43
GND
VDD
DIF_7#
DIF_7
44
OE7#
45
46
DIF_8#
DIF_8
47
OE8#
48
49
50
51
VDD
GND
DIF_9#
DIF_9
52
OE9#
53
54
DIF_10#
DIF_10
55
OE10#
56
57
58
59
GND
VDD
DIF_11#
DIF_11
60
OE11#
61
VDD
PWR
62
IREF
OUT
63
64
AGND
VDDA
PWR
PWR
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
DESCRIPTION
Data pin of SMBUS circuitry, 5V tolerant
Ground pin.
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
VTTPWRGD# is an active low input used to sample latched inputs and
allow the device to Power Up. PD is an asynchronous active high input
pin used to put the device into a low power state. The internal clocks and
PLLs are stopped.
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Analog Ground pin for Core PLL
3.3V power for the PLL core.
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
4
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
VDDA
VDD
VIL
VIH
VIHSMB
Storage Temperature
Junction Temperature
Input ESD protection
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
UNITS NOTES
V
V
V
V
V
GND-0.5
Except for SMBus interface
SMBus clock and data pins
VDD+0.5V
5.5V
-65
Human Body Model
150
125
2000
°
C
°C
V
1,2
1,2
1
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Ambient Operating
Temperature
TCOM
Commmercial range
Single-ended inputs, except SMBus, low
Input High Voltage
VIH
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
Input Low Voltage
V IL
threshold and tri-level inputs
IIN
Single-ended inputs, VIN = GND, VIN = VDD
MIN
TYP
MAX
UNITS NOTES
1
0
70
°C
2
VDD + 0.3
V
1
GND - 0.3
0.8
V
1
-5
5
uA
1
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
1
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
10
90
CINDIF_IN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
166
110
7
5
5
MHz
MHz
nH
pF
pF
2
2
1
1
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8
ms
1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
OE# Latency
tLATOE#
4
12
cycles
1,3
Tdrive_PD#
tDRVPD
300
us
1,3
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
5
5
0.8
@ IPULLUP
@ VOL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
5.5
1000
300
ns
ns
V
V
V
mA
V
ns
ns
1,2
1,2
1
1
1
1
1
1
1
fMAXSMB
Maximum SMBus operating frequency
100
kHz
1,5
Input Current
Input Frequency
Pin Inductance
Capacitance
IINP
Fibyp
Fipll
Lpin
CIN
2.1
4
2.7
100.00
VDDSMB
0.4
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
2
5
The differential input clock must be running for the SMBus to be active
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
5
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Electrical Characteristics - Clock Input Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage - DIF_IN
VIHDIF
Input Low Voltage - DIF_IN
VILDIF
Input Common Mode
Voltage - DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
600
800
1150
mV
1
VSS - 300
0
300
mV
1
VCOM
Common Mode Input Voltage
300
1000
mV
1
VSWING
dv/dt
I IN
dtin
J DIFIn
Peak to Peak value
Measured differentially
VIN = VDD , VIN = GND
Measurement from differential wavefrom
Differential Measurement
300
0.4
-5
45
0
1450
8
5
55
125
mV
V/ns
uA
%
ps
1
1,2
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Slew rate
Slew rate matching
Trf
∆Trf
CONDITIONS
MIN
TYP
MAX UNITS NOTES
V/ns 1, 2, 3
Scope averaging on
1
2.4
4
%
Slew rate matching, Scope averaging on
20
1, 2, 4
Statistical measurement on single-ended signal
Voltage High
VHigh
660
800
850
1
using oscilloscope math function. (Scope averaging
mV
Voltage Low
VLow
-150
20
150
1
on)
Measurement on single ended signal using absolute
Max Voltage
Vmax
850
1150
1
mV
value. (Scope averaging off)
Min Voltage
Vmin
-300
1
Vswing
Vswing
Scope averaging off
300
mV
1, 2
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
550
mV
1, 5
Crossing Voltage (var)
∆-Vcross
Scope averaging off
140
mV
1, 6
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH =
6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).
2
Measured from differential waveform
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
3
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
Electrical Characteristics - Current Consumption
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Operating Supply Current
Powerdown Current
1
I DD3.3OP
I DD3.3PD
I DD3.3PDZ
CONDITIONS
All outputs active @100MHz, CL = Full load;
All diff pairs driven
All differential pairs tri-stated
MIN
TYP
MAX
300
NA
21
375
24
UNITS NOTES
mA
mA
mA
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
6
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2
0.7
45
3
1
1.5
49.5
4
1.4
2
55
MHz
MHz
dB
%
1
1
1
1
0
2
%
1,4
45
25
25
4500
250
50
50
50
ps
ps
ps
ps
ps
1
1
1
1,3
1,3
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
t JPEAK
t DC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
Duty Cycle Distortion
t DCD
Measured differentially, Bypass Mode @100MHz
-2
Jitter, Cycle to cycle
tjcyc-cyc
Bypass Mode, VT = 50%
PLL Mode VT = 50%
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
2500
-250
Skew, Output to Output
t pdBYP
t pdPLL
t sk3
Skew, Input to Output
UNITS NOTES
1
Guaranteed by design and characterization, not 100% tested in production.
I REF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH = 0.7V @ ZO=50Ω.
3
Measured from differential waveform
4
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
2
Electrical Characteristics - PCIe Phase Jitter Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Phase Jitter, PLL Mode
SYMBOL
t jphPCIeG1
t jphPCIeG2
t jphPCIeG3
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
t jphPCIeG1
Additive Phase Jitter,
Bypass Mode
t jphPCIeG2
t jphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
MIN
TYP
34
MAX
86
1.1
3
2.2
3.1
0.4
1
2
5
0.5
0.6
0.8
1
0.35
0.5
UNITS Notes
ps (p-p) 1,2,3
ps
1,2
(rms)
ps
1,2
(rms)
ps
1,2,4,5
(rms)
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
1,2,3
1,2,6
1,2,6
1,2,4,5,
6
1
Applies to all outputs when driven by 932SQ420DGLF or equivalent.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.4
6
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) = SQRT{(total jittter)^2 - (input jitter)^2}
2
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
7
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Clock Periods Differential Outputs with Spread Spectrum Enabled
Measurement
Window
Symbol
Definition
DIF
DIF 100
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
-SSC
Short-term
Average
Minimum
Absolute
Period
9.99900
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
0ppm
+ ppm error
Long-Term
Average
+SSC
Short-term
Average
Lg+
Nominal
Maximum
Maximum
Maximum
10.00000
10.00100
10.05130
10.17630
Period
Period
Units Notes
ns
1,2,3
Clock Periods Differential Outputs with Spread Spectrum Disabled
Measurement
Window
Symbol
Definition
DIF
DIF 100
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
-SSC
Short-term
Average
Minimum
Absolute
Period
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
0ppm
+ ppm error
Long-Term
Average
+SSC
Short-term
Average
Lg+
Nominal
Maximum
Maximum
10.00000
10.00100
Period
Period
Maximum
10.17630
Units Notes
ns
1,2,3
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK410B+/CK420BQ accuracy requirements. The 9DB1233 itself does not contribute to ppm error.
3
Driven by SRC output of main clock, PLL or Bypass mode
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
8
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
DIF Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Rs
Rt
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
HCSL Output Buffer
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
HCSL Output Buffer
Rt
L3'
IDT® Twelve Output Differential Buffer for PCIe Gen3
PCI Express
Add-in Board
REF_CLK Input
L3
1675B—11/08/10
9
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
R2a
HCSL Output Buffer
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
IDT® Twelve Output Differential Buffer for PCIe Gen3
PCIe Device
REF_CLK Input
1675B—11/08/10
10
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
General SMBus serial interface information for the 9DB1233
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (h)
IDT clock will acknowledge
Controller (host) sends the begining byte location = N
IDT clock will acknowledge
Controller (host) sends the data byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address DC(h)
WRite
WR
Controller (host) will send start bit.
Controller (host) sends the write address DC (h)
IDT clock will acknowledge
Controller (host) sends the begining byte
location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (h)
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N + X -1
IDT clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address DC(h)
WR
WRite
IDT (Slave/Receiver)
IDT (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address DD(h)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
Note: Addresses show assumes pin 29 is low.
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
11
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
SMBus Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
HIGH_BW#
High or Low BW
Bit 7
BYPASS#/PLL
Bypass (non-PLL Mode) or PLL Mode
Bit 6
Reserved
Reserved
Bit 5
Reserved
Reserved
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
High BW
Low BW
Bypass
PLL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
Latch
Latch
X
X
X
1
0
1
SMBus Table: Output Control Register
Byte 1
Pin #
Name
43,42
DIF_7
Bit 7
38,37
DIF_6
Bit 6
27,28
DIF_5
Bit 5
22,23
DIF_4
Bit 4
19,20
DIF_3
Bit 3
14,15
DIF_2
Bit 2
11,12
DIF_1
Bit 1
6,7
DIF_0
Bit 0
Control Function
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Default
1
1
1
1
1
1
1
1
SMBus Table: Output Control Register
Byte 2
Pin #
Name
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
58,59
DIF_11
Bit 3
53,54
DIF_10
Bit 2
50,51
DIF_9
Bit 1
45,46
DIF_8
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
0
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Type
RW
RW
RW
RW
RW
RW
RW
RW
1
Reserved
Reserved
Reserved
Reserved
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Default
0
0
0
0
1
1
1
1
Type
R
R
R
R
R
R
R
R
0
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Default
X
X
X
X
X
X
X
X
SMBus Table: Output Enable Readback
Byte 3
Pin #
Name
43,42
OE7#
Bit 7
38,37
OE6#
Bit 6
27,28
OE5#
Bit 5
22,23
OE4#
Bit 4
19,20
OE3#
Bit 3
14,15
OE2#
Bit 2
11,12
OE1#
Bit 1
OE0#
6,7
Bit 0
Control Function
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
IDT® Twelve Output Differential Buffer for PCIe Gen3
1
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
1675B—11/08/10
12
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
SMBus Table: Output Enable Readback
Byte 4
Pin #
Name
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
58,59
OE11#
Bit 3
53,54
OE10#
Bit 2
50,51
OE9#
Bit 1
OE8#
45,46
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Output Control (Disable =
Hi-Z)
Hi-Z)
Hi-Z)
Hi-Z)
Type
R
R
R
R
R
R
R
R
0
1
Reserved
Reserved
Reserved
Reserved
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Default
0
0
0
0
X
X
X
X
Note: For an output to be enabled, BOTH the Output Enable Bit and the OE# pin must be enabled.
This means that the Output Enable Bit must be '1' and the corresponding OE# pin must be '0'.
SMBus Table: Vendor & Revision ID Register
Byte 5
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: DEVICE ID
Byte 6
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Byte Count Register
Byte 7
Pin #
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
Default
0
0
1
0
0
0
0
1
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
1
1
0
0
0
0
0
0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
REVISION ID
VENDOR ID
Writing to this register configures how
many bytes will be read back.
IDT® Twelve Output Differential Buffer for PCIe Gen3
Device ID is C0 Hex
0
-
1
-
Default
0
0
0
0
0
1
1
1
1675B—11/08/10
13
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
c
N
SYMBOL
L
E1
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
INDEX
AREA
1 2
a
D
VARIATIONS
A
A2
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
-1.20
-.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.17
0.27
.007
.011
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
-0.10
-.004
N
A1
64
D mm.
MIN
16.90
D (inch)
MAX
17.10
MIN
.665
MAX
.673
-CReference Doc.: JEDEC Publication 95, MO-153
e
SEATING
PLANE
b
10-0039
aaa C
Ordering Information
Part / Order Number
9DB1233AGLF
9DB1233AGLFT
Shipping Packaging
Tubes
Tape and Reel
Package
64-pin TSSOP
64-pin TSSOP
Temperature
0 to +70°C
0 to +70°C
“LF” after the package code denotes the Pb-Free configuration, RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
IDT® Twelve Output Differential Buffer for PCIe Gen3
1675B—11/08/10
14
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Revision History
Rev.
0.1
A
B
Issue Date Who Description
7/7/2010
RDW Initial Release
1. Changed 'PWD' to 'Default' in SMBus
2. Updated Electrical Tables
7/12/2010 RDW 3. Move to Final
11/4/2010
Page #
-
12,13
1. Corrected Additive phase jitter calculation in PCIe phase jitter table
RDW 2. Added footnotes 5 and 6 to this table.
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15