A4975 Full-Bridge PWM Microstepping Motor Driver Features and Benefits Description ▪ ±1.5 A continuous output current ▪ 50 V output voltage rating ▪ Internal PWM current control ▪ 3-bit nonlinear DAC ▪ Fast, mixed fast/slow, and slow current-decay modes ▪ Internal thermal shutdown circuitry ▪ Crossover-current and UVLO protection The A4975 is designed to drive one winding of a bipolar stepper motor in a microstepping mode. The outputs are rated for continuous output currents to ±1.5 A and operating voltages to 50 V. Internal pulse width modulated (PWM) current control combined with an internal three-bit nonlinear digitalto-analog converter allows the motor current to be controlled in full-, half-, quarter-, or eighth-step (microstepping) modes. Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides increased step resolution, and reduces torque variations and resonance problems at low speed. Packages: Package B, 16-pin DIP with exposed tabs Internal circuitry determines whether the PWM current-control circuitry operates in a slow (recirculating) current-decay mode, fast (regenerative) current-decay mode, or in a mixed current-decay mode in which the off-time is divided into a period of fast current decay and with the remainder of the fixed off-time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, digitally selected output current ratio; and slow, fast, or mixed current-decay modes provides users with a broad, variable range of motor control. Package LB, 16-pin SOIC with internally fused pins Not to scale Continued on the next page… 10 6 VCC PHASE 15 LOAD SUPPLY OUTB OUTA LOGIC SUPPLY Functional Block Diagram 16 7 V BB GROUND 4 5 UVLO & TSD 12 13 MIXED-DECAY COMPARATOR CURRENT-SENSE COMPARATOR R + – Q S DISABLE RS RT CT 2 8 9 14 D0 V TH D1 + – RC 3 4975-DS 11 D/A w5 BLANKING VCC SENSE + – D2 1 BLANKING GATE REF PFD PWM LATCH A4975 Full-Bridge PWM Microstepping Motor Driver Description (continued) Internal circuit protection includes thermal shutdown with hysteresis, an undervoltage monitor, and crossover-current protection. Special power-up sequencing is not required. The A4975 is supplied in a choice of two power packages; a 16-pin dual-in-line plastic package with copper heat-sink tabs (suffix ‘B’), and a 16-lead plastic SOIC with internally fused pins (suffix ‘LB’). For both package styles, the thermally enhanced pins are at ground potential and need no electrical isolation. Both packages are lead (Pb) free, with leadframe plating 100% matte tin. Selection Guide Part Number A4975SB-T A4975SLBTR-T Packing 16-pin DIP with exposed thermal tabs 16-pin SOICW with internally fused pins Package 25 per tube 1000 per reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage VBB 50 V Logic Supply Voltage VCC 6 V Logic/Reference Input Voltage Range VIN –0.3 to 6 V Sense Voltage VS 0.5 V ±1.5 A Output Current, Continuous IOUT Package Power Dissipation PD Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) Storage Temperature Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Range S See graph W –20 to 85 ºC 150 ºC –55 to 150 ºC Value Units 43 ºC/W 67 ºC/W 6 ºC/W Fault conditions that produce excessive junction temperature will activate the device’s thermal shutdown circuitry. These conditions can be tolerated but should be avoided. Tstg Thermal Characteristics Characteristic Symbol Test Conditions* B Package, single-layer PCB, 1 in.2 2-oz. exposed copper Package Thermal Resistance, Junction to Ambient RθJA Package Thermal Resistance, Junction to Tab RθJT LB Package, 2-layer PCB, 0.3 side in.2 2-oz. exposed copper each ALLOWABLE PACKAGE POWER DISSIPATION (W) *Additional thermal information available on Allegro website. 4 R θJT = 6.0°C/W 3 SUFFIX 'B', R θJA = 43°C/W 2 1 SUFFIX 'LB', R θJA = 67°C/W 0 25 50 75 100 TEMPERATURE IN °C 125 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4975 Full-Bridge PWM Microstepping Motor Driver ELECTRICAL CHARACTERISTICS at TA = 25°C, VCC = 4.5 to 5.5 V (unless otherwise noted.) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Operating 5 — 50 V VOUT = VBB — <1.0 50 μA VOUT = 0 V — <-1.0 -50 μA Total Sink + Source, IOUT = 1.5 A , VBB > 8 V, TJ = 25°C — 1 1.4 Ω IBB(ON) D0 = D1 = D2 = VIN(1) — 500 700 μA IBB(OFF) D0 = D1 = D2 = VIN(0) — 250 500 μA Power Outputs Load Supply Voltage Range VBB Output Leakage Current ICEX Output Resistance RDS Motor Supply Current (No Load) Control Circuitry Logic Supply Voltage Range VCC Operating 4.5 5.0 5.5 V Reference Voltage Range VREF Operating 0.5 — 2.5 V VCC = 0 → 5 V 3.35 3.7 4.05 V 0.3 0.45 0.6 V UVLO Enable Threshold UVLO Hysteresis Logic Supply Current ICC(ON) D0 = D1 = D2 = VIN(1) — 2.7 — mA ICC(OFF) D0 = D1 = D2 = VIN(0) — 2.7 — mA VIN(1) VCC × 0.55 — — V VIN(0) — — VCC × 0.27 V Logic Input Voltage Logic Input Current IIN(1) VIN = VCC = 5 V — 0 –10 μA IIN(0) VIN = 0 V, VCC = 5 V — –106 –200 μA Slow Current-Decay Mode 3.5 — — V Mixed Current-Decay Mode 1.1 — 3.1 V Fast Current-Decay Mode — — 0.8 V Mixed-Decay Comparator Trip Points VPFD Mixed-Decay Comparator Input Offset Voltage VIO(PFD) — 0 ±50 mV ∆VIO(PFD) 5 25 55 mV VREF = 0.5 to 2.5 V — — ±5.0 μA At trip, D0 = D1 = D2 = VIN(1) — 5 — — 1.0 V < VREF ≤ 2.5 V — — ±3.0 % 0.5 V ≤ VREF ≤ 1.0 V — — ±4.0 % Mixed-Decay Comparator Hysteresis Reference Input Current IREF Reference Divider Ratio VREF/VS Digital-to-Analog Converter Accuracy* — Continued next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4975 Full-Bridge PWM Microstepping Motor Driver ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VCC = 4.5 to 5.5 V (unless otherwise noted.) Characteristic Symbol Test Conditions Min. Typ. Max. Unit VREF = 0 V — — ±5.0 mV D0 = D1 = D2 = VIN(0) — 0 — % D0 = VIN(1), D1 = D2 = VIN(0) — 19.5 — % D0 = VIN(0), D1 = VIN(1), D2 = VIN(0) — 38.2 — % D0 = D1 = VIN(1), D2 = VIN(0) — 55.5 — % D0 = D1 = VIN(0), D2 = VIN(1) — 70.7 — % D0 = VIN(1), D1 = VIN(0), D2 = VIN(1) — 83.1 — % D0 = VIN(0), D1 = D2 = VIN(1) — 92.4 — % D0 = D1 = D2 = VIN(1) Control Circuitry (cont’d) Current-Sense Comparator Input Offset Voltage* Step Reference Current Ratio Thermal Shutdown Temp. Thermal Shutdown Hysteresis VIO(S) SRCR — 100 — % TJ — 165 — °C ∆TJ — 15 — °C AC Timing PWM RC Fixed Off-time tOFFRC CT = 470 pF, RT= 43 kΩ 18.2 20.2 22.3 μs PWM Minimum On Time tON(min) VCC = 5.0 V, RT ≥ 43 kΩ, CT = 470 pF, IOUT = 100 mA 0.8 1.6 2.2 μs * The total error for the VREF/VS function is the sum of the D/A error and the current-sense comparator input offset voltage. Table 1 — PHASE Truth Table PHASE H L OUTA Table 3 — DAC Truth Table OUTB H L L H D2 DAC DATA D1 D0 Current Ratio, % VREF/VS H H H 100 5.00 H H L 92.4 5.41 H L H 83.1 6.02 Description H L L 70.7 7.07 ≥3.5 V Slow Current-Decay Mode L H H 55.5 9.01 1.1 V to 3.1 V Mixed Current-Decay Mode L H L 38.2 13.09 Fast Current-Decay Mode L L H 19.5 25.64 L L L All Outputs Disabled Table 2 — PFD Truth Table VPFD ≤0.8 V where VS = ITRIP×RS. See Applications section. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4975 Full-Bridge PWM Microstepping Motor Driver Note the A4975SB (DIP) and the A4975SLB (SOIC) are electrically identical and share a common terminal number assignment. 16 LOAD SUPPLY 2 15 OUTB RC 3 14 D0 GROUND 4 13 GROUND 12 GROUND 11 SENSE PFD 1 REF VBB LOGIC GROUND 5 LOGIC SUPPLY 6 PHASE 7 10 OUTA D2 8 9 D1 VCC Terminal Functions Terminal Name 1 PFD (Percent Fast Decay) The analog input used to set the current-decay mode. 2 REF (VREF) The voltage at this input (along with the value of RS and the states of DAC inputs D0, D1, and D2) set the peak output current. 3 RC The parallel combination of external resistor RT and capacitor CT set the off time for the PWM current regulator. CT also sets the blanking time. 4-5 GROUND 6 Description Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage measurements. LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V. 7 PHASE The PHASE input determines the direction of current in the load. 8 D2 (DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter. 9 D1 (DATA1) One-of-three control bits for the internal digital-to-analog converter. 10 OUTA 11 SENSE 12-13 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage measurements. 14 D0 (DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter. 15 OUTB 16 LOAD SUPPLY One-of-two output load connections. Connection to the sink-transistor emitters. Sense resistor RS is connected between this point and ground. One-of-two output load connections. (VBB) Supply voltage for the load. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4975 Full-Bridge PWM Microstepping Motor Driver Functional Description Two A4975 full-bridge PWM microstepping motor drivers are needed to drive the windings of a bipolar stepper motor. Internal pulse width modulated (PWM) control circuitry regulates each motor winding current. The peak motor current is set by the value of an external current-sense resistor (RS), a reference voltage (VREF), and the digital-to-analog converter (DAC) data inputs (D0, D1, and D2). To improve motor performance, especially when using sinusoidal current profiles necessary for microstepping, the A4975 has three distinct current-decay modes: slow decay, fast decay, and mixed decay. PHASE Input. The PHASE input controls the direction of current flow in the load (table 1). An internally generated dead time of approximately 500 ns prevents crossover currents that could occur when switching the PHASE input. DAC Data Inputs (D0, D1, D2). A non-linear DAC is used to digitally control the output current. The output of the DAC is used to set the trip point of the current-sense comparator. Table 3 shows DAC output voltages for each input condition. When D0, D1, and D2 are all logic low, all of the power output transistors are turned off. Internal PWM Current Control. Each motor driver contains an internal fixed off-time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink transistors are enabled and current flows through the motor winding and RS (figure 1). When the voltage across the sense resistor equals the DAC output voltage the current-sense comparator resets the PWM latch, which turns off the source drivers (slow-decay mode) or the sink and source drivers (fast- or mixed-decay mode). With the DAC data input lines at VIN(1) voltage, the maximum value of current limiting is set by the selection of RS and VREF with a transconductance function approximated by: ITRIP ≈ VREF / 5RS. The actual peak load current (IPEAK) will be slightly higher than ITRIP due to internal logic and switching delays. The driver(s) remain off for a time period determined by a user-selected external resistor-capacitor combination (RTCT). At the end of the fixed off-time, the driver(s) are re-enabled, allowing the load current to increase to ITRIP again, maintaining an average load current. The DAC data input lines are used to provide up to eight levels of output current. The internal 3-bit digital-to-analog converter reduces the reference input to the current-sense comparator in precise steps (the step reference current ratio or SRCR) to provide half-step, quarter-step, or “microstepping” load-current levels. ITRIP ≈ SRCR x VREF / 5RS Slow Current-Decay Mode. When VPFD ≥ 3.5 V, the device is in slow current-decay mode (the source drivers are disabled when the load current reaches ITRIP). During the fixed off-time, the load inductance causes the current to recirculate through the motor winding and sink drivers (see figure 1). Slow-decay mode produces low ripple current for a given fixed off-time (see figure 2). Low ripple current is desirable because the average current in the motor winding is more nearly equal to the desired reference value, resulting in increased motor VBB I PEAK SLOW (VPFD ≥ 3.5 V) MIXED (1.1 V ≤ V PFD ≤ 3.1 V) FAST (V PFD ≤ 0.8 V) PFD t OFF Dwg. WP-031-1 RS Drive Current (Normal) Recirculation (Fast Decay) Recirculation (Slow Decay) Figure 1 — Load-Current Paths Figure 2 — Current-Decay Waveforms Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4975 Full-Bridge PWM Microstepping Motor Driver performance in microstepping applications. For a given level of ripple current, slow decay affords the lowest PWM frequency, which reduces heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. Slow decay also has the advantage that the PWM load current regulation can follow a more rapidly increasing reference before the PWM frequency drops into the audible range. For these reasons slow-decay mode is typically used as long as good current regulation can be maintained. Under some circumstances slow-decay mode PWM can fail to maintain good current regulation: 1) The load current will fail to regulate in slow-decay mode due to a sufficiently negative back-EMF voltage in conjunction with the low voltage drop across the load during slow decay recirculation. The negative back-EMF voltage can cause the load current to actually increase during the slow decay off time. A negative back-EMF voltage condition commonly occurs when driving stepping motors because the phase lead of the rotor typically causes the back-EMF voltage to be negative towards the end of each step (see figure 3A). A — Slow-Decay 2) When the desired load current is decreased rapidly, the slow rate of load current decay can prevent the current from following the desired reference value. 3) When the desired load current is set to a very low value, the current-control loop can fail to regulate due to its minimum duty cycle, which is a function of the user-selected value of tOFF and the minimum on-time pulse width ton(min) that occurs each time the PWM latch is reset. B — Fast-Decay Fast Current-Decay Mode. When VPFD < 0.8 V, the device is in fast current-decay mode (both the sink and source drivers are disabled when the load current reaches ITRIP , and the opposite pair is turned on). During the fixed off-time, the load inductance causes the current to flow from ground to the load supply via the motor winding and the opposite pair of transistors (see figure 1). Because the full motor supply voltage is across the load during fast-decay recirculation, the rate of load current decay is rapid, producing a high ripple current for a given fixed off-time (see figure 2). This rapid rate of decay allows good current regulation to be maintained at the cost of decreased average current accuracy or increased driver and motor losses. C — Mixed-Decay Figure 3 — Sinusoidal Drive Currents Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4975 Full-Bridge PWM Microstepping Motor Driver Mixed Current-Decay Mode. If VPFD is between 1.1 V and 3.1 V, the device will be in a mixed current-decay mode. Mixed-decay mode allows the user to achieve good current regulation with a minimum amount of ripple current and motor/driver losses by selecting the minimum percentage of fast decay required for their application (see also the Stepper Motor Applications section). As in fast current-decay mode, mixed-decay starts with the sink and source drivers disabled and the opposite pair turned on after the load current reaches ITRIP. When the voltage at the RC terminal decays to a value below VPFD, the sink drivers are re-enabled, placing the device in slow current-decay mode for the remainder of the fixed off-time (figure 2). The percentage of fast decay (PFD) is user determined by VPFD or two external resistors. PFD = 100 ln (0.6[R1+R2]/R2) where: V CC R1 PFD R2 again. The PWM cycle repeats, maintaining the peak load current at the desired value. With increasing values of tOFF, switching losses will decrease, low-level load-current regulation will improve, EMI will be reduced, the PWM frequency will decrease, and ripple current will increase. A value of tOFF can be chosen for optimization of these parameters. For applications where audible noise is a concern, typical values of tOFF are chosen to be in the range of 15 to 35 μs. RC Blanking. In addition to determining the fixed off-time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the currentsense comparator when the outputs are switched by the internal current-control circuitry (or by the PHASE input, or when the device is enabled with the DAC data inputs). The comparator output is blanked to prevent false over-current detections due to reverse recovery currents of the clamp diodes, and/or switching transients related to distributed capacitance in the load. During internal PWM operation, at the end of the tOFF time, the comparator’s output is blanked and CT begins to be charged from approximately 0.22VCC by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 0.6VCC. The blanking time, tBLANK, can be calculated as: tBLANK = RTCT ln (RT/[RT – 3 kΩ]). Dwg. EP-062-1 Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one-shot off-time, tOFF, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off-time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ, is approximated by: tOFF ≈ RTCT. When the load current is increasing, but has not yet reached the sense-current comparator threshold (ITRIP), the voltage on the RC terminal is approximately 0.6VCC. When ITRIP is reached, the PWM latch is reset by the current-sense comparator and the voltage on the RC terminal will decay until it reaches approximately 0.22VCC. The PWM latch is then set, thereby re-enabling the driver(s) and allowing load current to increase When a transition of the PHASE input occurs, CT is discharged to near ground during the crossover delay time (the crossover delay time is present to prevent simultaneous conduction of the source and sink drivers). After the crossover delay, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 0.6VCC. Similarly, when the device is disabled, via the DAC data inputs, CT is discharged to near ground. When the device is re-enabled, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 0.6VCC. The blanking time, tBLANK, can be calculated as: tBLANK = RTCT ln ([RT - 1.1 kΩ]/RT - 3 kΩ). The minimum recommended value for CT is 470 pF ± 5 %. This value ensures that the blanking time is sufficient to avoid Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4975 Full-Bridge PWM Microstepping Motor Driver false trips of the comparator under normal operating conditions. For optimal regulation of the load current, this value for CT is recommended and the value of RT can be sized to determine tOFF. Thermal Considerations. Thermal-protection circuitry turns off all output transistors when the junction temperature reaches approximately +165°C. This is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. The output transistors are re-enabled when the junction temperature cools to approximately +150°C. Stepper Motor Applications. The A4975 is used to optimize performance in microstepping/sinusoidal stepper-motor drive applications (see figures 4 and 5). When the load current is increasing, the slow current-decay mode is used to limit the switching losses in the driver and iron losses in the motor. This also improves the maximum rate at which the load current can increase (as compared to fast decay) due to the slow rate of decay during tOFF. When the load current is decreasing, the mixed current-decay mode is used to regulate the load current to the desired level. This prevents tailing of the current profile caused by the back-EMF voltage of the stepper motor (see figure 3A). VBB 1 16 V REF 2 15 + V PFD BRIDGE B 47 MF D 1B 9 8 D2B 10 7 PHASE B 11 6 +5 V D 0A 12 +5 V 6 11 11 PHASE A 7 10 D2A 8 9 D0B 47 MF D 1A VBB 5 LOGIC 13 4 14 3 15 2 V REF 16 1 V PFD + 5 12 30 k7 13 LOGIC 0.5 7 30 k7 470 pF 4 0.5 7 14 3 470 pF BRIDGE A Dwg. EP-047-3 Figure 4 — Typical Application MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY Dwg. WK-004-3 Figure 5 — Microstepping/Sinusoidal Drive Current Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4975 Full-Bridge PWM Microstepping Motor Driver Table 4 — Step Sequencing Bridge A Full Step Half Step 1 1 Quarter Eighth Step Step 1 2 2 3 4 2 3 5 6 4 7 8 3 5 9 10 6 11 12 4 7 13 14 8 15 16 Bridge B PHASEA D2A D1A D0A ILOADA PHASEB D2B D1B D0B ILOADB 1 2 3 4 5 6 7 8 H H H H X L L L H L L L L L L L L H H L L L H H L H L H L H L H 70.7% 55.5% 38.2% 19.5% 0% -19.5% -38.2% -55.5% H H H H H H H H H H H H H H H H L L H H H H H L L H L H H H L H 70.7% 83.1% 92.4% 100% 100% 100% 92.4% 83.1% 9 10 11 12 13 14 15 16 L L L L L L L L H H H H H H H H L L H H H H H L L H L H H H L H -70.7% -83.1% -92.4% -100% -100% -100% -92.4% -83.1% H H H H X L L L H L L L L L L L L H H L L L H H L H L H L H L H 70.7% 55.5% 38.2% 19.5% 0% -19.5% -38.2% -55.5% 17 18 19 20 21 22 23 24 L L L L X H H H H L L L L L L L L H H L L L H H L H L H L H L H -70.7% -55.5% -38.2% -19.5% 0% 19.5% 38.2% 55.5% L L L L L L L L H H H H H H H H L L H H H H H L L H L H H H L H -70.7% -83.1% -92.4% -100% -100% -100% -92.4% -83.1% 25 26 27 28 29 30 31 32 H H H H H H H H H H H H H H H H L L H H H H H L L H L H H H L H 70.7% 83.1% 92.4% 100% 100% 100% 92.4% 83.1% L L L L X H H H H L L L L L L L L H H L L L H H L H L H L H L H -70.7% -55.5% -38.2% -19.5% 0% 19.5% 38.2% 55.5% Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4975 Full-Bridge PWM Microstepping Motor Driver MAXIMUM FULL-STEP A TORQUE (141%) 100 92.4 P 10 EP 2 E ST U EP Q R 3/8 TO ST T AN 1/4 S TEP 1/8 ST E ST N O C 70.7 55.5 1/ CURRENT IN PER CENT 0% 83.1 EP 5/8 ST 38.2 3/4 19.5 P STE EP 7/8 ST FULL STEP B B 19.5 A 38.2 55.5 70.7 CURRENT IN PER CENT 83.1 92.4 100 Dwg. GK-020-1 Figure 5 — Current and Displacement Vectors Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4975 Full-Bridge PWM Microstepping Motor Driver B package 16-pin DIP 19.05±0.25 16 +0.10 0.38 –0.05 +0.76 6.35 –0.25 +0.38 10.92 –0.25 7.62 A 1 2 5.33 MAX +0.51 3.30 –0.38 1.27 MIN +0.25 1.52 –0.38 2.54 For Reference Only (reference JEDEC MS-001 BB) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 0.46 ±0.12 LB package 16-pin SOICW 10.30±0.20 4° ±4 16 1.27 0.65 +0.07 0.27 –0.06 10.30±0.33 7.50±0.10 A 9.50 +0.44 0.84 –0.43 2.25 1 2 0.25 16X SEATING PLANE 0.10 C 0.41 ±0.10 1.27 2.65 MAX 0.20 ±0.10 C SEATING PLANE GAUGE PLANE B PCB Layout Reference View For Reference Only Pins 4 and 5, and 12 and 13 internally fused Dimensions in millimeters (reference JEDEC MS-013 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-16M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4975 Full-Bridge PWM Microstepping Motor Driver Revision History Revision Revision Date Final December 19, 2011 Description of Revision Update production availability Copyright ©2009-2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13