A617308 Series Preliminary 128K X 8 BIT HIGH SPEED CMOS SRAM Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. History Issue Date Remark Preliminary 0.0 Initial issue September 17, 1999 0.1 Change VDR(Max.) from 3.6V to 5.5V November 30, 1999 Add 32-pin SOP package Modify 32-pin SOJ package outline drawing and Dimensions 0.2 Add 15ns part January 19, 2000 Change operating current from 180mA to 150mA (Max.) Change VDR(Min.) from 2V to 3V Remove 32-pin SOP package PRELIMINARY (January, 2000, Version 0.2) AMIC Technology, Inc. A617308 Series Preliminary 128K X 8 BIT HIGH SPEED CMOS SRAM Features n n n n n Single + 5V power supply n Access times: 10/12/15 ns (max.) n Current: Operating: 150mA (max.) Standby: 12mA (max.) n Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 3V (min.) Available in 32-pin SOJ and TSOP packages General Description The A617308 is a high-speed, low-power 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 3V. Pin Configurations 1 32 VCC 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 A1 11 23 A10 22 CE1 A0 12 21 I/O 7 I/O 0 13 20 I/O 6 I/O 1 14 19 I/O 5 I/O 2 15 18 I/O 4 GND 16 17 I/O 3 (January, 2000, Version 0.2) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ~ NC A16 A617308S PRELIMINARY n TSOP A617308V ~ ~ n SOJ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A0 A1 A2 A3 AMIC Technology, Inc. A617308 Series Block Diagram A0 ADDRESS 1,048,576-BIT DECODER MEMORY ARRAY A16 8 I/O0 - I/O 7 8 I/O CONTROL 8 WE OE CE1 CE2 CONTROL LOGIC Pin Description - TSOP Pin Descriptions – SOJ Pin No. Symbol 1 - 4, 7, 10 - 20, 31 A0 - A16 Address Inputs 21 - 23, 25 - 29 I/O0 - I/O7 Data Inputs/Outputs Chip Enable 1 30 CE1 Chip Enable 1 CE2 Chip Enable 2 6 CE2 Chip Enable 2 24 OE Output Enable 32 OE Output Enable 29 WE Write Enable 5 WE Write Enable 32 VCC Power Supply 8 VCC Power Supply 16 GND Ground 24 GND Ground 1 NC No Connection 9 NC Pin No. Symbol 2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs 13 - 15, 17 - 21 I/O0 - I/O7 Data Inputs/Outputs 22 CE1 30 PRELIMINARY Description (January, 2000, Version 0.2) 2 Description No Connection AMIC Technology, Inc. A617308 Series Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.5 V VIL Input Low (1) Voltage -0.5 0 +0.8 V CL Output Load - - 30 pF Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol (TA = 0°C to + 70°C, VCC = 5V ± 10%, GND = 0V) Parameter A617308-10/12/15 Min. Max. Unit Conditions ILI Input Leakage - 5 µA VIN = GND to VCC ILO Output Leakage - 5 µA CE1 = VIH, CE2= VIL or OE = VIH VI/O = GND to VCC Dynamic Operating Current - 150 mA CE1 = VIL, CE2 = VIH , II/O = 0 mA Min. Cycle, Duty = 100% - 35 mA - 12 mA ICC1 (2) ISB ISB1 Standby Power Supply Current CE1 = VIH or CE2 = VIL CE1 ≥ VCC - 0.2V, CE2 ≤ 0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. PRELIMINARY (January, 2000, Version 0.2) 3 AMIC Technology, Inc. A617308 Series Truth Table CE1 CE2 OE WE H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB1 Output Disable L H H H High Z ICC1 Read L H L H DOUT ICC1 Write L H X L DIN ICC1 Mode Standby I/O Operation Supply Current Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 8 pF VIN = 0V CI/O* Input/Output Capacitance - 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 5V ± 10%) Symbol Parameter A617308-10 A617308-12 A617308-15 Unit Min. Max. Min. Max. Min. Max. 10 - 12 - 15 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 10 - 12 - 15 ns tACE Chip Enable Access Time - 10 - 12 - 15 ns tOE Output Enable to Output Valid - 5 - 6 - 8 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - 3 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - 0 - ns tCHZ Chip Disable Output in High Z 0 5 0 6 - 8 ns tOHZ Output Disable to Output in High Z 0 5 0 6 0 8 ns tOH Output Hold from Address Change 3 - 3 - 3 - ns PRELIMINARY (January, 2000, Version 0.2) 4 AMIC Technology, Inc. A617308 Series AC Characteristics (continued) Symbol A617308-10 Parameter A617308-12 A617308-15 Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 10 - 12 - 15 - ns tCW Chip Enable to End of Write 9 - 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - 0 - ns tAW Address Valid to End of Write 9 - 10 - 12 - ns tWP Write Pulse Width 9 - 10 - 12 - ns tWR Write Recovery Time 0 - 0 - 0 - ns tWHZ Write to Output in High Z 0 5 0 6 0 8 ns tDW Data to Write Time Overlap 5 - 6 - 7 - ns tDH Data Hold from Write Time 0 - 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - 3 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1) tRC Address tAA OE tOE tOH tOLZ5 CE1 CE2 tACE tOHZ5 tCHZ5 tCLZ 5 DOUT PRELIMINARY (January, 2000, Version 0.2) 5 AMIC Technology, Inc. A617308 Series Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 3(1, 3, 4, 6) CE1 tACE tCLZ 5 tCHZ 5 DOUT PRELIMINARY (January, 2000, Version 0.2) 6 AMIC Technology, Inc. A617308 Series Timing Waveforms (continued) Read Cycle 4(1, 4, 7, 8) CE2 tACE tCLZ 5 tCHZ 5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE1= VIL and CE2= VIH 3. Address valid prior to or coincident with CE1 transition low. 4. 5. 6. 7. 8. OE = VIL. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high. Write Cycle 1(6) (Write Enable Controlled) tWC Address tAW tWR3 tCW5 CE1 (4) CE2 (4) tAS1 tWP2 WE tDW tDH DIN tWHZ7 tOW7 DOUT PRELIMINARY (January, 2000, Version 0.2) 7 AMIC Technology, Inc. A617308 Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tWR3 tAW tCW5 CE1 tAS1 CE2 (4) (4) tWP2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (January, 2000, Version 0.2) 8 AMIC Technology, Inc. A617308 Series AC Test Conditions Input Pulse Levels 0V to 3.0V Input Rise and Fall Time 2 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 5V 5V 480Ω 480Ω DATAOUT DATA OUT 30pF 255Ω 255Ω 5pF* * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR Parameter VCC for Data Retention Min. Max. Unit 3 5.5 V ICCDR Data Retention Current - 1 mA tCDR Chip Disable to Data Retention Time 0 - ns tR Operation Recovery Time Conditions CE1 ≥ VCC - 0.2V VCC = 3.0V CE1 ≥ VCC - 0.2V CE2 ≤ 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform TRC* - ms tRC = Read Cycle Time PRELIMINARY (January, 2000, Version 0.2) 9 AMIC Technology, Inc. A617308 Series Low VCC Data Retention Waveform (1) ( CE1 controlled) DATA RETENTION MODE VCC 4.5V 4.5V tCDR tR VDR > 3.0V VIH CE1 VIH CE1 > VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 controlled) DATA RETENTION MODE VCC 4.5V 4.5V tCDR CE2 tR VDR > 3.0V VIL VIL CE2 < 0.2V Ordering Information Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) A617308S-10 10 150 12 32L SOJ A617308S-12 12 150 12 32L SOJ A617308S-15 15 150 12 32L SOJ A617308V-10 10 150 12 32L TSOP A617308V-12 12 150 12 32L TSOP A617308V-15 15 150 12 32L TSOP Part No. PRELIMINARY (January, 2000, Version 0.2) 10 Package AMIC Technology, Inc. A617308 Series Package Information SOJ 32L Outline Dimensions unit: inches/mm D 17 1 16 E1 32 b b1 S e D Seating Plane Symbol A y Min 0.025" y 0.004 Dimensions in inches A1 A2 C E E2 y Dimensions in mm Min Nom Max Min Nom Max A 0.128 0.132 0.140 3.25 3.35 3.56 A1 0.052 - - 2.08 - - A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.020 0.41 0.46 0.51 b1 0.026 0.028 0.032 0.66 0.71 0.81 C 0.006 0.008 0.012 0.15 0.20 0.30 D 0.820 0.825 0.830 20.83 20.96 21.08 E 0.330 0.335 0.340 8.39 8.51 8.63 E1 0.295 0.300 0.305 7.49 7.62 7.75 E2 0.260 0.267 0.274 6.61 6.78 6.96 e - 0.050 - - 1.27 - S - - 0.048 - - 1.22 y - - 0.004 - - 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (January, 2000, Version 0.2) 11 AMIC Technology, Inc. A617308 Series Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm A A1 c E A2 e D θ L LE HD Detail "A" D Detail "A" y S Dimensions in inches Symbol b Dimensions in mm Min Nom Max Min Nom Max A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.11 - 0.20 D 0.720 0.724 0.728 18.30 18.40 18.50 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC HD 0.779 0.787 0.795 19.80 20.00 20.20 L 0.016 0.020 0.024 0.40 0.50 0.60 LE - 0.032 - - 0.80 - S - - 0.020 - - 0.50 y - - 0.003 - - 0.08 θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (January, 2000, Version 0.2) 12 AMIC Technology, Inc.