Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers A6800SA A6800SL A6801SA A6801SEP A6801SLW ABSOLUTE MAXIMUM RATINGS Output Voltage, VCE ............................................50 V Supply Voltage, VDD .............................................7 V Input Voltage Range, VIN ..............–0.3 V to VDD +0.3 V Continuous Collector Current, IC........................ 600 mA Package Power Dissipation, PD, see Allowable Power Disspation chart, page 5 Operating Temperature Range Ambient Temperature, TA ............–20°C to +85°C Storage Temperature, TS ..........–55°C to +150°C Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. The A6800 and A6801 latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (‘D’ type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar NPN Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The A6800 ICs each contain four latched drivers. A6801 ICs contain eight latched drivers. The CMOS inputs are compatible with standard CMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/ power loads: relays, lamps, solenoids, small dc motors, etc. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 600 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. The A6800SA is furnished in a standard 14-pin DIP; the A6800SL and A6801SLW in surface-mountable SOICs; the A6801SA in a 22-pin DIP with 0.400” (10.16 mm) row centers; the A6801SEP in a 28-lead PLCC. These devices are lead (Pb) free, with 100% matte tin plated leadframes. FEATURES 3.3 V to 5 V logic supply range To 10 MHz data input rate High-voltage, high-current outputs Darlington current-sink outputs, with improved low-saturation voltages CMOS, TTL compatible inputs Output transient protection Internal pull-down resistors Low-power CMOS latches APPLICATIONS Relays Lamps Solenoids Small dc motors Use the following complete part numbers when ordering: Part Number Pins Package A6800SA-T 14 DIP A6800SL-T 14 SOIC A6801SA-T 22 DIP A6801SEP-T 28 PLCC A6801SLW-T 24 SOIC Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers Functional Block Diagram C OMMON S UP P LY V DD OUT N IN N S T R OB E G R OUND C LE AR OUT P UT E NAB LE T Y P IC AL MOS LAT C H T Y P IC AL B IP OLAR DR IV E C OMMON MOS C ONT R OL Allowable Power Dissipation Typical Input Circuit 2.5 VDD 22-P IN DIP , R θJA = 56°C /W 28-LE AD P LC C , R θJA = 68°C /W 14-P IN DIP , R θJA = 73°C /W P A C K A G E P OWE R DIS S IP A T ION (W) IN 2.0 24-LE AD S OIC , R θJA = 85°C /W 1.5 1.0 0.5 14-LE AD S OIC , R θJA = 120°C /W 0 25 50 75 100 125 150 A MB IE NT T E MP E R A T UR E (º C ) www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Vdd = 3.3 V Characteristic Min. Typ. Typ. Max. Units VOUT = 50 V – – 10 – – 10 µA IOUT = 350 mA, L = 3 mH 35 – – 35 – – V IOUT = 100 mA – 0.8 1.0 – 0.8 1.0 V IOUT = 200 mA – 0.9 1.1 – 0.9 1.1 V Symbol Output Leakage Current ICEX Output Sustaining Voltage VCE(SUS) Collector-Emitter Saturation Voltage VCE(SAT) Test Conditions IOUT = 350 mA (See note 2) Input Voltage Input Resistance Logic Supply Current Vdd = 5 V Max. Min. – 1.0 1.3 – 1.0 1.3 V VIN(1) 2.2 – – 3.3 – – V VIN(0) – – 1.1 – – 1.7 V RIN 50 – – 50 – – kΩ IDD(1) One output on, IOUT = 100 mA – – 1.0 – – 1.0 mA IDD(0) All outputs off – 130 150 – 130 150 µA Clamp Diode Leakage Current Ir Vr = 50 V – – 50 – – 50 µA Clamp Diode Forward Voltage Vf If = 350 mA – – 2.0 – – 2.0 V Output Fall Time tf VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – 80 – – 80 – ns Output Rise Time tr VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – 100 – – 100 – ns 1 Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1. 2 Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle. Truth Table IN N S T R OB E CLE AR 0 1 X X X X 1 1 X X 0 0 0 0 1 X 0 0 OUT P UT OUT N E NA B L E t-1 t 0 0 X 1 0 0 X X X X ON OF F OF F ON OF F OF F ON OF F X = irrelevant t-1 = previous output s tate t = pres ent output s tate www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) CLEAR H STROBE A C OUTPUT ENABLE B C B C A G B I INN D E F G E OUTN Key Description Time (ns) A Minimum data active time before Strobe enabled (Data Set-Up Time) 25 B Minimum data active time after Strobe disabled (Data Hold Time) 25 C Minimum Strobe pulse width 50 D Maximum time between Strobe activation and transition from output on to output off* 500 E Minimum time between Strobe activation and transition from output off to output on* 500 F Maximum time between Output Enable activation and transition from output on to output off* 500 G Minimum time between Output Enable activation and transition from output off to output on* 500 H Minimum Clear pulse width 50 I Minimum data pulse width 100 *Conditions for output transition testing are: VDD = 50 V, VCC = 5 V, R1 = 500 Ω, C1 ≤ 30 pF. NOTE: Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output off condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the off contdition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers A6800SL A6801SA 1 14 A6800SA CLEAR 1 22 OUTPUT ENABLE STROBE 2 VDD 21 SUPPLY 14 OUTPUT ENABLE IN 1 3 20 OUT 1 STROBE 2 VDD 13 SUPPLY IN 2 4 19 OUT 2 IN 1 3 12 OUT 1 IN 3 5 18 OUT 3 IN 2 4 11 OUT 2 IN 4 6 17 OUT 4 IN 3 5 10 OUT 3 IN 5 7 16 OUT 5 IN 4 6 9 OUT 4 IN 6 8 15 OUT 6 GROUND 7 8 COMMON IN 7 9 14 OUT 7 IN 8 10 13 OUT 8 GROUND 11 12 COMMON Dwg. PP-014A Note: The A6800SL (SOIC) and the A6800SA (DIP) are electrically identical and share a common terminal number assignment. LATCHES 1 LATCHES CLEAR Dwg. PP-015 OUT1 6 OUT 2 IN 3 7 23 OUT 3 IN 4 8 22 OUT4 IN 5 9 SUPPLY 3 22 OUT 1 IN 2 4 21 OUT 2 IN 3 5 20 OUT 3 IN 4 6 19 OUT 4 IN5 7 18 OUT 5 IN 6 8 17 OUT 6 IN 7 9 16 OUT 7 IN 8 10 15 OUT 8 GROUND 11 14 COMMON NO CONNECTION 12 13 NO CONNECTION 2 IN1 OUT8 16 15 GROUND 17 NC OUT7 LAMP DIODE COMMON VDD 18 19 K IN 7 11 14 NC OUT 6 13 NC 20 12 23 STROBE 21 OUT 5 IN 6 10 IN 8 OUTPUT ENABLE 1 LATCHES 25 24 LATCHES 5 IN 2 IN1 24 CLEAR NC 27 SUPPLY A6801SLW 26 V DD CLEAR 1 28 OUTPUT ENABLE C OE 2 NC 3 ST NC 4 STROBE A6801SEP NC Dwg. PP-037 NC Dwg. PP-015-1 www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers TYPICAL APPLICATION UNIPOLAR STEPPER-MOTOR DRIVE +30 V OUT P UT E NAB LE (AC T IV E LOW) C LE AR S T R OB E 1 14 2 V DD 13 3 12 V DD ∝ IN 2 IN 3 IN 4 4 5 LAT C HE S IN 1 OUT 1 OUT 2 11 OUT 3 10 OUT 4 6 9 7 8 A6800S A +30 V Dwg. No. B -1537 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE S T R OB E S T R OB E IN 1 IN 1 IN 2 IN 2 IN 3 IN 3 IN 4 IN 4 OUT 1 OUT 1 OUT 2 OUT 2 OUT 3 OUT 3 OUT 4 OUT 4 Dwg. G P -060 www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. G P -060-1 6 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers A6800SA Dimensions in Inches (controlling dimensions) 0.014 0.008 8 14 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 0.775 0.735 7 BSC 0.005 MIN 0.210 MAX 0.150 0.115 0.015 MIN 0.022 0.014 Dwg. MA-001-14A in Dimensions in Millimeters (for reference only) 0.355 0.204 8 14 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 19.68 18.67 BSC 7 0.13 MIN 5.33 MAX 0.39 3.81 2.93 MIN 0.558 0.356 Dwg. MA-001-14A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers A6800SL Dimensions in Inches (for reference only) 14 8 0.0098 0.0075 0.1574 0.1497 0.020 0.013 0.2440 0.2284 1 2 3 0.050 0° TO 8° BSC 0.3444 0.3367 0.050 0.016 0.0688 0.0532 0.0040 MIN. Dwg. MA-007-14 in Dimensions in Millimeters (controlling dimensions) 14 8 0.25 0.19 4.00 3.80 0.51 0.33 6.20 5.80 1 2 1.27 3 8.75 8.55 BSC 1.27 0.40 0° TO 8° 1.75 1.35 0.10 MIN. NOTES: 1. 2. Dwg. MA-007-14A mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers A6801SA Dimensions in Inches (controlling dimensions) 22 0.015 0.008 12 0.500 MAX 0.380 0.330 0.400 BSC 1 2 0.070 0.030 3 11 0.100 1.120 1.050 0.005 BSC MIN 0.210 MAX 0.015 0.160 0.115 MIN 0.022 0.014 Dwg. MA-002-22 in Dimensions in Millimeters (for reference only) 22 0.381 0.204 12 12.70 MAX 9.65 8.39 10.16 BSC 1 2 0.070 0.030 3 2.54 28.44 26.67 11 0.13 BSC MIN 5.33 MAX 0.39 4.06 2.93 MIN 0.558 0.356 Dwg. MA-002-22 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 9 DABiC-5 Latched Sink Drivers A6801SEP Dimensions in Inches (controlling dimensions) 18 0.013 0.021 12 19 0.219 0.191 11 0.026 0.032 0.456 0.450 INDEX AREA 0.495 0.485 0.050 BSC 0.219 0.191 25 5 26 0.020 28 1 4 0.456 0.450 0.495 0.485 MIN 0.165 0.180 Dwg. MA-005-28A in Dimensions in Millimeters (for reference only) 18 0.331 0.533 12 19 5.56 4.85 11 0.812 0.661 11.58 11.43 12.57 12.32 1.27 INDEX AREA BSC 5.56 4.85 25 5 26 0.51 28 1 4 11.582 11.430 12.57 12.32 MIN 4.57 4.20 Dwg. MA-005-28A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 10 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers A6801SLW Dimensions in Inches (for reference only) 24 13 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0.6141 0.5985 0° TO 8° BSC 0.0926 0.1043 Dwg. MA-008-24A in 0.0040 MIN. Dimensions in Millimeters (controlling dimensions) 24 13 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 15.60 15.20 BSC 0° TO 8° 2.65 2.35 0.10 MIN. NOTES: 1. 2. Dwg. MA-008-24A mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 11 Datasheet 26180.110 A6800/A6801 DABiC-5 Latched Sink Drivers The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2003, 2004, 2005 Allegro Microsystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 12 Datasheet 26180.110 A6800/A6801