A Semtech Company Technical Reference Manual USAR ACPITroller™ 342 System Management Family UR8HC342 HID & ACPI Embedded Controller Confidential Preliminary Document Number: DOC8-342-TR-080 Date: September 2000 © 1999-2000 USAR − A Semtech Company USAR − A Semtech Company INTELLECTUAL PROPERTY DISCLAIMER This specification is provided “as is” with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. A license is hereby granted to reproduce and distribute this specification for internal use only. No other license, expressed or implied to any other intellectual property rights is granted or intended hereby. Authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. Authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. ACPITroller™ Basic UR8HC342 Preliminary system management controller product Table of contents USAR − A Semtech Company Table of contents Chapter 1 / Introduction Document revisions 1-1 Overview 1-3 Scope of this document 1-4 Features at a glance 1-5 Pin overview 1-6 Pin usage 1-7 Pin description 1-8 USAR ACPITroller™ sample configuration 1-11 Chapter 2 / Human input device controller interface HIDC bus interface 2-1 USAR ACPITroller™ HIDC registers 2-2 HIDC commands 2-5 PS/2 information registers 2-12 Chapter 3 / AlphaKey™ keyboard manager Overview 3-1 USAR AlphaKey™ features at a glance 3-3 USAR AlphaKey™ hardware configuration 3-3 PS/2 keyboard protocol command and data handling 3-6 USAR AlphaKey™ keyboard matrix 3-8 USAR AlphaKey™ key numbers 3-9 © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential TOC-1 USAR − A Semtech Company Table of contents ACPITroller™ Basic UR8HC342 Preliminary system management controller product Chapter 4 / AlphaMouse™ pointing devices manager Overview 4-1 Multiplex mode 4-2 Legacy mode 4-3 Chapter 5 / Embedded controller interface UR8HC342 EC bus interface 5-1 UR8HC342 embedded controller registers 5-2 Port Operation 5-4 EC Commands 5-6 Chapter 6 / SCI & SWI interrupt generation Event interrupts 6-1 Interrupt generation 6-4 Chapter 7 / SMBus host controller interface Overview 7-1 SMBus overview 7-1 The SMBus host controller interface 7-1 SMBus alarm message & SMBus alert process 7-2 SMBus error recovery 7-3 SMBus host register space 7-3 SMBus host registers 7-3 Chapter 8 / General input/output options Internal virtual SMBus device TOC-2 8-1 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Table of contents USAR − A Semtech Company GIO0: LED driver 8-3 GIO1: Analog output for flat panel digital controls 8-5 GIO2: 3-channel 10-bit analog to digital converter 8-10 GIO3: general purpose I/O 8-12 Chapter 9 / Electrical characteristics Absolute maximum ratings Recommended operating conditions / electrical characteristics – Digital section Recommended operating conditions / electrical characteristics – Analog section Chapter 10 / Sample schematic Appendix A USAR AlphaKey™ standard PS/2 key number definitions A-1 Appendix B USAR AlphaKey™ default keyboard matrix and layout B-1 Appendix C Standard SMBus registers C-1 Standard SMBus protocol C-6 © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential TOC-3 USAR − A Semtech Company Table of contents ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank TOC-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Introduction Document revisions Document revision history Date 1999/07/28 1999/09/14 Version 0.60 0.70 2000/09/11 0.80 © 1999-2000 USAR − A Semtech Company Comments Initial draft Incorporated technical corrections and clarifications; grayed out features that are still in development Incorporated technical corrections and clarifications DOC8-342-TR-080 Confidential 1-1 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 1-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Introduction USAR − A Semtech Company USAR ACPITroller™ technical reference introduction Overview The UR8HC342 is a single IC that functions both as an 8042-type Human Input Device Controller (HIDC) and an ACPI-compliant Embedded Controller (EC). The UR8HC342 provides the typical functionality of an 8042-type HID Controller with embedded key and motion scanning. In addition, the UR8HC342 functions as an ACPI compliant Embedded Controller (EC) and SMBus host. The IC achieves unparalleled minimum power consumption (typically less than 1µA) due to USAR’s patented Zero-Power™ technologies for both PS/2 ports and the SMBus port – an industry first. The USAR ACPITroller™ can power down even when devices are connected and active. Based on USAR’s patented Zero-Power™ technology, the UR8HC342 always operates in the “STOP” mode, independently of the configuration and without any data or event losses. The USAR AlphaKey™ keyboard manager, implemented in the UR8HC342, provides OEMs with the most advanced and versatile keyboard management functions, including keyboard matrix programming. The USAR AlphaMouse™ pointing device manager supports MouseWheel operation, recommended by Microsoft, for both the embedded and the hotplugged external pointing devices. Using the UR8HC342, system designers can implement systems that take advantage of the SMBus, the Smart Battery System, and the ACPI specifications, all using a single IC. The UR8HC342 uses USAR’s patented Zero-Power™ SMBus technology and is the lowest power consumption IC in the market today. The UR8HC342 can be customized easily through an extensive library of hardware and firmware modules in order to accommodate specialized configurations at low production cost. SMBus Host The IC manages one hardware SMBus port. The IC complies with version 1.0 of the Smart Battery System (SBS) and SMBus specifications. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 1-3 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product Scope of this document This is a preliminary document. Although all the functions described in this document have been tested in USAR’s laboratories, the document may contain errors and inaccuracies. Prior to committing to design, consult with USAR for up to date revisions. Some features described in this document are still in development; these features are identified by grayed-out text. USAR has used every effort to design the part in the best manner to serve the current industry needs. Nevertheless, input from OEMs for both function and configuration is appreciated and may result in future modifications and enhancements. This document is still in a confidential state, as printed on the bottom of each page, and it cannot be distributed without explicit permission from USAR. Please forward all your comments or questions regarding this product and document to: [email protected] USAR Systems, Inc. 568 Broadway New York, NY 10012 212.226.2042 Telephone 212.226.3215 Telefax Evaluation kits For information or to order a USAR ACPITroller™ evaluation kit, send your email to: [email protected] 1-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Introduction USAR − A Semtech Company Features at a glance • Typical power consumption of less than 1µA as a result of USAR’s patented Zero-Power™ technologies; the IC can power down even when devices are connected and active • Patented Zero-Power™ operation of all PS/2 ports and the SMBus port – an industry first • AlphaMouse™ pointing device manager supports hot-plugging and hotswapping of standard two-button and three-button mice without a special driver; it also supports hot-plugging and hot-swapping of MouseWheel mice with a MouseWheel-capable driver • Two external PS/2 ports for external keyboard and mouse with auto-detect and hot-plug support • Simultaneous operation of external and internal input devices • Support of MouseWheel functionality for both embedded and external pointing devices, even with hot-plug connections, with a MouseWheelcapable driver • 8042-compatible host interface and functionality • 8 x 16 fully programmable scanned keyboard matrix • Support of all three keyboard scan code sets • ACPI EC host interface • Support of up to 6 ACPI GPE interrupt inputs • ACPI Power Button and Power Button Override support • SMBus compatible host complies with version 1.0 of the SBS/SMBus specifications • Blocks potentially dangerous Smart Battery System commands (write charger voltage and write charger current) issuing from the host system • Up to three 10-bit A/D inputs • Two D/A and two PWM outputs • Easily customized for specialized applications • Three-volt and five-volt operation • AlphaMouse™ performs active PS/2 multiplexing of input from different types of mice simultaneously, with the appropriate driver(s) • Support of the USAR ScreenCoder™ PS/2 absolute and relative touchscreen encoder, with the appropriate driver • Support of the five-button mouse, with an appropriate driver © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 1-5 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product Pin overview The figure below illustrates the pins for the UR8HC342 implementation for the FQ package. GIO11/PWM2/GPE1 GIO10/PWM1/GPE0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VCC VREF AVSS ROW7 ROW6 ROW5 ROW4 SMBEN GIO22/AN2 GIO21/AN1 80 61 1 60 IVSD20/AN0 SCL0 SDA0 PS21CLK PS20CLK IMCLK PS21DAT PS20DAT IMDAT GIO13/DA2/PWM2 GIO12/DA1/PWM1 GIO37/GPE7/DOCK GIO36/GPE6/LID IOW IOR 8042S A2 ACPIS SCI KBINIT GIO32/GPE2/PWBUTTON GIO33/GPE3/PWBOVERRIDE GIO34/GPE4 GIO35/GPE5 SMBINT KEYWKUP COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 COL12 COL13 URHC342- 20 21 1-6 A20GATE IRQ12 IRQ1 CNVSS RESET SYSSUS SWI XIN XOUT VSS GIO03/KATAKANALED GIO02/CAP_LOCK GIO01/NUM_LOCK IGIO00/SCROLL_LOCK ROW3 ROW2 ROW1 ROW0 COL15 COL14 41 DOC8-342-TR-080 Confidential 40 © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Introduction USAR − A Semtech Company Pin usage © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 1-7 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product Pin description The following table describes the pins of the USAR UR8HC342 ACPITroller™. Note: If a pin is active low, then there is an overscore over the pin name in schematics, and there is a single underscore character (_) preceding the pin name in tables and text; for example, _RESET. ACPITroller™ pin descriptions Pin Name Pin no. Description Power Supply AVSS 73 Analog signal ground CNVSS 24 Should be tied to ground VCC 71 Vcc 3-5 volts VREF 72 Analog circuitry reference voltage VSS 30 Ground Oscillator pins XIN 28 Oscillator input (8 MHz operating frequency) XOUT 29 Oscillator output Reset _RESET 25 Controller hardware reset pin System bus interface pins _8042S 16 8042 keyboard controller port select signal input _ACPIS 18 ACPI embedded controller port select signal input _IOR 15 X-bus/ISA I/O read signal input _IOW 14 X-bus/ISA I/O write signal input IRQ1 23 Keyboard interrupt output IRQ12 22 Mouse interrupt output _KBINIT 20 Keyboard initialize output A2 17 X-bus/ISA address 2 input A20GATE 21 A20 Gate output signal DQ0 70 X-bus/ISA parallel data I/O ports DQ1 69 DQ2 68 DQ3 67 DQ4 66 DQ5 65 DQ6 64 DQ7 63 1-8 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Introduction USAR − A Semtech Company ACPITroller™ pin descriptions Pin Name Pin Description no. ACPI, SMBus, and general purpose I/O signals 19 System control interrupt output SCI _SMBINT 56 SMBus interrupt input _SWI 27 System wake-up event interrupt output _SYSSUS 26 System suspend input GIO00 34 This pin can be programmed to act as a keyboard LED or as a /SCROLL_LOCK GPIO pin. GIO01/NUM_LOCK 33 This pin can be programmed to act as a keyboard LED or as a GPIO pin. GIO02/CAP_LOCK 32 This pin can be programmed to act as a keyboard LED or as a GPIO pin. GIO03 31 This pin can be programmed to act as a keyboard LED or as a /KATAKANALED GPIO pin. GIO10/PWM1/GPE0 62 GIO1 bit 0 or PWM output or ACPI GPE GIO11/PWM2/GPE1 61 GIO1 bit 1 or PWM output or ACPI GPE GIO12/DA1/PWM1 11 This pin can be configured as GPIO, as D/A output, or PWM output. GIO13/DA2/PWM2 10 This pin can be configured as GPIO, as D/A output, or PWM output. GIO20/AN0 1 This pin can be configured as a 10-bit A/D input or logic I/O. GIO21/AN1 80 This pin can be configured as a 10-bit A/D input or logic I/O. GIO22/AN2 79 GIO2 bit or A/D input GIO36/GPE6/LID 13 GIO3 bit 0 or ACPI general purpose event (GPE); capable of detecting both negative and positive signal transitions; typically serves the LID ACPI function GIO37/GPE7/DOCK 12 GIO3 bit 1 or ACPI GPE; capable of detecting both negative and positive signal transitions; typically serves the DOCK ACPI function GIO32/GPE2 60 GIO3 bit 2 or ACPI GPE; typically an ACPI ""Power Button"" input. /_PWBUTTON GIO33/GPE3 59 GIO3 bit 3 or ACPI GPE; typically an ACPI ""Power Button /_PWBOVERRIDE Override"" input GIO34/GPE4 58 GIO3 bit 4 or ACPI GPE 4 GIO35/GPE5 57 GIO3 bit 5 or ACPI GPE 5 SCL0 2 This pin acts as the clock line for the SMBus SDA0 3 This pin acts as the data line for the SMBus © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 1-9 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product ACPITroller™ pin descriptions Pin Name Pin Description no. ACPI, SMBus, and general purpose I/O signals SMBEN 78 This output pin allows the SMBus latch to notify the ACPITroller™ when SMBus activity has been detected. It is used to wake the ACPITroller™ from sleep mode, and to disable all PS/2 inputs while SMBus processing is taking place. Scanned matrix pins COL0 54 Column matrix outputs COL1 53 COL2 52 COL3 51 COL4 50 COL5 49 COL6 48 COL7 47 COL8 46 COL9 45 COL10 44 COL11 43 COL12 42 COL13 41 COL14 40 COL15 39 KEYWKUP 55 Key wake-up output ROW0 38 Row matrix inputs ROW1 37 ROW2 36 ROW3 35 ROW4 77 ROW5 76 ROW6 75 ROW7 74 PS/2 ports IMCLK 6 PS/2 clock line for internal mouse IMDAT 9 PS/2 data line for internal mouse PS20CLK 5 Clock line for external PS/2 port 0; both external PS/2 ports support hot-plug ins and auto-select for keyboard or mouse PS20DAT 8 Data line for external PS/2 port 0 PS21CLK 4 Clock line for external PS/2 port 1 PS21DAT 7 Data line for external PS/2 port 1 1-10 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Introduction USAR ACPITroller™ sample configuration The USAR ACPITroller™ is a highly versatile part that can be configured to accommodate different OEM configurations. The block diagram below illustrates the major functional components of the USAR ACPITroller™ in a simple configuration. USAR ACPITroller™ sample configuration 3 x PS/2 Ports IRQ1 8 x 16 Matrix IRQ12 GPIO 4 4 bit port expander 2 10 bit A/D GIO0 KBINIT A20Gate D0-D7 PIO eyboard Controller KBC 8 KBC Data Register ACPIS 8042S 8042 Registers A/D GIO2 D/A, PWM 2 GIO1 PWBOVERRIDE KBC Control/StatusB IOW, IOR, A2 PWBUTTON GPE Embedded Controller SCI EC Data Register ACPI 4 GPEx 2 SMBus GIO3 EC Registers SWI Brightness/ Contrast EC Control/Status SMBus Host SMBINT SMBEN Simple configuration block diagram of UR8HC342 In the configuration shown above the USAR ACPITroller™ is configured to provide besides the basic EC and KC functionality the following: • Power button and power button override function implemented on GPE pins • 4 general-purpose I/O pins • 4 additional GPE inputs • 3 pins that can be configured as 10 bit A/D channels or GPIO • 2 pins that can be configured as D/A or PWM outputs or GPIO • One Zero-Power SMBus port © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 1-11 USAR − A Semtech Company Introduction ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 1-12 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product HID controller interface USAR − A Semtech Company USAR ACPITroller™ human input device controller (HIDC) interface HIDC bus interface The Human Input Device Controller (HIDC) portion of the USAR ACPITroller™ interfaces to the host ISA bus via two I/O addresses, generally 0x60 and 0x64. The following diagram illustrates the HIDC register architecture. Data Write HIDC DATA INPUT REGISTER (60h) Data Read HIDC DATA OUTPUT REGISTER (60h) 8042 HID CONTROLLER RAM REGISTER AND ISA EXPANDED PROGRAM MEMORY Status Read HIDC COMMAND/STATUS REGISTER (64h) Command Write KBD Interrupt Mouse Interrupt Gate A20 HIDC Reset USAR ACPITroller™ HID Controller Interface © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 2-1 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR ACPITroller™ HIDC registers The HIDC portion of the USAR ACPITroller™ contains three registers that occupy two I/O locations. The registers are listed in the following table: HIDC registers Name Description I/O function HIDC_SC(W) HIDC_SC(R) HIDC_DATA Command Status Data IOW IOR IOR/IOW I/O Port Address 0x64 0x64 0x60 HIDC Status Register, HIDC_SC (R) The HIDC Status Register is a read-only register that indicates the current status of the Keyboard Controller interface. It contains the following fields: HIDC_SC (R) status register bit definitions 2-2 bit7 HIDC_PE bit6 HIDC_GTO bit5 HIDC_AOBF bit4 HIDC_INH bit3 HIDC_CMD bit2 HIDC_SF bit1 HIDC_IBF bit0 HIDC_OBF DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product HID controller interface USAR − A Semtech Company HIDC_SC (R) status register bit descriptions HIDC_PE HIDC_GTO HIDC_AOBF HIDC_INH HIDC_CMD HIDC_SF HIDC_IBF HIDC_OBF Parity Error 1 – Indicates a parity error. In this case 0xFF is placed in the data register 0 – Indicates that the last byte of data received from the PS/2 device had odd parity General Time-Out 1 – Indicates that a time-out occurred during a transaction with one of the PS/2 devices. The HIDC_GTO is set in any of the following situations: – Reception of a byte from a PS/2 device started but did not complete within the Receive Time Out limit. The HIDC places 0xFF into the data register – A transmission started by the HIDC to a PS/2 device, but was not completed within the Transmit Time Out limit. The HIDC places 0xFE into the data register – A byte requiring response (command) was clocked out to a PS/2 device but it was not acknowledged within the ACK Time Limit – A command byte was clocked out and a response was received with a parity error. In this case both HIDC_GTO and HIDC_PE are set 0 – No Time-Out Auxiliary Output Buffer Full This bit works in conjunction with HIDC_OBF (Output Buffer Full) bit 1 – When HIDC_OBF is also set, indicates that data from the Auxiliary device is pending in the data register 0 – When HIDC_OBF is set, indicates that Keyboard data or a HIDC response is pending in the data register Inhibit Switch 1 – Keyboard is enabled 0 – Password state is active and the keyboard is inhibited (For more information, see section below on Password Protection) Command/Data 1 – Data register contains a command byte (set by the host, read by the HIDC) 0 – Data register contains a data byte (set by the host, read by the HIDC) System Flag 1 – The System Flag bit in the Controller Command byte is set to one 0 – The System Flag bit in the Controller Command byte is set to zero (default after reset) Input Buffer Full 1 – Input buffer is full (data has been written in the data register but has not been read by the HIDC) 0 – Input buffer is empty (data has been read by the HIDC) Output Buffer Full 1 – Data ready for host in the Data Register (generate appropriate interrupt) 0 – Data has been read by the host (set automatically after an IO read operation) Command register, HIDC_SC (W) The HIDC_SC (W) command register is a write-only register that allows commands to be issued to the keyboard controller. Write operations to this port are latched into the input data register; the input buffer full (HIDC_IBF) flag is set in the status register. Writes to this location also cause the HIDC_CMD (Command/Data) bit to be set in the status register. This © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 2-3 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product enables the keyboard controller to differentiate the start of a command sequence from a data byte write operation. Data Register, HIDC_DATA(R/W) The HIDC_DATA(R/W) data register is a read/write register that allows command/data bytes to be issued to the keyboard controller while also enabling the host system to read data returned by the keyboard controller. Writes to this port are latched into the input data register; the input buffer full (HIDC_IBF) flag is set in the status register. Data written by the system into this register is generally transmitted to the appropriate PS/2 device, unless the HIDC expects a data byte as part of a command sequence. Reads from this register return data from the output data register and clear the output buffer full (HIDC_OBF) flag in the status register. 2-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product HID controller interface USAR − A Semtech Company HIDC Commands Any byte written by the host system into the HIDC_SC register is interpreted as a command. The USAR ACPITroller™ supports all the standard 8042 commands, as well as expanded commands, as described below. Standard 8042 commands Hex Value 20 21-3F 60 61-7F A4 A5 A6 A7 A8 A9 AA AB AD AE C0 C2-C3 D0 D1 D2 D3 © 1999-2000 USAR − A Semtech Company Description Read Controller Command byte Read HIDC RAM Registers. Address is specified by bit0-bit5 Write Controller Command byte. The following byte is data Write HIDC RAM Registers. Address is specified by bit0-bit5, and the following byte is data Test Password Installed. The result is placed in the data buffer as follows: – 0xFA – installed – 0xF1 – not installed (See below) Load Password. Data follows until a null (0) is detected (See below) Enable Password. This command is valid only when a password is loaded in the controller (See below) Disable Auxiliary Device Interface. This command sets bit 5 of the Controller Command byte and disables the Auxiliary Device clock line Enable Auxiliary Device Interface. This command clears bit 5 of the Controller Command byte and enables the Auxiliary Device clock line Auxiliary Device Interface Test. Test results are returned in the data buffer as follows: – 00 – No error – 01 – Clock line stuck low – 02 – Clock line stuck high – 03 – Data line stuck low – 04 – Data line stuck high Controller self test, Return 55. Keyboard Device Interface Test. Test results are returned in the data buffer as follows: – 00 – No error – 01 – Clock line stuck low – 02 – Clock line stuck high – 03 – Data line stuck low – 04 – Data line stuck high Disable Keyboard Interface. This command sets bit 4 of the Controller Command byte and disables the Keyboard clock line Enable Keyboard Interface. This command clears bit 4 of the Controller Command byte and enables the Keyboard clock line Read Input Port and place data in the data register Poll Input Port and update bit7-bit4 of the Status Register Read Output Port and place data in the data register Write Output Port. The next byte is written to the HIDC Output Port Write Keyboard Output Buffer. The next byte is played back as if originating from the keyboard Write Auxiliary Device Output Buffer. The next byte is played back as if originating from the Auxiliary Device DOC8-342-TR-080 Confidential 2-5 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product Standard 8042 commands Hex Value D4 E0 F0-FF Description Write to Auxiliary Device. The next byte is transmitted to the Auxiliary Device Read Test Inputs. Returns 0 (Type 1 controller) Pulse Output Port. This command pulses Output Port bits, defined by bit0bit3, for approximately 6 us. Keyboard password The USAR ACPITroller™ supports keyboard password functionality. There are three commands associated with the password operation. • Load Password (0xA5) • Test Password Installed (0xA4) • Enable Password (0xA6) The password can be loaded into the USAR ACPITroller™ RAM area by the system at any time, using the “Load Password” command. The password can be up to seven bytes long and is loaded using Scan Code 1 (scan codes provided by the system). The system can check if a password is installed using the “Test Password Installed” command. If a password is already installed, the system can enable the password by issuing the “Enable Password” command. While the password is enabled, the HIDC enters the secure mode and behaves as follows: 1. The HIDC intercepts any incoming code stream from the keyboard and compares it with what is installed in the RAM password pattern. The HIDC discards any code from the keyboard and the auxiliary device that does not match the password. If an incoming code does not match either the next character in the pattern or the contents of RAM Register addresses 0x16 and 0x17, the HIDC resets its password pointer and the next incoming code is compared to the first byte of the password pattern. 2. While in secure mode, the HIDC does not pass any codes to the system or accept any commands. 3. After a match occurs, the HIDC resumes normal operation and starts passing codes to the host system. 2-6 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product HID controller interface USAR − A Semtech Company There are four HIDC RAM Registers related to the password operation: Password associated RAM registers RAM Register Security on Address Description 13H Security off 14H Make 1 & 2 16H, 17H When the password is enabled, a non-zero value in this register forces the HIDC to output the contents of the register into the Data Register and issue IRQ1 When the password is matched, a non-zero value forces the HIDC to output the register contents into the Data Register and issue IRQ1 These registers can be loaded by the system with scan codes that should be ignored during the password match process (i.e., shift codes) HIDC RAM registers The HIDC has on-board RAM registers, listed in the table below. HIDC RAM Registers are accessed for read and write operations through the Read/Write HIDC RAM Register commands. A description of specific RAM registers follows. HIDC RAM registers Address Offset Description of Register 00 Controller Command byte (Read or Write) 01-12 Not defined, system use 13 Security on 14 Security off 16-17 Make 1 and 2 © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 2-7 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product Controller command byte The Controller Command byte occupies address offset zero in the HIDC RAM Register space. The Controller Command byte can be accessed through general Read/Write or specific commands and contains the following bits: Controller command byte bit definitions bit7 RES bit6 TRS bit5 ADIS bit4 KDIS bit3 RES bit2 SF bit1 AIRQ bit0 KIRQ Controller command byte bits descriptions RES TRS ADIS KDIS SF AIRQ KIRQ 2-8 Reserved Keyboard Translate 1 – Sets keyboard translation from Scan Code Set 2 to Scan Code Set 1 0 – Disables keyboard scan code translation Disable Auxiliary Device 1 – HIDC disables the Auxiliary device by pulling the clock line low 0 – HIDC enables the Auxiliary device Disable Keyboard 1 – HIDC disables the keyboard by pulling the clock line low 0 – HIDC enables the keyboard System Flag The value written in this bit is placed in the relevant bit of the Status Register (system use) Enable Auxiliary Device Interrupts Setting this bit to 1 enables IRQ12 whenever an auxiliary device data byte is placed into the data register Enable Keyboard Interrupts Setting this bit to 1 enables IRQ1 whenever a keyboard data byte is placed into the data register DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product HID controller interface USAR − A Semtech Company Security on The Security On register is used for Keyboard Password functionality. When the password is enabled, a non-zero value in this register forces the HIDC to output the contents of the register into the Data Register and issue IRQ1. Security off The Security Off register is used for Keyboard Password functionality. When the password is matched, a non-zero value forces the HIDC to output the register contents into the Data Register and issue IRQ1. Make 1 and 2 These registers are used for Keyboard Password functionality and can be loaded by the system with scan codes that should be ignored during the password match process (i.e., shift codes). AlphaKey™ Control Register This register controls local handling of the PS/2 keyboard protocol, defines pins as GPIO or keyboard LEDs, and enables and disables programming of the embedded keyboard matrix. Functional details are described in full in the AlphaKey Keyboard Manager chapter. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 2-9 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product HIDC USAR expanded command set In addition to the standard 8042 commands, the HIDC section implements a set of Expanded Commands, defined by USAR in order to accommodate the special functions implemented in the USAR ACPITroller™ HID section. These commands provide BIOS, Drivers and application software with access to the following unique features of the USAR ACPITroller™: • Version control • OEM Programmable Area • Scanned Keyboard Matrix programmability HIDC expanded commands Hex Value B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD Description Read model number, 1Byte Bit7: – 0: Standard part – 1: Customized part Bit6-Bit0: model number A value of 01H denotes the basic configuration Read revision number, 1byte Write Program RAM Page Register Valid Values: 0, 1 Read Program RAM Page Register, 1 byte Write Program RAM Pointer Register Valid Values: 0 – FFh for page 0; 0 – 7Fh for page 1; Read Program RAM Pointer Register, 1 byte Write to Program RAM in given page and current address Read from Program RAM in given page and current address Write data block to Program RAM, starting at specified address. This command is followed by one byte block size, one byte address and data Read from Program RAM by specified address Download Whole Matrix Layout0, follow by 128 bytes matrix Download Whole Num Lock and Fn Matrix Layout, follow by 96 bytes matrix Download Whole Macro Function Pointer, follow by 16 bytes pointer Download Whole Macro Function Code, follow by 128 bytes code For commands B6 and B7, the RAM pointer register automatically increments after each byte is read or written. The increment wraps from FFh to 00h within RAM Page 0 (you cannot implicitly write to Page 1), and from 7Fh to 00h within RAM Page 1. For the download commands (BA, BB, BC, and BD), you must issue the command in the command/status register, than send each byte of data, one at a time, in the data register. You must verify that the input buffer full bit (bit 1 of the HIDC status register, as shown earlier in this chapter) has been cleared before sending the next byte. Each of these commands expects a 2-10 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product HID controller interface USAR − A Semtech Company fixed number of data bytes. The HIDC must read all of the expected bytes before another command issues. If a new command issues before all expected bytes are read, the download command aborts and the rest of the matrix is unchanged. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 2-11 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product PS/2 information registers Starting at offset 15 from the start of the 8042 extended register area, there are three read-only registers with information about the three PS/2 ports: registers R15-R17. R15: 8042 configuration register 0 bit definitions (R) bit7 MXEN bit 6 RES bit 5 M3PEND bit 4 M2PEND bit 3 M1PEND bit 2 M3DIS bit 1 M2DIS bit 0 M1DIS R15: 8042 configuration register 0 bit descriptions (R) RES MXEN M3PEND M2PEND M1PEND M3DIS M2DIS M1DIS reserved 1– Mouse multiplexing mode enabled by command 1– Mouse multiplexing mode command pending port 3 1– Mouse multiplexing mode command pending port 2 1– Mouse multiplexing mode command pending port 1 (internal) 1– Direct port 3 clock disable by command 1– Direct port 2 clock disable by command 1– Direct port 1 clock disable by command R16: 8042 configuration register 1 bit definitions (R) bit7 OK2 bit 6 KB2 bit 5 5BUT2 bit 4 WHEEL2 bit 3 OK3 bit 2 KB3 bit 1 5BUT3 bit 0 WHEEL3 R16: 8042 configuration register 1 bit descriptions (R) OK2 KB2 5BUT2 WHEEL2 OK3 KB3 5BUT3 WHEEL3 2-12 1– External device on port 2 initialized OK 1– Device on port 2 is a keyboard 0– Device on port 2 is a mouse 1– Device on port 2 is a 5-button mouse 1– Device on port 2 is a wheel mouse 1– External device on port 3 initialized OK 1– Device on port 3 is a keyboard 0– Device on port 3 is a mouse 1– Device on port 3 is a 5-button mouse 1– Device on port 3 is a wheel mouse DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company HID controller interface R17: 8042 configuration register 2 bit definitions (R) bit7 RES bit 6 RES bit 5 RES bit 4 RES bit 3 RES bit 2 OK1 bit 1 5BUT1 bit 0 WHEEL1 R17: 8042 configuration register 2 bit descriptions (R) RES OK1 5BUT1 WHEEL1 © 1999-2000 USAR − A Semtech Company reserved 1– Internal device on port 1 initialized OK 1– Device on port 3 is a 5-button mouse 1– Device on port 3 is a wheel mouse DOC8-342-TR-080 Confidential 2-13 USAR − A Semtech Company HID controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company This page intentionally left blank 2-14 ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company AlphaKey™ keyboard manager USAR UR8HC342 ACPITroller™ AlphaKey™ keyboard manager Overview The USAR AlphaKey™ keyboard manager is the most advanced keyboard management module in the industry today and the first one to integrate the laptop keyboard matrix with system management tasks through ACPI and SMBus. The USAR AlphaKey™ keyboard manager provides OEMs with extreme flexibility both with PS/2 keyboard functionality, as well as with user control, from the keyboard, of system management tasks through ACPI and SMBus. The USAR AlphaKey™ keyboard manager, as shown in the following diagram, communicates with the HID controller, the ACPI embedded controller, the virtual SMBus device manager and the external PS/2 ports of the USAR ACPITroller™. AlphaKey™ communications block diagram The USAR AlphaKey™ keyboard manager can simultaneously support both ® an external keyboard (including Windows and Japanese layout keyboards) HID Controller KBD ACPI EC 4 LEDs R0-R7 Keyboard Matrix Mouse C0-C15 AlphaKey™ Keyboard Manager Virtual SMBus Device Manager PS/2 Ports and an internal scanned key matrix. The internal scan matrix layout can be programmed through an extended set of keyboard commands. The USAR © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 3-1 USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaKey™ keyboard manager handles PS/2 keyboard commands, supports external keyboard hot-plug-ins, and merges internal and external keyboard data as if they were coming from one source. USAR AlphaKey™ features at a glance • Supports IBM standard 101/102 keyboards including Windows , On-Now Power keys, Japanese keyboard keys, and Korean keyboard keys. • External keyboard and internal keyboard operate simultaneously; data is merged • User can hot-plug external keyboard • Auto-detection of type of device in any external PS/2 port • N-key rollover and ghost key detection • Programmable scan matrix • Embedded numeric keypad support • Supports all three scan code sets • Interoperability between 3-volt systems and 5-volt PS/2 devices without any external level-shifting circuitry • Unique “Zero-Power” operation of the scanned matrix AND the PS/2 embedded port • “Protocol safe” handling of external PS/2 devices ® 3-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaKey™ keyboard manager USAR − A Semtech Company USAR AlphaKey™ hardware configuration The USAR AlphaKey™ keyboard manager interfaces directly to the signals of the scanned matrix, the external PS/2 ports and the LEDs’ port. This section describes the handling of the signal lines and the options OEMs have in configuring the hardware interfaces of the USAR AlphaKey™ keyboard manager. Scanned matrix The USAR AlphaKey™ embedded keyboard is organized as an 8 x 16 matrix. While the maximum matrix size and the organization of rows and columns are fixed, smaller matrixes can be accommodated. The USAR AlphaKey™ matrix comes configured with a default key layout described in Appendix B of this document. OEMs requiring a custom matrix layout are presented with the option to either order the ACPITroller™ delivered with their own matrix specification or use the programming facilities of the USAR ACPITroller™. Configuration of the matrix layout can be accomplished though the USAR Extended Command set of the HID controller (8042), and it is described in detail later in this section. Custom configuration information is stored in the AlphaKey™ RAM and has to be downloaded into the controller each time power is recycled. Alternatively, information can be stored permanently in the controller’s flash RAM area – if available – or in a EEPROM residing in one of the SMBus ports of the controller. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 3-3 USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product LED port The USAR AlphaKey™ keyboard manager supports up to four LEDs. Three LEDs correspond to the standard 101/102 PS/2 keyboard Numeric Lock, Caps Lock and Scroll Lock LEDs. The fourth LED is the Katakana LED used in Japanese keyboards. OEMs have the option either to utilize the LEDs or to disable them in order to use the LED port for other general input/output functions. The configuration of the LED port is in the AlphaKey™ control register, and it is described later in this section. External PS/2 ports The USAR AlphaKey™ supports three PS/2 ports, all of them functioning with USAR’s patented “Zero-Power™” operation. Each of the three PS/2 ports is available for either a PS/2 keyboard or a PS/2 mouse-type device. The USAR AlphaKey™ keyboard manager detects the hot-plug-in of an external keyboard, and integrates its data input with the input from the embedded keyboard matrix. The USAR AlphaKey™ responds to and implements every PS/2 keyboard command, and individually handles communications with externally connected keyboard devices. In addition to this mode, the USAR AlphaKey™ can support a pure 8042 type of operation, in which the externally connected keyboard provides the responses to the system-issued PS/2 commands. This mode is implemented in order to support proprietary devices that identify themselves as PS/2 keyboards; however, they require special drivers in order to operate properly. Setting the KLHDIS bit of the control register to one (1) activates the pure 8042 mode. While in this mode, only the first connected external PS/2 keyboard is enabled, in order to avoid conflicting responses from other devices to the custom driver. 3-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaKey™ keyboard manager USAR − A Semtech Company Auto-detection of device type in external PS/2 ports The USAR ACPITroller™ auto-detects the type of PS/2 device connected to either one of the two external PS/2 ports and configures the device properly according to the current system and driver settings. Users can connect any type of PS/2 device (keyboard or mouse) to either port. Data from any keyboard(s) detected are routed to the USAR AlphaKey™ keyboard manager for proper initialization and data handling. 3-volt and 5-volt operation of PS/2 ports The USAR ACPITroller™ can be powered by either a 3-volt or a 5-volt power supply. Even when powered by a 3-volt power supply, the USAR ACPITroller™ communicates flawlessly with 5-volt powered PS/2 devices, without any additional level-shifting circuit. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 3-5 USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product PS/2 keyboard protocol command and data handling The USAR AlphaKey™ fully implements the PS/2 keyboard command protocol including support for scan code set 3 specific commands. Support of scan code set 3 provides compatibility with all operating systems ported to the Intel x86 architecture. The USAR AlphaKey™ keyboard manager, which responds to and executes all PS/2 keyboard. The table below lists the PS/2 commands supported by AlphaKey™ as well as the corresponding responses to them. PS/2 command & response codes 3-6 Command FFh FEh FDh, XXh FCh, XXh FBh, XXh FAh F9h F8h F7h F6h F5h F4h F3h , XXh F2h F1h F0h, 00 – 03 Response Fah, AAh XXh Fah, FAh Fah, FAh Fah, FAh Fah Fah Fah Fah Fah Fah Fah Fah, FAh Fah, 8Xh, ABh Feh Fah, FAh, (0Xh) EFh EEh EDh, 0Xh Feh Eeh Fah, FAh Description Keyboard reset command Resend last byte transmitted Set key make (key) Set key make/break (key) Set key typematic (key) Set all keys typematic/make/break Set all keys make Set all keys make/break Set all keys typematic Set default Disable Enable Set typematic delay and rate (value) Read device ID Invalid command Set scan set (value) 0 = Programmable keyboard matrix Invalid command Echo Set LEDs (value) DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaKey™ keyboard manager USAR − A Semtech Company Protocol Safe™ handling of external PS/2 keyboards The USAR AlphaKey™ keyboard manager provides a level of protocol isolation between the external PS/2 keyboard(s) and the host system. Even when an external keyboard is connected, commands issued by the system are responded to and executed internally within the USAR AlphaKey™ keyboard manager. The USAR AlphaKey™ keyboard manager subsequently relays only relevant commands to the external device(s) and it processes locally any hand-shaking, including errors and recovery messages. This unique mode of operation provides the system with two benefits: • It isolates the system from bad implementations of the PS/2 keyboard protocol from external keyboards. The USAR AlphaKey™ directs to the external keyboard only the simplest commands required for data entry and LED handling and it handles internally the more complicated commands. It basically uses the external device the same way it handles the scanned matrix for pure key entry and it takes full responsibility of the protocol implementation. The system “sees” a consistent PS/2 keyboard protocol implementation independently of the PS/2 keyboard the user has connected to the external PS/2 ports. • It improves the system performance. Unlike keyboard controller implementations that rely on the external device to provide command responses, the USAR AlphaKey™ communicates quickly and efficiently through the X-bus, and hides from the system the overhead of low level PS/2 error handling. USAR AlphaKey™ Scan Code support USAR’s AlphaKey™ supports the IBM Standard Scan Code Sets 1, 2, and 3 ® for all keys, including Windows and the On-Now Power keys (Scan Code 1 & 2 only). © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 3-7 USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR AlphaKey™ keyboard matrix The USAR AlphaKey™ implements three distinct key layouts over the same keyboard matrix. Each keyboard matrix layout can be viewed as a separate keyboard selected and activated by the user through the Fn and Num Lock key. The default layout is QWERTY; this is the most commonly used layout, and it includes all keys needed for regular data entry. The NumPad layout can be invoked by setting the Num Lock LED on, and it implements a numeric keypad over part of the matrix for fast numeric entry. The Fn layout is invoked when the user presses the Fn key of the laptop keyboard, and it is used to activate special keys for system functions and custom data functions. The USAR AlphaKey™ is preprogrammed with a typical laptop keyboard matrix, implementing all three layouts. The preprogrammed matrix and layouts are described in Appendix B of this document. Keyboard matrix layouts The USAR AlphaKey™ keyboard manager maintains the keyboard matrix layout information in the controller’s Matrix RAM area which is described later in this chapter. After a power-on reset, the USAR AlphaKey™ defaults to Scan Set 1. Subsequently, the OEM can download a custom matrix and/or custom key definitions and assignments through BIOS, TSR programs or device driver software, and select Scan Set 0 to enable the custom matrix. The following table describes the matrix layouts supported by the USAR AlphaKey™. USAR AlphaKey™ matrix layouts Fn Key Up Up Down 3-8 Num Lock Off On X Description QWERTY layout NumPad layout Fn layout DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaKey™ keyboard manager USAR − A Semtech Company USAR AlphaKey™ key numbers The action invoked by a key press is determined primarily by the USAR key number assigned to the specific matrix location. Each matrix location has a USAR key number assigned to it. If a matrix location is empty (no physical switch), or if the switch should produce no action in specific layouts, the null key number can be assigned into the specific position. USAR has defined four distinct ranges of key numbers. The following table describes the USAR defined key number ranges for keys supported by the AlphaKey™ keyboard manager. USAR AlphaKey™ key number ranges Key numbers (hex) No of keys Category 00 - 7F 128 Standard PS/2 keys 80 - AF 48 Alternate layout keys (NumPad and Fn layouts) A description of the codes in each of these ranges follows. Standard PS/2 keys USAR AlphaKey™ uses 128 unique numbers 00-7Fh (0-127) to describe the Standard PS/2 keys implemented in most standard PS/2 keyboard layouts. The key numbers for Standard PS/2 keys are fixed and they are re-used. Note the following special key ranges: 0 1 - 101 102 – 104 105 106 107 108 – 110 111 – 115 124 – 132 Null key 101/102 Keyboard keys Windows keys. Overrun error Function (Fn) key Sticky mode key. This key is used to toggle the “sticky” mode of operation of the PS/2 shift keys (Ctrl, Shift, Alt, Win Keys) On-now Power keys. Japanese keyboard key numbers. Korean keyboard key numbers. Extended function keys F13 – F24 A list of the USAR Standard PS/2 key numbers appears in Appendix A of this document. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 3-9 USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product Alternate layouts keys (NumPad and Fn layouts) The USAR AlphaKey™ keyboard manager uses 48 distinct codes (80h – Afh) to describe a special range of keys that, in addition to their default QWERTY values, implement the NumPad and Fn layout translations. Each one of the “alternate layouts” keys has three key numbers associated with them which are programmable and kept in the Matrix RAM area of the controller. The output of an “alternate layouts” key is determined by the active matrix layout (QWERTY, NumPad or Fn). OEMs can define the output for each layout to be a Standard PS/2 key. The following drawings illustrate an example of an “alternate layouts” key. Esc F1 ~ ` ! 1 F2 @ 2 Q Tab F4 # 3 W Caps Lock A F5 $ 4 E S R X Ctrl F6 F7 % 5 D Z Shift Fn F3 ^ 6 & 7 T F C F8 Y G F11 ( 9 U Alt } ] " ' > . Delete SysRq Backspace { [ : ; < , Insert Prt Sc + = P L M Num Lk Scr Lk _ - O K N F12 ) 0 I J B F10 * 8 H V F9 | \ Shift Alt Home PgUp PgDn Enter ? / Pause Break End Ctrl Example 1: “Alternate layouts” key number DBh acts as the “J” when the QWERTY layout is active. Esc F1 ~ ` ! 1 Caps Lock F3 @ 2 Q Tab F4 # 3 W A Ctrl F5 $ 4 E S Z Shift Fn F2 F7 % 5 R D X F6 ^ 6 C & 7 T F Y G V F8 F10 * 8 Alt { [ : ; > . Alt Insert Prt Sc + = P L < , Num Lk Scr Lk _ - O K M F12 ) 0 I 1 N F11 ( 9 U H B F9 Backspace } ] " ' ? / Delete SysRq | \ Enter Shift Pause Break Home PgUp PgDn End Ctrl Example 2: The same key acts as the numeric keypad key “1”, when the NumPad layout is selected. 3-10 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Esc F1 ~ ` ! 1 Caps Lock F3 @ 2 F4 # 3 W A Ctrl F5 $ 4 E S Z Shift Fn F2 Q Tab USAR − A Semtech Company AlphaKey™ keyboard manager F7 % 5 R D X F6 ^ 6 C Y G V F9 & 7 T F F8 * 8 Alt M F12 ) 0 I null N F11 ( 9 U H B F10 _ - O K { [ : ; > . Alt Insert Prt Sc + = P L < , Num Lk Scr Lk Backspace } ] " ' ? / | \ Enter Shift Ctrl Example 3: When the Fn layout is active, the key acts as a “null” key. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential Delete SysRq 3-11 Pause Break Home PgUp PgDn End USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product The following table lists the default values of the “alternate layouts” keys. For each “alternate layouts” key number, three matrix RAM locations exist to store its key number values for each matrix layout. The OEM can program these RAM locations, using the “extended protocol” commands. Alternate layouts key numbers default values QWERTY layout Alt. Layout key # (Hex) 80 81 82 3-12 Matrix RAM USAR offset key # (Hex) (Hex) 80 2F 81 23 82 24 NumPad layout Key label M J K Matrix RAM offset USAR key # (Hex) A0 4A A1 41 A2 42 83 D4 83 84 25 L 16 U A3 A4 43 44 85 86 85 86 17 I 18 O A5 A6 45 46 87 88 87 88 08 7 / & 09 8 / * A7 A8 47 48 89 8A 89 8A 0A 9 / ( 19 P A9 AA 49 4C 8B 8C 8D 8E 8F 90 8B 8C 8D 8E 8F 90 26 0B 32 31 3A 3B AB AC AD AE AF B0 40 3F 4E 4B 3A 3B 91 92 91 91 37 3E B1 B2 37 3E 93 94 95 96-AF 91 91 91 92-AF 63 35 36 0 B3 B4 B5 B6-CF 63 35 36 0 /: 0/} //? ./> up arrow down arrow left arrow right arrow Scrl lock INS DELr Null DOC8-342-TR-080 Confidential Fn layout Key label 0 / INS 1 / END 2 / down arrow 3 / PgDn 4 / left arrow 5 6 / right arrow 7 / home 8 / up arrow 9 / PgUp Num dash N.+ * / . / DEL up arrow down arrow left arrow right arrow Scrl lock INS DELr Null Matrix RAM USAR offset key # (Hex) (Hex) C0 2F C1 23 24 C2 Key label M J K C3 C4 25 L 16 U C5 C6 17 I 18 O C7 C8 08 7 / & 09 8 / * C9 CA 0A 9 / ( 19 P CB CC CD CE CF D0 26 0B 32 31 3C 3D D1 D2 39 END 38 HOME D3 D4 D5 D6-EF 62 64 7E 0 /: 0/} //? ./> PgUp PgDn NumLk PrtScr SysReq Null © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaKey™ keyboard manager USAR − A Semtech Company Programming the keyboard matrix The keyboard matrix is a contiguous section of ACPITroller™ memory divided into four subsections. You program the keyboard matrix by downloading the desired values into the matrix memory. You do this with the four download commands, BA, BB, BC, and BD, which are part of the HIDC USAR expanded command set. Chapter 2, the HID controller interface chapter, explains the role of each command and how to issue it. The first of the four sections of the keyboard matrix is 128 bytes long. It maps the row and column coordinates generated by a keyboard into USAR numbers, described above. The section is organized as follows: Byte Offset Function 0 1 2 3 4 5 6 7 8 . . . 124 125 126 127 USAR number for Row 0, Column 0 USAR number for Row 1, Column 0 USAR number for Row 2, Column 0 USAR number for Row 3, Column 0 USAR number for Row 4, Column 0 USAR number for Row 5, Column 0 USAR number for Row 6, Column 0 USAR number for Row 7, Column 0 USAR number for Row 0, Column 1 . . . USAR number for Row 4, Column 15 USAR number for Row 5, Column 15 USAR number for Row 6, Column 15 USAR number for Row 7, Column 15 USAR numbers 0-7fh correspond to the standard PS/2 key numbers and are used for keys that are unaffected by the Numeric Lock and Function keys. Key numbers 80h to 9fh are reserved for those keys that are influenced by the Numeric Lock and Function keys. Row and column coordinates that are assigned these numbers then generate a second code lookup from one of sections 2, 3, or 4. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 3-13 USAR − A Semtech Company AlphaKey™ keyboard manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product Each of the remaining three sections of the keyboard matrix is 32 bytes long and contains the USAR number generated by a keypress in one of three states: 1. No control keys selected 2. Numeric Lock selected 3. Function selected For example, on the Fujitsu 7654 keyboard, Key J is at Row 7, Column 8 and is a part of the integrated numeric keypad (number 2). When the keyboard is in Numeric Lock, the J key generates the keycode for Keypad 2. So, at offset 47h of matrix section one (which corresponds to Row 7, Column 8), we assign the value 8ah, which is one of the reserved USAR numbers. Matrix section two contains the keycode to be generated when no control keys are pressed, and the offset into this table is calculated by subtracting 128 from the value we put into matrix section one. Therefore, the offset into matrix section two is 10, which is where we put the value 23h, which is the standard keycode generated by the J key. If Numeric Lock was selected, then the offset is used to lookup in matrix section three, which would contain the keycode 41h, which is Numeric 2. If Function was selected, then the offset is used to lookup in matrix section four, which would contain 23h, since the J key is not affected by the Function key. The four sections comprise Page 0 of the matrix RAM. Matrix section one is at offset 0, section two is at offset 80h, section three is at offset A0h, and section four is at offset C0h. 3-14 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaMouse™ pointing devices manager USAR − A Semtech Company USAR UR8HC342 ACPITroller™ Basic AlphaMouse™ Pointing Devices Manager Overview In legacy mode, the UR8HC342 USAR AlphaMouse™ pointing devices manager can simultaneously support up to three standard mice connected to both the external and internal PS/2 ports of the ACPITroller™. The USAR AlphaMouse™ handles PS/2 mouse commands, supports external mouse hot-plug-ins, and merges internal and external mouse data. In multiplexing mode, operating with a multiplexing host driver, UR8HC342 USAR AlphaMouse™ pointing devices manager can simultaneously support up to three pointing devices connected to both the external and internal PS/2 ports of the ACPITroller™. These pointing devices can include proprietary and non-standard devices, depending on the driver(s). The USAR AlphaMouse™ does not merge the data, but keeps data reports from separate pointing devices separate for handling by the multiplexing host driver. Features at a glance • AlphaMouse™ pointing device manager supports hot-plugging and hotswapping of standard two-button and three-button mice without a special driver; it also supports hot-plugging and hot-swapping of MouseWheel mice with a MouseWheel-capable driver • Two external PS/2 ports for external keyboard and mouse with auto-detect and hot-plug support • Simultaneous operation of external and internal pointing devices, merging internal and external mouse data • Support of MouseWheel functionality for both embedded and external pointing devices, even with hot-plug connections, with a MouseWheelcapable driver • Operates safely with PS/2 mouse protocol • AlphaMouse™ performs active PS/2 multiplexing of input from different types of mice simultaneously, with the appropriate driver(s) • Support of the USAR ScreenCoder™ PS/2 absolute and relative touchscreen encoder, with the appropriate driver • Support of the five-button mouse, with an appropriate driver © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 4-1 USAR − A Semtech Company AlphaMouse™ pointing devices manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product Multiplex mode A host driver that supports active PS/2 multiplexing sends a special sequence of commands to the USAR UR8HC342 ACPITroller™ as follows: The host writes 0xD3 to output port 0x64 The host writes 0xF0 to output port 0x60 The controller responds with 0xF0 on input port 0x60 The host writes 0xD3 to output port 0x64 The host writes 0x56 to output port 0x60 The controller responds with 0x56 on input port 0x60 The host writes 0xD3 to output port 0x64 The host writes 0xA4 to output port 0x60 The controller responds with 0x11 on input port 0x60 By responding to last part of the sequence with 0x11 instead of 0xA4, the ACPITroller™ shows that it supports active PS/2 multiplexing standard, version 1.1. At this point, the ACPITroller™ AlphaMouse enters multiplex mode. While in multiplex mode, the ACPITroller™ AlphaMouse behaves as follows: When it receives a data report from a pointing device on a PS/2 port, it adds a prefix to the data report indicating which PS/2 port, and passes the report with the prefix to the multiplexing driver. When it receives a command from the multiplexing driver, it strips the prefix from the command, and sends the command to the PS/2 port indicated by the prefix. 4-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaMouse™ pointing devices manager USAR − A Semtech Company Legacy Mode Functional description and handling of PS/2 ports The USAR AlphaMouse™ pointing devices manager receives its pointing device input through one or more of the USAR ACPITroller™ Basic PS/2 ports. The USAR AlphaMouse™ can handle up to three pointing devices. The PS/2 Ports Driver auto-detects the type of device connected to each PS/2 port. If the device reports itself as a Pointing Device, PS/2 Ports Driver connects it to the USAR AlphaMouse™ pointing devices manager for proper initialization and further data and command handling. The USAR AlphaMouse™ pointing devices manager communicates with the host system through the mouse port of the HID controller. • HID Controller AlphaMouse™ Pointing Devices Manager PS/2 Ports Driver PS/2 Port2 PS/2 Port1 PS/2 Port0 USAR AlphaMouse™ block diagram © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 4-3 USAR − A Semtech Company AlphaMouse™ pointing devices manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product Local handling mode In legacy mode, the USAR AlphaMouse™ supports two distinct modes of pointing devices operation; the “Local handling” and the “System handling” modes. In the “Local handling“ mode, the USAR AlphaMouse™ responds locally to every command issued by the driver, including configuration commands for MouseWheel support. The AlphaMouse™ initializes up to three PS/2 pointing devices and handles all configuration and data transactions individually. If an IntelliMouse® device is hot-plugged in, it is configured by the USAR AlphaMouse™ to enable MouseWheel data reporting. X, Y and Z data reported by all the connected pointing devices is both accumulated and reported to the host driver as if they originated from a single PS/2 device. This default mode of operation supports all known PS/2 pointing devices, providing the least system intervention and the maximum flexibility in the usage of external PS/2 devices with the USAR ACPITroller™ Basic. The following drawing illustrates a possible configuration that can be supported by the USAR AlphaMouse™ pointing devices manager. 4-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaMouse™ pointing devices manager USAR − A Semtech Company HID Controller AlphaMouse™ pointing device manager PS/2 Ports Driver MS IntelliMouse compatible mouse 2 Button TouchPad Embedded 3 button PixiPoint™ force stick pointer USAR AlphaMouse™ sample user model In this example, a pointing device is connected to each of the three AlphaMouse™ PS/2 ports, one internal and two external A USAR PixiPoint™ force-stick type of embedded mouse, emulating a three-button mouse, is connected to the internal PS/2 port. A two-button TouchPad is connected to one of the external PS/2 ports and a Microsoft IntelliMouse to the other. In our example, we assume that the laptop is loaded with Windows 98 and the Microsoft IntelliMouse driver. In this configuration, the USAR ACPITroller™ Basic will operate as described below. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 4-5 USAR − A Semtech Company AlphaMouse™ pointing devices manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product • The PS/2 Ports Driver detects the presence of each pointing device and notifies the pointing device manager of their presence. • The system mouse driver interrogates the ACPITroller™ Basic about its capabilities. The USAR AlphaMouse™ detects the MouseWheel initialization sequence issued by the driver and reports it to the system driver as an IntelliMouse® compatible mouse, thus changing its report scheme from 3 to 4 bytes. • The USAR AlphaMouse™ pointing device manager interrogates each connected pointing device about its capabilities. The AlphaMouse™ initializes the Microsoft IntelliMouse® to report MouseWheel data. • The USAR AlphaMouse™ collects X, Y and Z (where available) data and composes a single report to present to the driver. The PixiPoint™ and the TouchPad report only X and Y coordinates. • Any change in the configuration, such as the hot-plug-in of another pointing device, is handled internally by the USAR AlphaMouse™ and the transaction details are hidden from the driver. 4-6 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product AlphaMouse™ pointing devices manager USAR − A Semtech Company PS/2 Mouse Commands The USAR AlphaMouse™ internally handles all PS/2 mouse commands. These commands, as well as the responses to them, are listed in the following table. USAR AlphaMouse™ PS/2 commands Command FFh FEh F7h – FDh F6h F5h F4h F3h , XXh F2h F1h F0h EFh EEh EDh ECh EBh EAh E9h E8h, 0Xh E7h E6h © 1999-2000 USAR − A Semtech Company Response FAh, AAh, 00h XXh FEh FAh FAh FAh FAh, FAh FAh, 00h Feh FAh FEh FAh FEh FAh FAh, XXh, XXh, XXh, FAh FAh, XXh, XXh, XXh FAh, FAh FAh FAh DOC8-342-TR-080 Confidential Description Mouse reset command Resends last package Invalid Set default Disable Enable Sampling rate Read device ID Invalid command Set remote mode Invalid command Set wrap mode Invalid command Reset wrap mode Read data Set stream mode Status request Set resolution Set scaling 2:1 Reset scaling 1:1 4-7 USAR − A Semtech Company AlphaMouse™ pointing devices manager ACPITroller™ Basic UR8HC342 Preliminary system management controller product External Mouse Hot-Plug Support The USAR AlphaMouse™ pointing devices manager supports the hot-plug in of external mice. The pointing devices manager initializes and configures each connected device dynamically, according to the system mouse driver settings. The USAR AlphaMouse™ pointing devices manager auto-detects three-button mice, as well as MouseWheel type of devices, and enables every feature that the system driver supports. Transparent MouseWheel Support The USAR AlphaMouse™ supports MouseWheel reporting. The USAR AlphaMouse™ pointing device manager generates a special initial sequence to the host in order to alert the driver to utilize the MouseWheel report format. The MouseWheel has a different report packet than a standard PS/2 mouse. As a result, the two cannot be integrated. The USAR AlphaMouse™ pointing device manager monitors the connected mice. If the system mouse driver is initialized to work in MouseWheel mode, the USAR AlphaMouse™ alters its reports to correspond to the MouseWheel format. In this manner, both the internal and external mice data can be integrated. 4-8 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Embedded controller interface USAR − A Semtech Company USAR UR8HC342 ACPITroller™ Embedded Controller Interface UR8HC342 EC bus interface The USAR UR8HC342 ACPI embedded controller (EC) interfaces to the host ISA bus via two I/O addresses. The following diagram illustrates the embedded controller architecture that includes a dedicated ACPI Interface. EC DATA INPUT REGISTER (UR_ADD) ISA Data Read EC DATA OUTPUT REGISTER (UR_ADD) Status Read SMBUS HOST INTERFACE SCI INTERFACE and MAIN FIRMWARE and SMBUS INTERFACE and Internal Simulation SMBus Devices EC STATUS/COMMAND REGISTER (UR_ADD+4) Notes: UR_ADD represents the decoded base address for the UR8HC342 Embedded Controller ISA Ports. Default value is 0x62. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 5-1 Power Button Override Power Button SWI Interrupt LID SCI Interrupt SYSTEM SUSPEND Command Write USAR − A Semtech Company Embedded controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product UR8HC342 embedded controller registers The USAR UR8HC342 SMBus EC contains three registers that occupy two I/O locations. The registers are listed in the following table. USAR UR8HC342 Registers Name EC_SC (R ) EC_SC (W) EC_DATA Description Status Command Data I/O function IOR IOW IOR/IOW I/O Port Address UR_ADD+4 UR_ADD+4 UR_ADD EC Status Register, EC_SC (R) EC_SC (R) is a read-only register that indicates the current status of the Embedded Controller interface. It contains the following fields. EC_SC (R) EC status register bit definitions Bit7 IGN Bit6 SMI_EVT Bit5 SCI_EVT Bit4 BURST Bit3 CMD Bit2 IGN Bit1 IBF Bit0 OBF EC_SC (R) EC status register bit definitions IGN SMI_EVT SCI_EVT BURST CMD IBF OBF 5-2 Ignored SMI Event 1 – Indicates SMI event is pending (requesting SMI query) 0 – Indicates no SMI event pending SCI Event 1 – Indicates SCI event is pending (requesting SCI query) 0 – Indicates no SCI events are pending Burst Mode 1 – Controller is in burst mode for polled command processing 0 – Controller is in normal mode for interrupt-driven command processing Command/Data 1 – Byte in data register is a command byte (only set by host, used by EC) 0 – Byte in data register is a data byte (only clear by host, used by EC) Input Buffer Full 1 – Input buffer is full (data ready for EC) 0 – Input buffer is empty, generate SCI interrupt Output Buffer Full 1 – Output buffer is full (data ready for host), generate SCI interrupt 0 – Output buffer is empty DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Embedded controller interface USAR − A Semtech Company Command Register, EC_SC (W) EC_SC (W) is a write-only register that allows commands to be issued to the embedded controller. Writes to this register are latched in the input data register and the input buffer full (IBF) flag is set in the status register. Writes to this location also cause the command bit to be set in the status register. This enables the embedded controller to differentiate the start of a command sequence from a data byte write operation. Data Register, EC_DATA(R/W) EC_DATA(R/W) is a read/write register that allows both command/data bytes to be issued to the embedded controller and the OS to read data returned by the embedded controller. Writes to this port by the host are latched into the input data register and the input buffer full (IBF) flag is set in the status register. Reads from this register return data from the output data register and clear the output buffer full (OBF) flag in the status register. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 5-3 USAR − A Semtech Company Embedded controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product Port Operation The following diagrams illustrate the sequence for issuing commands and data to the EC through the host interface. Send Command Byte The Host can issue a command byte to command register directly. IBF = 0 ? Yes Write command byte to command port UR_ADD+4; No End 5-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company Embedded controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Send Data Byte The Host can send a data byte to the data port directly. IBF = 0 ? Yes No Write data byte to data port UR_ADD; End © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 5-5 USAR − A Semtech Company Embedded controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product EC Commands The Operating System can communicate with the EC using the standard ACPI embedded controller command set. These commands are listed and detailed below. USAR UR8HC342 ACPI controller command set Embedded Controller Command Read Embedded Controller (RD_EC) Write Embedded Controller (WR_EC) Burst Enable Embedded Controller (BE_EC) Burst Disable Embedded Controller (BD_EC) Query Embedded Controller (QR_EC) Command Byte Encoding 0x80 0x81 0x82 0x83 0x84 Read Embedded Controller, RD_EC (0x80) The RD_EC (0x80) command allows the OS to read a byte in the address space of the embedded controller. The exact command sequence is detailed below. This command is reserved exclusively for use by the OS and proceeds based on interrupts from the EC. The values of the IBF and OBF flags determine the interrupt generation as follows. RD_EC (0x80) command sequence Step 1 2 3 5-6 Action Send command header Send address to be read Host read data Register Command port Data Port Address UR_ADD+4 Data UR_ADD UR_ADD DOC8-342-TR-080 Confidential SCI Interrupt Interrupt on IBF=0, command header has been read No interrupt Interrupt on OBF=1, data is available © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Embedded controller interface USAR − A Semtech Company Write Embedded Controller, WR_EC (0x81) The WR_EC (0x81) command byte allows the OS to write a byte in the address space of the embedded controller. This command byte is reserved exclusively for use by the OS and proceeds based on interrupts from the EC. The value of the IBF flag determines the interrupt generation as follows. WR_EC (0x81) command sequence Step 1 2 3 Action Send command header Send address to be written Host write data Register Command port Data Port Address UR_ADD+4 Data UR_ADD UR_ADD SCI Interrupt Interrupt on IBF=0, command header has been read Interrupt on IBF=0, address has been read Interrupt on IBF=0, data has been read Burst Enable Embedded Controller, BE_EC (0x82) The BE_EC (0x82) command allows the OS to request dedicated attention from the EC and, except for critical events, the EC from doing tasks other than receiving command and data from the OS. This command is an optimization that allows the host processor to issue several commands back-to-back, in order to reduce latency at the embedded controller interface. When the controller is in the burst mode, it should transition to the burst Disable State if the host does not issue a command within the following guidelines: • First Access • Subsequent Accesses • Total Burst Time 400 microseconds 50 microseconds each 1 millisecond If the EC disables burst mode for any reason other than the burst disable command, it generates an SCI to the OS to indicate the change. While in burst mode, the embedded controller follows these guidelines for the OS driver: • SCIs are generated as normal, including IBF=0 and OBF=1. • Accesses should be responded to within 50 microseconds. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 5-7 USAR − A Semtech Company Embedded controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product Following is the burst enable command sequence. BE_EC (0x82) command sequence Step 1 2 Action Send command header Host read burst ACK byte Register Command port Data Port Address UR_ADD+4 SCI Interrupt No interrupt UR_ADD Interrupt on OBF=1, data is available Burst Disable Embedded Controller, BD_EC (0x83) This command releases the embedded controller from a previous Burst Enable command and allows it to resume normal processing. The OS sends this command after it has completed its entire queued command sequence to the embedded controller. Following is the burst disable command sequences. BD_EC (0x83) command sequence Step 1 Action Send command header Register Command port Port Address UR_ADD+4 SCI Interrupt Interrupt on IBF=0, command header has been read Query Embedded Controller, QR_EC (0x84) The OS driver sends the QR_EC (0x84) command when the SCI_EVT flag in the EC_SC register is set. When the EC has detected a system event that must be communicated to the OS, it first sets the SCI_EVT flag in the EC_SC register, generates an SCI, and then waits for the OS to send the query (QR_EC) command. The OS detects the embedded controller SCI, sees the SCI_EVT flag set, and sends the query command to the embedded controller. Upon receipt of the QR_EC command byte, the EC places a notification byte with a value between 0-255, indicating the cause of the notification. The notification byte indicates which interrupt handler operation the OS should execute in order to process the embedded controller SCI. The query value of zero is reserved for a spurious query result and indicates “no outstanding event.” 5-8 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Embedded controller interface Following is the query EC command sequences. QR_EC (0x84) command sequence Step 1 2 Action Send command header Host read query value Register Command port Data Port Address UR_ADD+4 SCI Interrupt No interrupt UR_ADD Interrupt on OBF=1, data is available SMBus Host Controller Notification Header (Optional), OS_SMB_EVT The OS_SMB_EVT query command notification header is the special return code that indicates events from an SMBus controller implemented within an embedded controller. These events include the following. OS_SMB_EVT events Num 1 2 3 4 Notification 00h 01h 02h 03h Event No outstanding event Command complete Command error Alarm Description Response to OS SMBus command Response to OS SMBus command Alarm from SMBus device The actual notification value is declared in the SMBus host controller device object in the ACPI name space. For more details on the SMBus Host functioning in the ACPI system, refer to the SMBus Host Controller Interface section of this Specification. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 5-9 USAR − A Semtech Company Embedded controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 5-10 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company USAR − A Semtech Company SCI & SWI interrupt generation ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR UR8HC342 ACPITroller™ SCI & SWI Interrupt Generation Event interrupts The USAR UR8HC342 ACPITroller™ generates two types of interrupts, the SCI and the SWI. The type of interrupt generated depends on the type of event that caused it. When a standard SMBus event occurs, the EC generates an SCI interrupt. For any other General Purpose Events (GPE), an SWI interrupt occurs. Such events may include lid events, dock events, or power button presses. SWI interrupts have the ability to wake up the system if it is in suspend. SCI interrupts do not do this. Below is a diagram describing the generation of these two interrupts. ECSCIEN.x X Standard SMBUS Event SCI interrupt Event Status X GPE SWI interrupt ECSWIEN.x X Generation of SCI and SWI event interrupts © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 6-1 USAR − A Semtech Company SCI & SWI interrupt generation ACPITroller™ Basic UR8HC342 Preliminary system management controller product SWI sources There are a number of events that trigger an SWI interrupt: up to eight external events can trigger a SWI interrupt; in addition, the USAR UR8HC342 internally generates an SWI in response to certain SMBus conditions. Eight pins, labeled GPE0 – GPE7, can be connected to event sources to generate SWI interrupts. Each of these pins has specific traits, making some more suitable than others for certain functions. Pins GPE0 and GPE1 are able to generate GP events on detection of positive- or negative-edge signals. This makes them most suitable for handling occasional events like docking insertion/removal, and lid open/close, where processing is required only when a change in input is detected. GPE2 to GPE7 trigger on logical low signal level, rather than signal edge. This makes them more suitable for functions like Power Button Override, which requires the Power Button to be held down for four seconds. GPE4 and GPE7 have no internal pullup resistors and require external pullup to be used. GPE3-6 can enable internal pullup only when SMBus2 is disabled. In order to use these pins as GPE input pins, the user must enable them as GPE pins in the GPECFG register. If these pins are not used as GPE pins, they are available as General I/O pins. In addition to these externally generated GPE events, the USAR UR8HC342 generates a SWI interrupt in response to certain SMBus conditions. The EC monitors the SMBus status. If the SMBus becomes stuck, the EC can 2 generate a SWI to the system to report this. If a generic I C device (not identified as a smart battery, charger, or selector) generates an alert, the EC can generate an SWI interrupt. In addition, under certain conditions, battery alarms and selector and charger alerts can generate SWI interrupts, as described below. 6-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SCI & SWI interrupt generation USAR − A Semtech Company Special SMBus events One of the differences between SCI and SWI events is that an SWI interrupt can wake up a host in suspend mode, while an SCI interrupt cannot. As described previously, standard SMBus events generate SCI interrupts. An SCI interrupt does not wake up the system if it is in suspend mode. Some SMBus events, however, may occur when the system is in suspend, and need to wake up the system. These events are battery alarm and selector and charger alert. For these events, if the system is in suspend, the UR8HC342 first simulates a power button press. This power button press generates an SWI interrupt, which wakes up the system. Once the system is active again, the regular SCI interrupt can be generated to indicate the SMBus event. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 6-3 USAR − A Semtech Company SCI & SWI interrupt generation ACPITroller™ Basic UR8HC342 Preliminary system management controller product Interrupt Generation The EC Interrupt Model uses pulsed interrupts to speed the clearing process. The SCI interrupts are firmware-generated, using EC generalpurpose outputs, and have the waveform shown in the figure below. Figure 13-3. The OS treats these interrupts as edge events. Interrupt detected 10us Interrupt serviced and cleared EC interrupt process waveform 6-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus host controller interface USAR − A Semtech Company USAR UR8HC342 ACPITroller™ SMBus Host Controller Interface Overview This chapter describes the System Management Bus (SMBus) host controller interface. The SMBus address space is a generic address space defined in the ACPI specification. Following is a description of the USAR UR8HC342 ACPITroller™ implementation of the SMBus Host Controller within the Embedded Controller. This implementation allows the OS directly to address devices on the SMBus. SMBus overview The SMBus is a two-wire interface based on I²C protocol. A low-speed bus, it provides multi-device addressing as well as bus arbitration. For more information on the SMBus generally, refer to the complete set of SMBus Specifications published by the Smart Battery System Implementers Forum (SBS-IF) at http://www.sbs-forum.org/. The SMBus host controller interface The SMBus Host Controller interface allows the host processor, under control of the OS, to manage devices on the SMBus. Among typical devices that reside on the SMBus are smart batteries, smart chargers, contrast/backlight control, and temperature sensors. Due to the sensitive nature of some of these devices, the SMBus Host Controller is required to monitor and filter certain SMBus commands addressed to the Smart Battery System. This particular function of the EC is essential for the system’s safety, since it prevents errant applications or viruses from creating system hazards through improper control of the battery subsystem. The SMBus Host Controller interface provides a method of communicating with SMBus devices through a block of registers that reside in the Embedded Controller space. In addition, the SMBus Host Controller handles certain SMBus functions related to alerts and error conditions. The USAR UR8HC342 ACPITroller™ supports the standard set of registers defined in the ACPI specification that an ACPI-compatible OS can use to communicate with SMBus devices. The following sections detail the SMBus Host Controller functionality, the Register Interface, and configuration parameters. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 7-1 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus alarm message & SMBus alert process In an SMBus system, several devices can be programmed to notify the host system when specific events occur. A Smart Battery, for example, issues an alarm message to signal a critical capacity condition. Other SMBus devices, including Smart Selectors and Smart Chargers, issue alerts to inform the SMBus Host Controller of an internal status change. SMBus devices typically notify the SMBus Host Controller that such an event has occurred by asserting the SMBus alert signal. When the USAR UR8HC342 ACPITroller™ SMBus Host Controller detects that the SMBus alert signal has been asserted, it first checks the CHGQREN and SLCTQREN bits in R0 (EC configuration register 0) in order to determine whether to query for a Smart Charger- or a Smart Selectorgenerated alert. If either one of these bits is set, the SMBus Host Controller queries the appropriate device and checks its status. The status is then ANDed with the appropriate masks and, if the result is nonzero, the appropriate device status message is placed into the EC SMBus Alarm buffer and an SCI is generated. The address used to query the selector and charger depends on the system configuration. If the system includes a selector and a charger at different addresses, the queries are made to the addresses specified. If the system includes a selector and charger device residing at the same address, the query is to that specific address. This configuration controlled by the CHGSLCT bit in R0. If the alert did not come from one of these two devices, the alert is 2 considered to come from a generic I C device. The alert can generate an SWI interrupt, not an SCI interrupt. The SMBus host generates an SWI interrupt if the DEVICEEN flag in EC_SWIEN is set. If querying for the selector is disabled (SLCTQREN is clear), alerts from the 2 selector are treated the same as for any other I C devices. Similarly, if querying for the charger is disabled (CHGQREN is clear), alerts from the 2 charger are treated in the same manner as any other I C device. In addition to SMBus devices generating alerts, the Smart Battery can generate an alarm to indicate a critical condition. When the USAR UR8HC342 ACPITroller™ receives a Smart Battery alarm, it retrieves the alarm message and ANDs it with the contents of R14 (the EC battery alarm mask register). If the result is nonzero, the EC puts an alarm message into the EC SMBus Alarm buffer and generates an SCI interrupt to the system. Note that once an alarm message has been received, the SMBus host controller does not receive additional alarm messages until the ALRM status bit is cleared. 7-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus host controller interface USAR − A Semtech Company SMBus error recovery The USAR UR8HC342 ACPITroller™ monitors the SMBus. If it detects that the SMBus has gotten stuck, the EC tries to recover the bus. If it fails and the SMBus Stuck event is enabled (by setting STUCKEN in register R05), the EC issues an SWI interrupt to the system. SMBus host register space The SMBus host interface is a flat array of registers that are arranged in a block of system address space. The SMBus Register Space base address (SMB_BASE) corresponds to zero (0) in the USAR UR8HC342’s address space. SMBus host registers The table below lists the registers defined for the SMBus Host with their reset values. Each register is eight bits wide. The first group of registers contains the standard SMBus Host registers, as listed in the ACPI Specification section on Embedded Controllers. A list of these registers follows. An appendix to this document provides brief descriptions of these registers. Full descriptions are given in the ACPI specification. The method of initiating the different protocols on the SMBus through these registers is also briefly described in the appendix, and fully provided in the ACPI specification. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 7-3 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product Standard SMBus host registers 7-4 Location Register Name SMB_BASE+0 SMB_BASE+1 SMB_BASE+2 SMB_BASE+3 SMB_BASE+4 SMB_BASE+5 SMB_BASE+6 SMB_BASE+7 SMB_BASE+8 SMB_BASE+9 SMB_BASE+10 SMB_BASE+11 SMB_BASE+12 SMB_BASE+13 SMB_BASE+14 SMB_BASE+15 SMB_BASE+16 SMB_BASE+17 SMB_BASE+18 SMB_BASE+19 SMB_BASE+20 SMB_BASE+21 SMB_BASE+22 SMB_BASE+23 SMB_BASE+24 SMB_BASE+25 SMB_BASE+26 SMB_BASE+27 SMB_BASE+28 SMB_BASE+29 SMB_BASE+30 SMB_BASE+31 SMB_BASE+32 SMB_BASE+33 SMB_BASE+34 SMB_BASE+35 SMB_BASE+36 SMB_BASE+37 SMB_BASE+38 SMB_BASE+39 SMB_PRTCL SMB_STS SMB_ADDR SMB_CMD SMB_DATA[0] SMB_DATA[1] SMB_DATA[2] SMB_DATA[3] SMB_DATA[4] SMB_DATA[5] SMB_DATA[6] SMB_DATA[7] SMB_DATA[8] SMB_DATA[9] SMB_DATA[10] SMB_DATA[11] SMB_DATA[12] SMB_DATA[13] SMB_DATA[14] SMB_DATA[15] SMB_DATA[16] SMB_DATA[17] SMB_DATA[18] SMB_DATA[19] SMB_DATA[20] SMB_DATA[21] SMB_DATA[22] SMB_DATA[23] SMB_DATA[24] SMB_DATA[25] SMB_DATA[26] SMB_DATA[27] SMB_DATA[28] SMB_DATA[29] SMB_DATA[30] SMB_DATA[31] SMB_BCNT SMB_ALRM_ADDR SMB_ALRM_DATA[0] SMB_ALRM_DATA[1] Reset Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 DOC8-342-TR-080 Confidential Description Protocol register Status register Address register Command register Data register zero Data register one Data register two Data register three Data register four Data register five Data register six Data register seven Data register eight Data register nine Data register ten Data register eleven Data register twelve Data register thirteen Data register fourteen Data register fifteen Data register sixteen Data register seventeen Data register eighteen Data register nineteen Data register twenty Data register twenty-one Data register twenty-two Data register twenty-three Data register twenty-four Data register twenty-five Data register twenty-six Data register twenty-seven Data register twenty-eight Data register twenty-nine Data register thirty Data register thirty-one Block Count Register Alarm address Alarm data register zero Alarm data register one © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus host controller interface USAR − A Semtech Company The second group of registers contains registers that are USAR-defined SMBus Host registers. These allow the user to access and configure all of the added features available on the UR8HC342, such as SBS device events and interrupt generation. USAR-defined SMBus host registers EC offset 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Register no. R00 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20-R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 © 1999-2000 USAR − A Semtech Company Register name EC configuration register 0 EC configuration register 1 EC configuration register 2 EC configuration register 3 EC SWI GPE enable register 0 EC SWI GPE enable register 1 EC SWI GPE status register 0 EC SWI GPE status register 1 EC selector alarm high mask register 0 EC selector alarm high mask register 1 EC selector alarm low mask register 0 EC selector alarm low mask register 1 EC charger alarm high mask register EC charger alarm low mask register EC battery alarm mask register 8042 configuration register 0 8042 configuration register 1 8042 configuration register 2 reserved GIO0 data/direction register reserved GIO1 mode register GIO1 data/direction register GIO1 PWM1 high byte register GIO1 PWM1 low byte register GIO1 PWM0 high byte register GIO1 PWM0 low byte register GIO1 DA1 data register GIO1 DA0 data register GIO2 data/direction register GIO2 AD2 data high byte register GIO2 AD2 data low byte register GIO2 AD1 data high byte register GIO2 AD1 data low byte register GIO2 AD0 data high byte register GIO2 AD0 data low byte register GIO3 direction register GIO3 data register DOC8-342-TR-080 Confidential Read / Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R Power-up / reset default value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 7-5 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product R00: EC configuration register 0 This register contains the control bytes that determine the EC and SMBus work modes. R00: EC configuration register 0 bit definitions bit7 RES bit 6 RES bit 5 RES bit 4 RES bit 3 RES bit 2 CHGQREN bit 1 SLCTQREN bit 0 CHGSLCT R00: EC configuration register 0 bit descriptions RES CHGQREN SLCTQRE CHGSLCT 7-6 Reserved Charger Alert Query Enable This setting controls whether the SMBus host queries the charger upon receiving an alert. 1– enable 0 – disabled Selector Alert Query Enable This setting controls whether the SMBus host queries the selector upon receiving an alert 1 – enable 0 – disabled Selector and Charger Combined device This selects what configuration is used. In some systems, the charger and the selector are different devices at different addresses, while in some systems, the selector and charger are combined into one device at one address 1 – separate address 0 – combined device at same address DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company R01: EC configuration register 1 bit definitions bit7 KKLEDEN bit 6 CLLEDEN bit 5 NLLEDEN bit 4 SLLEDEN bit 3 RES bit 2 RES bit 1 RES R01: EC configuration register 1 bit descriptions RES SLLEDEN NLLEDEN CLLEDEN KKLEDEN © 1999-2000 USAR − A Semtech Company Reserved Enable GIO03 as scroll lock LED 1– enable as scroll lock LED 0 – general purpose I/O Enable GIO02 as numeric lock LED 1– enable as numeric lock LED 0 – general purpose I/O Enable GIO01 as caps lock LED 1– enable as caps lock LED 0 – general purpose I/O Enable GIO00 as Katakana LED 1– enable as Katakana LED 0 – general purpose I/O DOC8-342-TR-080 Confidential 7-7 bit 0 RES USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product R02: EC configuration register This register controls which of the available general purpose event (GPE) pins are selected to function as GPE inputs and which remain generalpurpose I/O (GP I/O) pins. Setting a bit in the register to 1 configures the corresponding pin for GPE input, and resetting it to 0 configures it to be used for GP I/O. Note that a separate register, R04, determines whether a given GPE pin is enabled R02: EC configuration register 2 bit definitions bit7 GPE7AS bit 6 GPE6AS bit 5 GPE5AS bit 4 GPE4AS bit 3 GPE3AS bit 2 GPE2AS bit 1 GPE1AS bit 0 GPE0AS R02: EC configuration register 2 bit descriptions GPE7AS GPE6AS GPE5AS GPE4AS GPE3AS GPE2AS GPE1AS GPE0AS 7-8 Assign pin GPE7 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE6 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE5 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE4 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE3 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE2 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE1 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other Assign pin GPE0 to an SWI general purpose event (GPE) 1– assign pin to an SWI general purpose event (GPE) 0 – assign pin to general purpose I/O (GPIO) or other DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus host controller interface USAR − A Semtech Company R03: EC configuration register 3 bit definitions bit7 bit 6 bit 5 GPE7EDGE GPE6EDGE RES bit 4 RES bit 3 RES bit 2 PWBOVER bit 1 RES bit 0 RES R03: EC configuration register 3 bit descriptions RES GPE7EDGE GPE6EDGE PWBOVER RESERVED Make general purpose event GPE7 rising edge sensitive 1– Make general purpose event GPE7 rising edge sensitive Make general purpose event GPE6 rising edge sensitive 1– Make general purpose event GPE6 rising edge sensitive Enable power button override 1– enable power button override R04: EC SWI GPE enable register 0 bit definitions bit7 GPE7EN bit 6 GPE6EN bit 5 GPE5EN bit 4 GPE4EN bit 3 GPE3EN bit 2 GPE2EN bit 1 GPE1EN R04: EC SWI GPE enable register 0 bit descriptions GPE7EN GPE6EN GPE5EN GPE4EN GPE3EN GPE2EN GPE1EN GPE0EN © 1999-2000 USAR − A Semtech Company Enable SWI general purpose event GPE7 1– Enable SWI general purpose event GPE7 Enable SWI general purpose event GPE6 1– Enable SWI general purpose event GPE6 Enable SWI general purpose event GPE5 1– Enable SWI general purpose event GPE5 Enable SWI general purpose event GPE4 1– Enable SWI general purpose event GPE4 Enable SWI general purpose event GPE3 1– Enable SWI general purpose event GPE3 Enable SWI general purpose event GPE2 1– Enable SWI general purpose event GPE2 Enable SWI general purpose event GPE1 1– Enable SWI general purpose event GPE1 Enable SWI general purpose event GPE0 1– Enable SWI general purpose event GPE0 DOC8-342-TR-080 Confidential 7-9 bit 0 GPE0EN USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product R05: EC SWI GPE enable register 1 bit definitions bit7 bit 6 RES MOUSEN bit 5 KYBDEN bit 4 bit 3 STUCKEN ALRTEN bit 2 SLCTEN bit 1 CHRGEN bit 0 BATTEN R05: EC SWI GPE enable register 1 bit descriptions RES MOUSEN KYBDEN STUCKEN ALRTEN SLCTEN CHRGEN BATTEN 7-10 RESERVED Enable mouse wakeup SWI general purpose event (GPE) 1– Enable mouse wakeup SWI general purpose event (GPE) Enable keyboard wakeup SWI general purpose event (GPE) 1– Enable keyboard wakeup SWI general purpose event (GPE) Enable SMBus stuck error SWI general purpose event (GPE) 1– Enable SMBus stuck error SWI general purpose event (GPE) Enable SMBus alert SWI general purpose event (GPE) 1– Enable SMBus alert SWI general purpose event (GPE) Enable selector alarm SWI general purpose event (GPE) 1– Enable selector alarm SWI general purpose event (GPE) Enable charger alarm SWI general purpose event (GPE) 1– Enable charger alarm SWI general purpose event (GPE) Enable battery alarm SWI general purpose event (GPE) 1– Enable battery alarm SWI general purpose event (GPE) DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company SMBus host controller interface R06 and R07: EC SWI GPE status registers These registers contain the EC SWI interrupt events status bits, which correspond to the events controlled by the EC SWI GPE enable registers (R04 and R05). For each bit controlling an SWI event in an enable register, the same position bit in the corresponding status register indicates the status of that event. Each status bit is set by the SWI event and can be cleared only by the host writing 1 to its bit position. The status bits are set and reset regardless of whether each event is enabled. Enabling an event controls only whether an interrupt is generated on the event. R06: EC SWI GPE status register 0 bit definitions bit7 GPE7ST bit 6 bit 5 GPE6STN GPE5ST bit 4 GPE4ST bit 3 GPE3ST bit 2 GPE2ST bit 1 GPE1ST bit 0 GPE0ST R06: EC SWI GPE status register 0 bit descriptions GPE7ST GPE6ST GPE5ST GPE4ST GPE3ST GPE2ST GPE1ST GPE0ST © 1999-2000 USAR − A Semtech Company Flag SWI general purpose event GPE7 1– Flag SWI general purpose event GPE7 Flag SWI general purpose event GPE6 1– Flag SWI general purpose event GPE6 Flag SWI general purpose event GPE5 1– Flag SWI general purpose event GPE5 Flag SWI general purpose event GPE4 1– Flag SWI general purpose event GPE4 Flag SWI general purpose event GPE3 1– Flag SWI general purpose event GPE3 Flag SWI general purpose event GPE2 1– Flag SWI general purpose event GPE2 Flag SWI general purpose event GPE2 1– Flag SWI general purpose event GPE2 Flag SWI general purpose event GPE1 1– Flag SWI general purpose event GPE1 DOC8-342-TR-080 Confidential 7-11 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product R07: EC SWI GPE status register 1 bit definitions bit7 bit 6 RES MOUSST bit 5 KYBDST bit 4 STUCKST bit 3 ALRTST bit 2 SLCTST bit 1 CHRGST bit 0 BATTST R07: EC SWI GPE status register 1 bit descriptions RES MOUSST KYBDST STUCKST ALRTST SLCTST CHRGST BATTST 7-12 RESERVED Flag mouse wakeup SWI general purpose event (GPE) 1– Flag mouse wakeup SWI general purpose event (GPE) Flag keyboard wakeup SWI general purpose event (GPE) 1– Flag keyboard wakeup SWI general purpose event (GPE) Flag SMBus stuck error SWI general purpose event (GPE) 1– Flag SMBus stuck error SWI general purpose event (GPE) Flag SMBus alert SWI general purpose event (GPE) 1– Flag SMBus alert SWI general purpose event (GPE) Flag selector alarm SWI general purpose event (GPE) 1– Flag selector alarm SWI general purpose event (GPE) Flag charger alarm SWI general purpose event (GPE) 1– Flag charger alarm SWI general purpose event (GPE) Flag battery alarm SWI general purpose event (GPE) 1– Flag battery alarm SWI general purpose event (GPE) DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus host controller interface USAR − A Semtech Company R08-R11: EC selector alarm mask registers • R08: EC selector alarm high mask register 0 • R09: EC selector alarm high mask register 1 • R10: EC selector alarm low mask register 0 • R11: EC selector alarm low mask register 1 These registers contain the Smart Selector alert message mask. This controls whether an alert from the Smart Selector generates an SCI interrupt. When the Smart Selector sends an SMBus alert, if the Selector is enabled the SMBus host queries the Selector state. Each bit of the state is masked with the corresponding selector alarm mask flag, and if the result is nonzero, an SCI interrupt is generated. The high mask registers (R08 and R09) control whether a high level for a given bit of the selector state generates an interrupt, while the low mask registers (R10 and R11) control whether a low level for a given bit of the selector state generates an interrupt. By using both of these register pairs, the user can generate an interrupt on either low or high level – or both – for each of the selector state bits. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 7-13 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product R08 / R10 EC selector alarm high / low mask register 0 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 BATDCHG BATCCHG BATBCHG BATACHG BATDPRES BATCPRES BATBPRES BATAPRES bit 2 bit 1 bit 0 R08 / R10 EC selector alarm high / low mask register 0 bit descriptions BATDCHG BATCCHG BATBCHG BATACHG BATDPRES BATCPRES BATBPRES BATAPRES Mask for Battery D connected to charger state Mask for Battery C connected to charger state Mask for Battery B connected to charger state Mask for Battery A connected to charger state Mask for Battery D present state Mask for Battery C present state Mask for Battery B present state Mask for Battery A present state R09/ R11 EC selector alarm high / low mask register 1 bit definitions bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BATDSMB BATCSMB BATBSMB BATASMB BATDPWR BATCPWR BATBPWR BATAPWR R09/ R11 EC selector alarm high / low mask register 1 bit descriptions BATDSMB BATCSMB BATBSMB BATASMB BATDPWR BATCPWR BATBPWR BATAPWR 7-14 Mask for Battery D connected to SMBus state Mask for Battery C connected to SMBus state Mask for Battery B connected to SMBus state Mask for Battery A connected to SMBus state Mask for Battery D powering state Mask for Battery C powering state Mask for Battery B powering state Mask for Battery A powering state DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company SMBus host controller interface R12 and R13: EC charger alarm mask registers • R12: EC charger alarm high mask register • R13: EC charger alarm low mask register These registers contain the Smart Charger alert message masks, which use the same mechanism as the Smart Selector alarm message masks. When the Smart Charger sends an SMBus alert, if the Charger is enabled the SMBus host queries the Charger status. Each bit of its status is masked with the corresponding flag in these registers, and if the result is nonzero, an SCI interrupt is generated. R12 controls whether a high level for a given bit of the charger status generates an interrupt, while R13 controls whether a low level for a given bit of the charger status generates an interrupt. By using both of these register sets, the user can generate an interrupt on either low-or high-level – or both – for each of the charger status bits. The register contains the following fields. R12 / R13 EC charger alarm high / low mask register bit definitions bit7 bit 6 AC_PRES BAT_PRES PWRFAIL bit 5 bit 4 bit 3 bit 2 bit 1 ALRMINH THRM_UR THRM_HOT THRM_COLD THRM_OR bit 0 R12 / R13 EC charger alarm high / low mask register bit descriptions AC_PRES BAT_PRES PWRFAIL ALRMINH THRM_UR THRM_HOT THRM_COLD THRM_OR © 1999-2000 USAR − A Semtech Company Mask for AC Present bit Mask for Battery Present bit Mask for Power fail bit Mask for Alarm inhibited bit Mask for Thermistor Hot bit Mask for Battery C powering state Mask for Thermistor Cold bit Mask for Thermistor Over-range bit DOC8-342-TR-080 Confidential 7-15 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product R14: EC battery alarm mask register This register contains the Smart Battery alarm message mask. When the SMBus host receives a battery alarm, it ANDs the alarm message with the contents of R14, and if the result is not zero, the EC asserts SCI to the system. This register contains the following fields. R14: EC battery alarm mask register bit definitions bit7 OVERCHARG bit 6 TERMCHARG bit 5 RES bit 4 TEMPCHARG bit 3 TERMDISCHARG bit 2 RES bit 1 REMAINCAP bit 0 REMAINTIME R14: EC battery alarm mask register bit descriptions RES OVERCHARG TERMCHARG TEMPCHARG TERMDISCHARG REMAINCAP REMAINTIME 7-16 Reserved Battery over charged alarm mask Battery terminate charge alarm mask Battery over temperature alarm mask Battery terminate discharge alarm mask Battery remaining capacity alarm mask Battery remaining time alarm mask DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product SMBus host controller interface USAR − A Semtech Company SMBus Device Access Restrictions The USAR UR8HC342 ACPITroller™ does not allow access to elements of some specific SMBus devices. These commands should be accomplished among the various SMBus devices and should not be executed through the system. Allowing these commands to be processed through the host could cause damage to some SBS elements and, as such, must be restricted. Often the OS or its drivers must filter these commands. A distinct advantage to the USAR UR8HC342 is its ability to internally shield the SBS devices from these dangerous commands, freeing the OS and drivers from this consideration. The following commands are inhibited: • Write charge current command (0x14) to smart battery charger (address 0001001). • Write charge voltage command (0x15) to smart battery charger (address 0001001). These commands are disabled because they involve data which can only be accurately calculated and reported only by the smart battery itself. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 7-17 USAR − A Semtech Company SMBus host controller interface ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 7-18 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic R8HC342 Preliminary system management controller product Internal virtual SMBus devices USAR − A Semtech Company USAR ACPITroller™ general input / output options USAR ACPITroller™ internal virtual SMBus device A unique feature of the USAR ACPITroller™ is its incorporation of an internal virtual SMBus device. The host can address this device through the ACPI EC interface the same way it would address any external device residing on an SMBus port. Using SMBus commands, the host can read from and write to the register space of the ACPITroller™ The internal virtual SMBus device has the seven-bit binary SMBus address 0100110. It supports the following SMBus protocols: USAR ACPITroller™ internal virtual SMBus device supported protocols Protocol Send byte Receive byte Write byte Write word Write block Read byte Read word Read block Action Set register page (byte = page number: 0 or 1) Read register page (byte = page number: 0 or 1) Write to register space (command code = data offset, data = data to write) Read from register space (command code = data offset, data = data read) Page 1 of the ACPITroller™ register space contains the programmable keyboard matrix. Page 0 of the ACPITroller™ register space contains the registers in the following table. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 8-1 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Internal virtual SMBus devices ACPITroller™ registers page 0 8-2 8042 offset 00 01 02 03 04 05 06 07 08 Register no. R00 R01 R02 R03 R04 R05 R06 R07 R08 09 R09 10 R10 11 R11 12 R12 13 R13 14 15 16 17 18 19 20 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 R14 R15 R16 R17 R18 R19 R20-R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 Register name EC configuration register 0 EC configuration register 1 EC configuration register 2 EC configuration register 3 EC SWI GPE enable register 0 EC SWI GPE enable register 1 EC SWI GPE status register 0 EC SWI GPE status register 1 EC selector alarm high mask register 0 EC selector alarm high mask register 1 EC selector alarm low mask register 0 EC selector alarm low mask register 1 EC charger alarm high mask register EC charger alarm low mask register EC battery alarm mask register 8042 configuration register 0 8042 configuration register 1 8042 configuration register 2 reserved GIO0 data/direction register reserved GIO1 mode register GIO1 data/direction register GIO1 PWM1 high byte register GIO1 PWM1 low byte register GIO1 PWM0 high byte register GIO1 PWM0 low byte register GIO1 DA1 data register GIO1 DA0 data register GIO2 data/direction register GIO2 AD2 data high byte register GIO2 AD2 data low byte register GIO2 AD1 data high byte register GIO2 AD1 data low byte register GIO2 AD0 data high byte register GIO2 AD0 data low byte register GIO3 direction register GIO3 data register DOC8-342-TR-080 Confidential Read / Write R/W R/W R/W R/W R/W R/W R/W R/W R/W Power-up / reset default value 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W R R R 00h 00h 00h 00h R/W 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h © 1999-2000 USAR − A Semtech Company USAR − A Semtech Company Internal virtual SMBus devices ACPITroller™ Basic R8HC342 Preliminary system management controller product GIO0: LED drivers GIO0 is a 4-bit general-purpose input/output port mapped on the same pins used for the keyboard LEDs. The functions of the pins are determined by register R01, the EC configuration register 1. R01: EC configuration register 1 bit definitions bit7 KKLEDEN bit 6 CLLEDEN bit 5 NLLEDEN bit 4 SLLEDEN bit 3 RES bit 2 RES bit 1 RES R01: EC configuration register 1 bit descriptions RES SLLEDEN NLLEDEN CLLEDEN KKLEDEN © 1999-2000 USAR − A Semtech Company Reserved Enable GIO03 as scroll lock LED 1– enable as scroll lock LED 0 – general purpose I/O Enable GIO02 as numeric lock LED 1– enable as numeric lock LED 0 – general purpose I/O Enable GIO01 as caps lock LED 1– enable as caps lock LED 0 – general purpose I/O Enable GIO00 as Katakana LED 1– enable as Katakana LED 0 – general purpose I/O DOC8-342-TR-080 Confidential 8-3 bit 0 RES USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Internal virtual SMBus devices If a pin is used for general purpose I/O, the direction (input or output) and the data bit of the pin are in register R19, the GIO0 data/direction register. Writing to a bit whose pin is configured as an input has no effect. R19: GIO0 data/direction register bit definitions bit7 DIR03 bit 6 DIR02 bit 5 DIR01 bit 4 DIR00 bit 3 DAT03 bit 2 DAT02 bit 1 DAT01 bit 0 DAT00 R19: GIO0 data/direction register bit descriptions DIR03 DIR02 DIR01 DIR00 DAT03 DAT02 DAT01 DAT00 8-4 Direction of pin GIO03 1– output 0 – input Direction of pin GIO02 1– output 0 – input Direction of pin GIO01 1– output 0 – input Direction of pin GIO00 1– output 0 – input Data of pin GIO03 Data of pin GIO02 Data of pin GIO01 Data of pin GIO00 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic R8HC342 Preliminary system management controller product USAR − A Semtech Company Internal virtual SMBus devices GIO1: Analog output for flat panel digital controls Overview GIO1 is a two or four channel analog output device. Two pins are configurable as ACPI GPE0 and GPE1 inputs. (This configuration is done in register R02; see Chapter 7.) If they are configured as GPE input, then GIO1 is available only as a two-pin device. All of the GIO1 pins can operate in a digital input/output mode. If GIO1 is configured as a two-pin device (default mode) its output can function as either a Pulse Width Modulation (PWM) generator or a D/A converter. To select PWM or D/A mode, the OEM must configure the control register defining its operating mode. If the GIO1 is configured as a four-pin device, then two of the pins can be configured as PWM and two function as D/A analog outputs. The following table lists the pin names, power on default assignments as well as the function of each pin in two and four-pin modes. GIO1 pin usage Pin name GIO13 GIO12 GPE6/GIO11 GPE5/GIO10 Default GIO13 GIO12 GPE6 GPE5 2-pin analog function PWM or D/A PWM or D/A Not available Not available 4-pin analog function D/A D/A PWM PWM Features • Includes general I/O configuration • Programmable enhanced general I/O function • Can be configured as either D/A or PWM • Two D/A or PWM channels • © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 8-5 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Internal virtual SMBus devices Registers Register R41 determines the mode of the GIO1x pins. It is not valid to assign the same pin both as D/A and to an enabled PWM channel. If a pin is not assigned as D/A, and it is not assigned to an enabled PWM channel, and it was not configured as a GPE input, then it is used for general I/O (the default). R41: GIO1 mode register bit definitions bit7 RES bit 6 RES bit 5 DA1 bit 4 DA0 bit 3 PWM11 bit 2 PWM1EN bit 1 PWM01 bit 0 PWM0EN R41: GIO1 mode register bit descriptions RES DA1 DA0 PWM11 PWM1EN PWM01 PWM0EN 8-6 Reserved 1– Use GIO13 as DA1 1– Use GIO12 as DA0 1 – Use GIO13 as PWM11 0 – Use GIO11 as PWM10 1 – Enable channel PWM1x 1 – Use GIO12 as PWM01 0 – Use GIO10 as PWM00 1 – Enable channel PWM0x DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic R8HC342 Preliminary system management controller product USAR − A Semtech Company Internal virtual SMBus devices If a pin is assigned for general I/O, then the appropriate bits in R42 contain the direction and data of the I/O. Writing to a bit whose pin is configured as an input has no effect. R42: GIO1 data/direction register bit definitions bit7 DIR13 bit 6 DIR12 bit 5 DIR11 bit 4 DIR10 bit 3 DAT13 bit 2 DAT12 bit 1 DAT11 bit 0 DAT10 R42: GIO1 data/direction register bit descriptions DIR13 DIR12 DIR11 DIR10 DAT13 DAT12 DAT11 DAT10 Direction of pin GIO13 1– output 0 – input Direction of pin GIO12 1– output 0 – input Direction of pin GIO11 1– output 0 – input Direction of pin GIO10 1– output 0 – input Data of pin GIO13 Data of pin GIO12 Data of pin GIO11 Data of pin GIO10 Note: Note Only two simultaneous PWM outputs are available. PWM Channel 0 can be selected to GIO12 or GIO10, where it is referred to as PWM01 or PWM00 respectively, and PWM Channel 1 can be selected to GIO13 or GIO11, where it is referred to as PWM11 or PWM10 respectively. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 8-7 USAR − A Semtech Company Internal virtual SMBus devices ACPITroller™ Basic UR8HC342 Preliminary system management controller product PWM operation For each PWM channel, the PWM generated is controlled by 14 bits, which are contained in registers R43-R46. These 14 bits are further broken down into a group of upper eight bits and a group of lower six bits. For PWM1, the upper eight bits are located in R43, and the lower six bits are located in the lower six bits of R44. . For PWM0, the upper eight bits are located in R45, and the lower six bits are located in the lower six bits of R46. The manner in which the PWM works is based on a cycle and a sub-cycle. For an oscillation frequency XIN of 8MHz, the cycle period is 4096µs. Each cycle is broken down into sub-cycles of 64 µs. The time resolution available is 250 ns. The upper eight bits of data determine how long an “H”-level signal is output during each sub-cycle. If the upper eight bits contain the value N, then in each sub-cycle the output signal is H for a time of N*t, where t = 250 ns, the minimum time resolution. The lower six bits allow the user to lengthen the high, for some sub-cycles, by a duration of t = 250 ns. As indicated in the table below, these bits determine which sub-cycles are lengthened. For each pulse lengthened, the leading edge of the pulse is lengthened. As a result, an accurate wave form can be duplicated without the use of complex external filters – by changing the length of specific sub-periods instead of simply changing the global “H” duration. For example, if the upper eight bits of the 14-bit data are 0316 and the lower six bits are 0516, the length of the “H”- level output in sub-periods t8, t24, t32, t40 and t56 is 4*t, and its length 3*t in all other sub-periods. Relationship between the lower 6 bits of data and the period set by the ADD bit Lower 6 bits of data LSB 000000 000001 000010 000100 001000 010000 100000 Sub-periods tm length end (m = 0 to 63) None m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7,..., 57, 59, 61, 63 Data written to the lower register is transferred to the PWM latch once during each PWM period (every 4096µs), and data written to the higher register is transferred to the PWM latch once during each sub-period (every 64µs). 8-8 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic R8HC342 Preliminary system management controller product Internal virtual SMBus devices USAR − A Semtech Company The signal output to the PWM output pin corresponds to the contents of the latch. When the lower register is read, the contents of the latch are read. Bit 7 of the lower register indicates whether the transfer to the PWM latch is completed; the transfer is considered complete when bit 7 is zero. D/A operations The D/A converter provides 8-bit resolution and can output to two channels. D/A conversion is initiated by writing a non-zero value into the D/A data register for the D/A channel (R47 for channel 1, R48 for channel 0). The D/A conversion results are output on the corresponding output channel, if the D/A enable flag for the channel is set to 1. The output analog voltage (“V”) is determined by value “n” (n = decimal number) in the D/A conversion resister, as follows: V=(VREF)(n/256) (n=0255), where VREF indicates a reference voltage. Note: When using a D/A converter, set Vcc to 4.0V or more. Reset Considerations At reset, all control registers are cleared to 0 and all data registers are also cleared to 0. Therefore, all pins are placed in a high impedance state. Since the D/A output does not have a buffer, an external buffer should be used when connecting it to a low-impedance load. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 8-9 USAR − A Semtech Company Internal virtual SMBus devices ACPITroller™ Basic UR8HC342 Preliminary system management controller product GIO2: 3 channel 10-bit analog to digital converter Overview GIO2 can function as a 10-bit A/D converter or as a general purpose I/O device. To use each of the A/D channels, the OEM initializes the corresponding channels as described in this section. Features • Can be configured as either general I/O or A/D • 10-bit A/D • Up to three A/D channels • Programmable enhanced general I/O function IVS2 pin usage Pin name GIO2:0 GIO2:1 GIO2:2/SS_SDA1 8-10 Power on default function Input Input Input. If the internal Smart Selector is enabled this pin acts as the second SMBus data line DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic R8HC342 Preliminary system management controller product USAR − A Semtech Company Internal virtual SMBus devices Registers If a pin is used for general purpose I/O, the direction (input or output) and the data bit of the pin are in register R49, the GIO2 data/direction register. Writing to a bit whose pin is configured as an input has no effect. R49: GIO2 data/direction register bit definitions bit7 RES bit 6 DIR22 bit 5 DIR21 bit 4 DIR20 bit 3 RES bit 2 DAT22 bit 1 DAT21 bit 0 DAT20 R49: GIO2 data/direction register bit descriptions RES DIR22 DIR21 DIR20 DAT22 DAT21 DAT20 reserved Direction of pin GIO22 1– output 0 – input Direction of pin GIO21 1– output 0 – input Direction of pin GIO20 1– output 0 – input Data of pin GIO22 Data of pin GIO21 Data of pin GIO20 If the pins are configured for A/D conversion, the digital data is returned in the read-only registers R50-R55 (2 bytes of data for each A/D channel). A/D Comparison Voltage Generator In 10-bit mode, the A/D function divides the voltage between AVss and Vref by 1024. The result returned signifies the number of these divisions to which the input analog voltage corresponds. Thus, in 10 bit A/ D mode, with 10 bit read: Vref = Vref /1024 n (n=0 to 1023). In 10 bit A/D mode with 8 bit read: Vref = Vref / 256 n (n=0 to 255). © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 8-11 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Internal virtual SMBus devices GIO3: general purpose I/O GIO3 is a 6-pin port. The pins can be configured as ACPI general purpose event inputs (GPE) (see Chapter 7), or as general purpose I/O pins (the default). If a pin is used for general purpose I/O, the direction (input or output) of the pin are specified in register R56, the GIO3 direction register, and the data bit of the pin is in register R57, the GIO3 data register. Writing to a bit whose pin is configured as an input has no effect. R56: GIO3 direction register bit definitions bit7 DIR37 bit 6 DIR36 bit 5 DIR35 bit 4 DIR34 bit 3 DIR33 bit 2 DIR32 bit 1 RES bit 0 RES R56: GIO3 direction register bit descriptions RES DIR37 DIR36 DIR35 DIR34 DIR33 DIR32 8-12 reserved Direction of pin GIO37 1– output 0 – input Direction of pin GIO36 1– output 0 – input Direction of pin GIO35 1– output 0 – input Direction of pin GIO34 1– output 0 – input Direction of pin GIO33 1– output 0 – input Direction of pin GIO32 1– output 0 – input DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic R8HC342 Preliminary system management controller product USAR − A Semtech Company Internal virtual SMBus devices R57: GIO3 data register bit definitions bit7 DAT07 bit 6 DAT06 bit 5 DAT05 bit 4 DAT04 bit 3 DAT03 bit 2 DAT02 bit 1 RES bit 0 RES R57: GIO3 data register bit descriptions RES DAT37 DAT36 DAT35 DAT34 DAT33 DAT32 © 1999-2000 USAR − A Semtech Company reserved Data of pin GIO37 Data of pin GIO36 Data of pin GIO35 Data of pin GIO34 Data of pin GIO33 Data of pin GIO32 DOC8-342-TR-080 Confidential 8-13 USAR − A Semtech Company Internal virtual SMBus devices ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 8-14 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Electrical characteristics USAR − A Semtech Company Electrical characteristics Absolute maximum ratings (VSS = 0V, Ambient Temperature TA is in the range TLOW to THIGH) Absolute maximum ratings Parameter Supply Voltage Symbol VDD Value Unit -0.3 to +7.0 V Input voltage All pins except 2-9 Pins 2-9 VIN -0.3 to VDD+0.3 VIN -0.3 to +5.8 Output current Total peak for all pins Total average for all pins All pins except 31-34 Peak for each pin Average for each pin Pins 31-34 Peak for each pin Average for each pin Temperature range Operating Temperature Storage Temperature © 1999-2000 USAR − A Semtech Company V ∑IOH (PEAK) ∑IOL (PEAK) ∑IOH (AVG) ∑IOL (AVG) -80 80 -40 40 IOH (PEAK) IOL (PEAK) -10 10 mA IOH (AVG) IOL (AVG) -5 5 mA IOH (PEAK) IOL (PEAK) -10 20 mA IOH (AVG) IOL (AVG) -5 15 mA -20 to 85 -40 to 125 ºC ºC TLOW to THIGH TSTG DOC8-342-TR-080 Confidential V 9-1 mA mA USAR − A Semtech Company Electrical characteristics ACPITroller™ Basic UR8HC342 Preliminary system management controller product Recommended operating conditions / electrical characteristics Digital section (VSS = 0V, Ambient Temperature TA is in the range TLOW to THIGH) Recommended operating conditions/electrical characteristics, digital Section Parameter Supply voltage Input logic high voltage All pins except 2-9 Pins 2-9 Symbol VDD VIH VIH Input logic low voltage All pins except 28 Pin 28 VI = VSS, VDD) Input current Input Pull-up Current (pins 56-58 / IP6-IP8, VI = VSS) Output voltage IOH = -1.0 mA IOL = 1.6 mA Current Consumption Full Speed Mode (FOSC=4MHz) Reduced Power Mode (FOSC=4MHz) Stop Mode (Interrupts active, FOSC=0) Min 2.7 Typ Max 3.0 0.8VDD 0.8VDD VIL VIL IIL / IIH 0 0 -5.0 IPUP -120 VOH VOL NOTE1 IDD IDD VDD–1.0 IDD 5.5 Unit V VDD V 5.5 0 3.5 750 .1 V 0.2VDD 0.16VDD 5.0 V V µA -10 µA 0.4 V V 7.0 1.0 (TA = 25ºC ) 10 (TA = 85ºC ) mA µA µA NOTE1 Current consumption values do not include any loading on the output pins or Analog Reference Current for the built-in A/D or D/A modules. 9-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Electrical characteristics Recommended operating conditions / electrical characteristics Analog section (VSS = 0V, Ambient Temperature TA is in the range TLOW to THIGH) Recommended operating conditions/electrical characteristics, analog section Parameter Analog Signal Ground Analog Reference Voltage A/D Resolution A/D Absolute Accuracy A/D Analog Input Voltage Range A/D Analog Input Current Analog Reference Current NOTE2 (A/D is active) D/A Resolution D/A Absolute Accuracy D/A Output Impedance Analog Reference Current NOTE3 (D/A is active, Output = Full Scale) Symbol Min Typ Max Unit AVSS 0 V AVREF 2.7 VDD VDD V - 10 ±4 AVREF 5.0 Bits LSb V µA IAVREF 200 µA - 8 2.5 4.0 Bits % KOhms 3.2 mA VIA IIA RO IAVREF AVSS 1 2.5 NOTE2 Since built-in A/D module consumes current only during short periods of time when A/D conversion is actually requested, the Analog Reference Current for the built-in A/D module is not a significant contributor to the overall power consumption. NOTE3 The Analog Reference Current for the built-in D/A module correlates linearly to the Output Voltage. For D/A output of 0V, the Analog Reference Current is null. For D/A outputs approaching Full Scale (AVREF ), the maximum Analog Reference Current is indicated in this Table. This current is a significant contributor to the overall power consumption. Power consumption while operating the PWM channels Users should consider the built-in PWM channels for generating slowly changing DC control voltages. Since continuous clocking is necessary for the PWM operations, the only penalty for using the built-in PWM channels is the requirement for the chip to operate at least in the Reduced Power Mode, with typical Current Consumption of 750 µA. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 9-3 USAR − A Semtech Company Electrical characteristics ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 9-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Sample schematics USAR − A Semtech Company Sample schematic © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential 10-1 USAR − A Semtech Company Sample schematics ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank 10-2 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Appendix A AlphaKey™ key numbers Appendix A USAR AlphaKey™ standard PS/2 key number definitions The following table lists Standard PS/2 key numbers used by the USAR AlphaKey™ keyboard manager. Standard PS/2 Key Number Definitions USAR Key # Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 © 1999-2000 USAR − A Semtech Company PS/2 Key # Dec 1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 Scan Codes Make/Break SCS1 Hex No code 29/A9 02/82 03/83 04/84 05/85 06/86 07/87 08/88 09/89 0A/8A 0B/8B 0C/8C 0D/8D 0E/8E 0F/8F 10/90 11/91 12/92 13/93 14/94 15/95 16/96 17/97 18/98 19/99 1A/9A 1B/9B 2B/AB 1E/9E 1F/9F 20/A0 21/A1 22/A2 23/A3 24/A4 DOC8-342-TR-080 Confidential Key Label Null key `/~ 1/! 2 /@ 3/# 4/$ 5/% 6/^ 7/& 8/* 9/( 0/) -/_ =/+ Backspace Tab Q W E R T Y U I O P [/{ ]/} \/| A S D F G H J A-1 USAR − A Semtech Company Appendix A AlphaKey™ key numbers ACPITroller™ Basic UR8HC342 Preliminary system management controller product Standard PS/2 Key Number Definitions USAR PS/2 Scan Codes Key # Key # Make/Break SCS1 Dec Hex Dec Hex 24 38 25/A5 36 37 25 39 26/A6 38 26 40 27/A7 39 27 41 28/A8 40 28 43 1C/9C 41 29 46 2C/AC 42 2A 47 2D/AD 43 2B 48 2E/AE 44 2C 49 2F/AF 45 2D 50 30/B0 46 2E 51 31/B1 47 2F 52 32/B2 48 30 53 33/B3 49 31 54 34/B4 50 32 55 35/B5 51 33 61 39/B9 52 34 110 01/81 53 35 75 E0 52/E0 D2 54 36 76 E0 53/E0 D3 55 37 79 E0 4B/E0 CB 56 38 80 E0 47/E0 C7 57 39 81 E0 4F/E0 CF 58 3A 83 E0 48/E0 C8 59 3B 84 E0 50/E0 D0 60 3C 85 E0 49/E0 C9 61 3D 86 E0 51/E0 D1 62 3E 89 E0 4D/E0 CD 63 3F 100 37/B7 64 40 106 4E/CE 65 41 93 4F/CF 66 42 98 50/D0 67 43 103 51/D1 68 44 92 4B/CB 69 45 97 4C/CC 70 46 102 4D/CD 71 47 91 47/C7 72 48 96 48/C8 73 49 101 49/C9 74 4A 99 52/D2 75 4B 104 53/D3 76 4C 105 4A/CA 77 4D 108 E0 1C/E0 9C 78 4E 95 E0 35/E0 B5 79 4F 112 3B/BB 80 50 113 3C/BC 81 51 114 3D/BD 82 52 115 3E/BE 83 53 116 3F/BF A-2 DOC8-342-TR-080 Confidential Key Label K L ;/: ‘/“ Enter Z X C V B N M ,/< ./> / /? Space Esc Insert Delete Arrow Left Home End Arrow Up Arrow Down Page Up Page Down Arrow Right N. Star N. + N1 / K.P.End N2 / K.P.Arrow Down N3 / K.P.PgDn N4 / K.P.Arrow Left N5 N6 / K.P.Arrow Right N7 / K.P.Home N8 / K.P.Arrow Up N9 / K.P.PgUp N0 / K.P.Ins N. Period / K.P.Del N. N. Enter N. / F1 F2 F3 F4 F5 © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Appendix A AlphaKey™ key numbers USAR − A Semtech Company Standard PS/2 Key Number Definitions USAR PS/2 Scan Codes Key # Key # Make/Break SCS1 Dec Hex Dec Hex 54 117 40/C0 84 85 55 118 41/C1 86 56 119 42/C2 87 57 120 43/C3 88 58 121 44/C4 89 59 122 57/D7 90 5A 123 58/D8 91 5B 44 2A/AA 92 5C 57 36/B6 93 5D 60 38/B8 94 5E 62 E0 38/E0 B8 95 5F 58 1D/9D 96 60 64 E0 1D/E0 9D 97 61 30 3A/BA 98 62 90 45/C5 99 63 125 46/C6 100 64 124 E0 2A E0 37 / E0 B7 E0 AA 101 65 126 E1 1D 45 E1 9D C5 102 66 E0 5B/E0 DB 103 67 E0 5C/E0 DC 104 68 E0 5D/E0 DD 105 69 FF 106 6A No code 107 6B No code 108 6C E0 5E/E0 DE 109 6D E0 5F/E0 DF 110 6E E0 63/E0 E3 111 6F 70/F0 112 70 7B/FB 113 71 79/F9 114 72 7D/FD 115 73 73/F3 116 74 5B/DB 117 75 5C/DC 118 76 5D/DD 119 77 63/E3 120 78 65/E5 121 79 66/E6 122 7A 68/E8 123 7B 69/E9 124 7C 6B/EB 125– 7D – 127 7F © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential Key Label F6 F7 F8 F9 F10 F11 F12 L. Shift R. Shift L. Alt R. Alt L. Ctrl R. Ctrl Caps Lock Num Lock Scroll Lock Print Scr / SysReq Pause / Break Left Win Right Win Win Application Overrun Error Function Key Sticky Key Power event Sleep event Wake event Katakana NFER, F20 XFER, F17 Yen, F23 //_ F13 F14 F15 F16 F18 F19 F21 F22 F24 Reserved A-3 USAR − A Semtech Company Appendix A AlphaKey™ key numbers ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank A-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Appendix B AlphaKey keyboard matrix USAR − A Semtech Company Appendix B USAR AlphaKey™ default matrix & layout USAR AlphaKey™ default scan matrix Columns Rows COL 0 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 00 01 02 03 04 05 06 07 0 0 0 0 0 0 0 106 Function ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 08 09 0A 0B 0C 0D 0E 0F 0 0 0 0 0 102 Left Win 0 0 COL 2 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 10 11 12 13 14 15 16 17 15 97 2 30 41 29 16 52 COL 3 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 18 19 1A 1B 1C 1D 1E 1F 0 0 0 0 94 Right Alt 0 0 93 Left Alt COL 1 © 1999-2000 USAR − A Semtech Company Matrix RAM offset USAR key number DOC8-342-TR-080 Confidential QWERTY layout key label Tab Caps Lock 1/ ! S Z A Q escape NumPad layout key label Fn layout key label Function Function Left Win Left Win Tab Caps Lock 1/ ! S Z A Q escape Tab Caps Lock 1/! S Z A Q escape Right Alt Right Alt Left Alt Left Alt B-1 USAR − A Semtech Company Appendix B AlphaKey™ keyboard matrix ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR AlphaKey™ default scan matrix B-2 Columns Rows Matrix RAM offset USAR key number QWERTY layout key label F1 F2 F3 E D W 2/@ X NumPad layout key label F1 F2 F3 E D W 2/@ X Fn layout key label F1 F2 F3 E D W 2/@ X COL 4 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 20 21 22 23 24 25 26 27 79 80 81 18 31 17 3 42 COL 5 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 28 29 2A 2B 2C 2D 2E 2F 141 140 136 48 51 134 137 135 8/* 9/( | ,/< space K U M 8 / up arrow 9 / PGUP 5 ,/< space 2 / dn arrow 4 / left arrow 0 / INS 8/* 9/( | ,/< space K U M COL 6 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 30 31 32 33 34 35 36 37 84 4 5 32 43 19 6 82 F6 3/# 4/$ F C R 5/% F4 F6 3/# 4/$ F C R 5/% F4 F6 3/# 4/$ F C R 5/% F4 COL 7 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 38 39 3A 3B 3C 3D 3E 3F 87 83 7 44 45 33 20 85 F9 F5 6/^ V B G T F7 F9 F5 6/^ V B G T F7 F9 F5 6/^ V B G T F7 COL 8 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 40 41 42 43 44 45 46 47 88 89 86 46 34 21 142 138 F10 F11 F8 N H Y 7/& J F10 F11 F8 N H Y 7 / HOME 1 / END F10 F11 F8 N H Y 7/& J DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Appendix B AlphaKey keyboard matrix USAR − A Semtech Company USAR AlphaKey™ default scan matrix Columns Rows COL 9 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 48 49 4A 4B 4C 4D 4E 4F 90 143 133 145 0 0 129 L 139 num lock ROW 0 50 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 COL 10 COL 11 COL 12 COL 13 © 1999-2000 USAR − A Semtech Company Matrix RAM offset USAR key number NumPad layout key label F12 * 6 / rt arrow . / DEL Fn layout key label F12 0/) O ./> 3 / PGDN num lock NFER 1, F20 scroll lock 51 52 53 54 55 56 57 101 Pause / Break 13 = / + 27 ] / } 28 \ / | 0 0 26 [ / { 1 `/~ Pause / Break =/+ ]/} \/| Pause / Break =/+ ]/} \/| [/{ `/~ [/{ `/~ ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 58 59 5A 5B 5C 5D 5E 5F 14 146 147 39 104 40 0 13 Back Space down arrow up arrow ‘/“ Win appl. ENTER Back Space down arrow up arrow ‘/“ Win appl. ENTER Back Space PGDN PGUP ‘/“ Win appl. ENTER insert insert insert ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 60 61 62 63 64 65 66 67 0 0 0 103 RWIN 0 0 0 0 RWIN RWIN ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 68 69 6A 6B 6C 6D 6E 6F 148 149 150 144 0 130 151 12 right arrow left arrow delete //? Num Lock left arrow delete / end home SysRq //? ;/: P -/_ + -/_ ;/: P -/_ DOC8-342-TR-080 Confidential QWERTY layout key label F12 0/) O ./> B-3 USAR − A Semtech Company Appendix B AlphaKey™ keyboard matrix ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR AlphaKey™ default scan matrix Columns Rows COL 14 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 70 71 72 73 74 75 76 77 0 95 left ctrl 0 0 0 0 96 right ctrl 0 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 78 79 7A 7B 7C 7D 7E 7F 91 left shift 0 92 right shift 0 0 0 0 0 COL 15 B-4 Matrix RAM offset USAR key number QWERTY layout key label DOC8-342-TR-080 Confidential NumPad layout key label Fn layout key label left ctrl left ctrl right ctrl right ctrl Page Up Page Up ]/} ]/} © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Appendix C Standard SMBus registers and protocol Appendix C Standard SMBus registers Protocol register, SMB_PRTCL This register determines the type of SMBus transaction generated on the SMBus. In addition to indicating the protocol type to the SMBus host controller, a write to this register initiates the transaction on the SMBus. Bit descriptions for protocol register SMB_PRTCL bit6 bit7 PROTOCOL bit5 bit4 bit3 bit2 bit1 bit0 The values of the PROTOCOL are as follows: PROTOCOL definitions for protocol register SMB_PRTCL Value (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C Meaning Controller Not In Use Reserved Write Quick Command Read Quick Command Send Byte Receive Byte Write Byte Read Byte Write Word Read Word Block Write Block Read Process Call When the OS initiates a new command such as write to the SMB_PRTCL register, the SMBus Controller first updates the SMB_STS register and then clears the SMB_PRTCL register. After the SMB_PRTCL register is cleared, the host controller query value is raised. © 1999-2000 USAR − A Semtech Company DOC8-342-TR-080 Confidential C-1 USAR − A Semtech Company Appendix C Standard SMBus registers and protocol ACPITroller™ Basic UR8HC342 Preliminary system management controller product Status register, SMB_STS This register indicates general status on the SMBus. This includes SMBus host controller command completion status, alarm received status, and error detection status (the error codes are defined later in this section). Whenever a new command is issued using a write to the protocol register (SMB_PRTCL), bits 7 and 2 of this register are reset to 0. This register is always written with the error code before clearing the protocol register. The SMBus host controller query event (that is, an SMBus host controller interrupt) is raised after the clearing of the protocol register. NOTE: The OS driver must ensure the ALRM bit is cleared after it has been serviced by writing ‘00’ to the SMB_STS register. Status register SMB_STS bit descriptions bit7 DONE bit6 ALRM bit5 RES bit4 RES bit3 RES bit2 STATUS bit1 RES bit0 RES Status register SMB_STS bit descriptions RES DONE ALRM STATUS Reserved. When set to 1, indicates the last command has completed and no error. When set to 1, indicates an SMBus alarm message has been received. When set to 1, indicates SMBus communication status for one of the reasons listed in the following table. The following table shows SMBus Status Codes. SMBus Status Codes Status Code Name SMBus OK 00h 07h SMBus Unknown Failure 10h SMBus Device Address Not Acknowledged SMBus Device Error Detected SMBus Device Command Access Denied 11h 12h 13h C-2 SMBus Unknown Error Description Indicates the transaction has been successfully completed. Indicates failure because of an unknown SMBus error. Indicates the transaction failed because the slave device address was not acknowledged. Indicates the transaction failed because the slave device signaled an error condition. Indicates the transaction failed because the SMBus host does not allow the specific command for the device being addressed. For example, the SMBus host might not allow a caller to adjust the Smart Battery Charger's output. Indicates the transaction failed because the SMBus host encountered an unknown error. DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Appendix C Standard SMBus registers and protocol SMBus Status Codes Status Code Name 17h SMBus Device Access Denied 18h 19h 1Ah Description Indicates the transaction failed because the SMBus host does not allow access to the device addressed. For example, the SMBus host might not allow a caller to directly communicate with an SMBus device that controls the system's power planes. SMBus Timeout Indicates the transaction failed because the SMBus host detected a timeout on the bus. SMBus Host Unsupported Indicates the transaction failed because the Protocol SMBus host does not support the requested protocol. SMBus Busy Indicates that the transaction failed because the SMBus host reports that the SMBus is presently busy with some other transaction. For example, the Smart Battery might be sending charging information to the Smart Battery Charger. All other status codes are reserved. Address register, SMB_ADDR This register contains the 7-bit address to be generated on the SMBus. This is the first byte to be sent on the SMBus for all of the different protocols. SMB_ADDR address register bit definitions bit 6 bit7 ADDRESS (A6:A0) RES ADDRESS bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RES Reserved 7-bit SMBus address Command register, SMB_CMD This register contains the command byte to be sent to the target device on the SMBus and is used for all of the protocols except for Receive Byte, Read Quick Command, and Write Quick Command. For those protocols, the value in SMB_CMD has no effect. SMB_CMD command register bit definitions bit 6 bit 7 COMMAND © 1999-2000 USAR − A Semtech Company bit 5 bit 4 DOC8-342-TR-080 Confidential bit 3 bit 2 bit 1 C-3 bit 0 USAR − A Semtech Company Appendix C Standard SMBus registers and protocol ACPITroller™ Basic UR8HC342 Preliminary system management controller product Data register array, SMB_DATA[i], i=0-31 This bank of registers contains the remaining bytes to be sent or received in any of the different protocols that can be run on the SMBus. The SMB_DATA registers are defined on a per-protocol basis and, as such, provide efficient use of register space. SMB_DATA[I] data register bit definitions bit7 DATA bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Block count register, SMB_BCNT This register contains the block count, used in the Block Read and Block Write protocols. SMB_BCNT block count register bit definitions bit7 RES RES BCNT bit 6 bit 5 bit 4 BCNT bit 3 bit 2 bit 1 bit 0 Reserved Block Count Alarm address register, SMB_ALRM_ADDR This register contains the source address of an alarm message received by the host controller from the SMBus master that initiated the alarm. The address indicates the slave address of the device on the SMBus that initiated the alarm message. The status of the alarm message is contained in the SMB_ALRM_DATAx registers. Once an alarm message has been received, the SMBus host controller must clear the ALRM status bits to receive further alarm messages. C-4 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product USAR − A Semtech Company Appendix C Standard SMBus registers and protocol The OS driver does not read the alarm address and alarm data registers until the alarm status bit is set. The OS driver then reads the three bytes, and clears the alarm status bit to indicate that the alarm registers are now available for the next event. SMB_BCNT block count register bit definitions bit 6 bit7 ADDRESS (A6:A0) RES ADDRESS bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RES Reserved 7-bit slave address (A6:A0) of the SMBus device that initiated the alarm message Alarm data registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1] These registers contain the two data bytes of an alarm message received by the host controller, from the SMBus master that initiated the alarm. These data bytes indicate the specific reason for the alarm message, to allow the OS to take corrective action. Once an alarm message has been received, the SMBus host controller must clear the ALRM status bits to receive further alarm messages. SMB_ALRM_DATA alarm data register bit definitions bit 6 bit7 DATA (D7:0) © 1999-2000 USAR − A Semtech Company bit 5 bit 4 DOC8-342-TR-080 Confidential bit 3 bit 2 bit 1 bit 0 C-5 USAR − A Semtech Company Appendix C Standard SMBus registers and protocol ACPITroller™ Basic UR8HC342 Preliminary system management controller product Standard SMBus protocol Protocol description All registers should be written with the appropriate values before writing the protocol value that starts the SMBus transaction. All transactions can be completed in one pass. Write Quick Data Sent: • SMB_ADDR: • SMB_PRTCL: Address of SMBus device. Write 0x02 to initiate quick write protocol. Data Returned: • SMB_STS: • SMB_PRTCL: Status code for transaction. 0x00 to indicate command completion. Read Quick Data Sent: • SMB_ADDR: • SMB_PRTCL: Address of SMBus device. Write 0x03 to initiate quick read protocol. Data Returned: • SMB_STS: • SMB_PRTCL: Status code for transaction. 0x00 to indicate command completion. Send Byte Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Write 0x04 to initiate send byte protocol. Data Returned: • SMB_STS: • SMB_PRTCL: C-6 Status code for transaction. 0x00 to indicate command completion. DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Appendix C Standard SMBus registers and protocol USAR − A Semtech Company Receive Byte Data Sent: • SMB_ADDR: • SMB_PRTCL: Address of SMBus device. Write 0x05 to initiate receive byte protocol. Data Returned: • SMB_DATA[0]: • SMB_STS: • SMB_PRTCL: Data byte received. Status code for transaction. 0x00 to indicate command completion. Write Byte Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_DATA[0]: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Data byte to be sent. Write 0x06 to initiate write byte protocol. Data Returned: • SMB_STS: • SMB_PRTCL: Status code for transaction. 0x00 to indicate command completion. Read Byte Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Write 0x07 to initiate read byte protocol. Data Returned: • SMB_DATA[0]: • SMB_STS: • SMB_PRTCL: © 1999-2000 USAR − A Semtech Company Data byte received. Status code for transaction. 0x00 to indicate command completion. DOC8-342-TR-080 Confidential C-7 USAR − A Semtech Company Appendix C Standard SMBus registers and protocol ACPITroller™ Basic UR8HC342 Preliminary system management controller product Write Word Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_DATA[0]: • SMB_DATA[1]: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Low data byte to be sent. High data byte to be sent. Write 0x08 to initiate write word protocol. Data Returned: • SMB_STS: • SMB_PRTCL: Status code for transaction. 0x00 to indicate command completion. Read Word Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Write 0x09 to initiate read word protocol. Data Returned: • SMB_DATA[0]: • SMB_DATA[1]: • SMB_STS: • SMB_PRTCL: Low data byte received. High data byte received. Status code for transaction. 0x00 to indicate command completion. Write Block Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_DATA[0• SMB_BCNT: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Data bytes to write (1-32). Number of data bytes (1-32) to be sent. Write 0x0A to initiate write block protocol. Data Returned: • SMB_PRTCL: • SMB_STS: C-8 0x00 to indicate command completion. Status code for transaction. DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company ACPITroller™ Basic UR8HC342 Preliminary system management controller product Appendix C Standard SMBus registers and protocol USAR − A Semtech Company Read Block Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Write 0x0B to initiate read block protocol. Data Returned: • SMB_BCNT: • SMB_DATA[0:31 • SMB_STS: • SMB_PRTCL: Number of data bytes (1-32) received. Data bytes received (1-32). Status code for transaction. 0x00 to indicate command completion. Process Call Data Sent: • SMB_ADDR: • SMB_CMD: • SMB_DATA[0]: • SMB_DATA[1]: • SMB_PRTCL: Address of SMBus device. Command byte to be sent. Low data byte to be sent. High data byte to be sent. Write 0x0C to initiate process call protocol. Data Returned: • SMB_DATA[0]: • SMB_DATA[1]: • SMB_STS: • SMB_PRTCL: © 1999-2000 USAR − A Semtech Company Low data byte received. High data byte received. Status code for transaction. 0x00 to indicate command completion. DOC8-342-TR-080 Confidential C-9 USAR − A Semtech Company Appendix C Standard SMBus registers and protocol ACPITroller™ Basic UR8HC342 Preliminary system management controller product This page intentionally left blank C-10 DOC8-342-TR-080 Confidential © 1999-2000 USAR − A Semtech Company A Semtech Company For sales information and product literature, contact: USAR − A Semtech Company 568 Broadway New York, NY 10012 [email protected] http://www.usar.com 212 226 2042 Telephone 212 226 3215 Telefax In Japan: Semtech Japan Tel: +81-45-948-5925 Fax: +81-45-948-5930 In Taiwan: Semtech Asia/Pacific Sales Tel: +886-2-2748-3380 Fax: +886-2-2748-3390 Koryo Electronics Co., Ltd. Tel: +886-2-2698-1143 E-mail: [email protected] In Korea: Semtech Korea Tel: +82-2-527-4377 Fax: +82-2-527-4377 In Europe: Semtech Limited +44-1592-630350 +44-1592-774781 Copyright 1998-2000 USAR Systems, Inc., A Semtech Company All rights reserved. No part of this datasheet may be reproduced in any way without the express written consent of USAR Systems. All trademarks belong to their respective companies. USAR Systems reserves the right to make changes without further notice to any products herein to improve reliability, function or design. USAR Systems does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent and copyright rights nor the rights of others.