Dual, Ultralow Noise Variable Gain Amplifier AD604 a FEATURES Ultralow Input Noise at Maximum Gain: 0.80 nV/√Hz, 3.0 pA/√Hz Two Independent Linear-in-dB Channels Absolute Gain Range per Channel Programmable: 0 dB to +48 dB (Preamp Gain = +14 dB), through +6 dB to +54 dB (Preamp Gain = +20 dB) 61.0 dB Gain Accuracy Bandwidth: 40 MHz (–3 dB) 300 kV Input Resistance Variable Gain Scaling: 20 dB/V through 40 dB/V Stable Gain with Temperature and Supply Variations Single-Ended Unipolar Gain Control Power Shutdown at Lower End of Gain Control Can Drive A/D Converters Directly FUNCTIONAL BLOCK DIAGRAM PAO –DSX +DSX VGN GAIN CONTROL AND SCALING VREF DIFFERENTIAL ATTENUATOR R-1.5R LADDER NETWORK PAI AFA OUT 0 TO –48.4dB VOCM PROGRAMMABLE ULTRALOW NOISE PREAMPLIFIER G = 14–20dB PRECISION PASSIVE INPUT ATTENUATOR FIXED GAIN AMPLIFIER +34.4dB APPLICATIONS Ultrasound and Sonar Time-Gain Control High Performance AGC Systems Signal Measurement PRODUCT DESCRIPTION The AD604 is an ultralow noise, very accurate, dual channel, linear-in-dB variable gain amplifier (VGA) optimized for timebased variable gain control in ultrasound applications; however it will support any application requiring low noise, wide bandwidth variable gain control. Each channel of the AD604 provides a 300 kΩ input resistance and unipolar gain control for ease of use. User determined gain ranges, gain scaling (dB/V) and dc level shifting of output further optimize application performance. Each channel of the AD604 utilizes a high performance preamplifier that provides an input referred noise voltage of 0.8 nV/√Hz. The very accurate linear-in-dB response of the AD604 is achieved with the differential input exponential amplifier (DSX-AMP) architecture. Each of the DSX-AMPs comprise a variable attenuator of 0 dB to 48.36 dB followed by a high speed fixed gain amplifier. The attenuator is based on a seven stage R-1.5R ladder network. The attenuation between tap points is 6.908 dB and 48.36 dB for the ladder network. Each independent channel of the AD604 provides a gain range of 48 dB which can be optimized for the application by programming the preamplifier with a single external resistor in the preamp feedback path. The linear-in-dB gain response of the AD604 can be described by the equation: G (dB) = (Gain Scaling (dB/V ) × VGN (V )) + (Preamp Gain (dB) – 19 dB). Preamplifier gains between 5 and 10 (+14 dB and +20 dB) provide overall gain ranges per channel of 0 dB through +48 dB and +6 dB through +54 dB. The two channels of the AD604 can be cascaded to provide greater levels of gain range by bypassing the 2nd channel’s preamplifier. However, in multiple channel systems, cascading the AD604 with other devices in the AD60x VGA family, which do not include a preamplifier may provide a more efficient solution. The AD604 provides access to the output of the preamplifier allowing for external filtering between the preamplifier and the differential attenuator stage. The gain control interface provides an input resistance of approximately 2 MΩ and scale factors from 20 dB/V to 30 dB/V for a VREF input voltage of 2.5 V to 1.67 V respectively. Note that scale factors up to 40 dB/V are achievable with reduced accuracy for scales above 30 dB/V. The gain scales linear-in-dB with control voltages of 0.4 V to 2.4 V with the 20 dB/V scale. Below and above this gain control range, the gain begins to deviate from the ideal linear-in-dB control law. The gain control region below 0.1 V is not used for gain control. In fact when the gain control voltage is <50 mV the amplifier channel is powered down to 1.9 mA. The AD604 is available in a 24-pin plastic SSOP, SOIC and DIP, and is guaranteed for operation over the –40°C to +85°C temperature range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 AD604–SPECIFICATIONS (Each Amplifier Channel at TA = +258C, VS = 65 V, RS = 50 V, RL = 500 V, CL = 5 pF, VREF = 2.50 V (Scaling = 20 dB/V), 0 dB to +48 dB gain range (preamplifier gain = +14 dB), VOCM = 2.5 V, C1 and C2 = 0.1 mF (see Figure 35) unless otherwise noted) Parameter INPUT CHARACTERISTICS Preamplifier Input Resistance Input Capacitance Input Bias Current Peak Input Voltage Input Voltage Noise Input Current Noise Noise Figure DSX Input Resistance Input Capacitance Peak Input Voltage Input Voltage Noise Input Current Noise Noise Figure Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS –3 dB Bandwidth Slew Rate Output Signal Range Output Impedance Output Short-Circuit Current Harmonic Distortion HD2 HD3 HD2 HD3 Two-Tone Intermodulation Distortion (IMD) 3rd Order Intercept 1 dB Compression Point Channel-to-Channel Crosstalk Group Delay Variation VOCM Input Resistance ACCURACY Absolute Gain Error 0 dB to +3 dB +3 dB to +43 dB +43 dB to +48 dB Gain Scaling Error Output Offset Voltage Output Offset Variation Conditions Min Typ Max Unit Preamp Gain = +14 dB Preamp Gain = +20 dB VGN = 2.9 V, RS = 0 Ω Preamp Gain = +14 dB Preamp Gain = +20 dB Independent of Gain RS = 50 Ω, f = 1 MHz, VGN = 2.9 V RS = 200 Ω, f =1 MHz, VGN = 2.9 V 300 8.5 –27 ± 400 ± 200 kΩ pF µA mV mV 0.8 0.73 3.0 2.3 1.1 nV/√Hz nV/√Hz pA/√Hz dB dB VGN = 2.9 V VGN = 2.9 V RS = 50 Ω, f = 1 MHz, VGN = 2.9 V RS = 200 Ω, f =1 MHz, VGN = 2.9 V f = 1 MHz, VGN = 2.65 V 175 3.0 2.5 ± 2 1.8 2.7 8.4 12 –20 Ω pF V nV/√Hz pA/√Hz dB dB dB 40 170 2.5 ± 1.5 2 ± 40 MHz V/µs V Ω mA –54 –67 –43 –48 dBc dBc dBc dBc –74 –71 –12.5 dBc dBc dBm +15 dBm –30 dB dB ns kΩ Constant with Gain VGN = 1.5 V, Output = 1 V Step RL ≥ 500 Ω f = 10 MHz VGN = 1 V, VOUT = 1 V p-p f = 1 MHz f = 1 MHz f = 10 MHz f = 10 MHz VGN = 2.9 V, VOUT = 1 V p-p f = 1 MHz f = 10 MHz f = 10 MHz, VGN = 2.65 V, VOUT = 1 V p-p, Input Referred f = 1 MHz, VGN = 2.9 V, Output Referred VOUT = 1 V p-p, f = 1 MHz Ch #1: VGN = 2.65 V, Inputs Shorted Ch #2: VGN = 1.5 V (Mid Gain) 1 MHz < f < 10 MHz, Full Gain Range 0.25 V < VGN < 0.400 V 0.400 V < VGN < 2.400 V 2.400 V < VGN < 2.65 V 0.400 V < VGN < 2.400 V VREF = 2.500 V, VOCM = 2.500 V VREF = 2.500 V, VOCM = 2.500 V –2– ±2 45 –1.2 –1.0 –3.5 –50 +0.75 ± 0.3 –1.25 ± 0.25 ± 30 30 +3 +1.0 +1.2 +50 50 dB dB dB dB/V mV mV REV. 0 AD604 Parameter GAIN CONTROL INTERFACE Gain Scaling Factor Gain Range Input Voltage (VGN) Range Input Bias Current Input Resistance Response Time VREF Input Resistance POWER SUPPLY Specified Operating Range Power Dissipation Quiescent Supply Current Powered Down Power-Up Response Time Power-Down Response Time Conditions Min Typ VREF = 2.5 V, 0.4 V < VGN < 2.4 V VREF = 1.67 V Preamp Gain = +14 dB Preamp Gain = +20 dB 20 dB/V, VREF = 2.5 V 19 20 21 30 0 to +48 +6 to +54 0.1 to 2.9 –0.4 2 0.2 10 dB/V dB/V dB dB V µA MΩ µs kΩ ±5 +5 220 95 32 19 –12 1.9 –150 0.6 0.4 V V mW mW mA mA mA mA µA µs µs 48 dB Gain Change One Complete Channel One DSX Only One Complete Channel One DSX Only VPOS, One Complete Channel VPOS, One DSX Only VNEG, One Preamplifier Only VPOS, VGN < 50 mV, One Channel VNEG, VGN < 50 mV, One Channel 48 dB Gain Change, VOUT = 2 V p-p ABSOLUTE MAXIMUM RATINGS –15 Max 36 23 3.0 Unit ORDERING GUIDE Supply Voltage ± VS Pins 17, 18, 19, 20 (with Pins 16, 22 = 0 V) . . . . . . ± 6.5 V Input Voltages Pins 1, 2, 11, 12 . . . . . . . . . . . . . VPOS/2 ± 2 V Continuous Pins 4, 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2 V Pins 5, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPOS, VNEG Pins 6, 7, 13, 14, 23, 24 . . . . . . . . . . . . . . . . . . . . VPOS, 0 Internal Power Dissipation Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W Shrink Small Outline (RS) . . . . . . . . . . . . . . . . . . . . . 1.1 W Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature, Soldering 60 seconds . . . . . . . . . +300°C Model Temperature Range uJA Package Option* AD604AN AD604AR AD604ARS –40°C to +85°C –40°C to +85°C –40°C to +85°C 57°C/W 70°C/W 112°C/W N-24 R-24 R-24 *N = Plastic DIP, R = Small Outline IC (SOIC), RS = Shrink Small Outline Package (SSOP). NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Pins 1, 2, 11, 12, 13, 14, 23, 24 are part of a single-supply circuit and the part will most likely be damaged if any of these pins are accidentally connected to VN. 3 When driven from an external low impedance source. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD604 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD604 PIN DESCRIPTIONS Pin No. Mnemonic Description Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 –DSX1 +DSX1 PAO1 FBK1 PAI1 COM1 COM2 PAI2 FBK2 PAO2 +DSX2 –DSX2 VGN2 Pin 14 Pin 15 Pin 16 Pin 17 Pin 18 Pin 19 Pin 20 Pin 21 Pin 22 Pin 23 Pin 24 VOCM OUT2 GND2 VPOS VNEG VNEG VPOS GND1 OUT1 VREF VGN1 CH1 Negative Signal Input to DSX1. CH1 Positive Signal Input to DSX1. CH1 Preamplifier Output. CH1 Preamplifier Feedback Pin. CH1 Preamplifier Positive Input. CH1 Signal Ground; when connected to positive supply, Preamplifier1 will shut down. CH2 Signal Ground; when connected to positive supply, Preamplifier2 will shut down. CH2 Preamplifier Positive Input. CH2 Preamplifier Feedback Pin. CH2 Preamplifier Output. CH2 Positive Signal Input to DSX2. CH2 Negative Signal Input to DSX2. CH2 Gain-Control Input and Power-Down Pin. If grounded, device is off, otherwise positive voltage increases gain. Input to this pin defines common-mode of output at OUT1 and OUT2. CH2 Signal Output. Ground. Positive Supply. Negative Supply. Negative Supply. Positive Supply. Ground. CH1 Signal Output. Input to this pin sets gain-scaling for both channels +2.5 V = 20 dB/V, +1.67 V = 30 dB/V. CH1 Gain-Control Input and Power-Down Pin. If grounded, device is off; otherwise positive voltage increases gain. PIN CONFIGURATION –DSX1 1 24 VGN1 +DSX1 2 23 VREF PAO1 3 22 OUT1 FBK1 4 21 GND1 PAI1 5 20 VPOS AD604 COM1 6 TOP VIEW 19 VNEG (Not to Scale) COM2 7 18 VNEG PAI2 8 17 VPOS FBK2 9 16 GND2 PAO2 10 15 OUT2 +DSX2 11 14 VOCM –DSX2 12 13 VGN2 –4– REV. 0 Typical Performance Characteristics (per Channel)–AD604 (Unless otherwise noted G (preamp) = +14 dB, VREF = 2.5 V (20 dB/V Scaling), f = 1 MHz, RL = 500 V, CL = 5 pF, TA = +258C, VSS = 65 V) 50 G (PREAMP) = +14dB (0dB – +48dB) 50 40 30 GAIN – dB 3 CURVES –40°C, +25°C, +85°C 20 10 30 40 G (PREAMP) = +20dB (+6dB – +54dB) 20 10 ACTUAL 20 20dB/V VREF = 2.50V 10 DSX ONLY (–14dB – +34dB) 0 0 ACTUAL 30dB/V VREF = 1.67V 30 GAIN – dB 40 GAIN – dB 50 60 0 –10 –10 0.1 0.5 0.9 1.3 1.7 2.1 VGN – Volts 2.5 –20 0.1 2.9 0.5 0.9 1.3 1.7 2.1 VGN – Volts 2.5 Figure 2. Gain vs. VGN for Different Preamp Gains Figure 1. Gain vs. VGN 40 37.5 –10 0.1 2.9 0.5 0.9 1.3 1.7 2.1 VGN – Volts 2.5 2.9 Figure 3. Gain vs. VGN for Different Gain Scalings 2.0 2.0 1.5 1.5 1.0 1.0 32.5 30 ACTUAL 27.5 25 0.5 –40°C GAIN ERROR – dB GAIN ERROR – dB GAIN SCALING – dB/V THEORETICAL 35 +25°C 0 –0.5 +85°C 0.5 FREQ = 1MHz 0 –0.5 FREQ = 5MHz –1.0 –1.0 FREQ = 10MHz 22.5 1.5 1.75 2 VREF – Volts 2.25 2.5 –2.0 0.2 0.7 1.2 1.7 VGN – Volts –2.0 0.2 20 1.0 PERCENTAGE 0.5 0 –0.5 30dB/V VREF = 1.67V 1.2 1.7 VGN – Volts 2.2 2.7 25 N = 50 VGN1 = 1.0V VGN2 = 1.0V ∆G(dB) = G(CH1) – G(CH2) 1.5 20dB/V VREF = 2.50V 0.7 Figure 6. Gain Error vs. VGN at Different Frequencies 25 2.0 GAIN ERROR – dB 2.7 Figure 5. Gain Error vs. VGN at Different Temperatures Figure 4. Gain Scaling vs. VREF –1.0 2.2 15 10 20 PERCENTAGE 20 1.25 –1.5 –1.5 N = 50 VGN1 = 2.50V VGN2 = 2.50V ∆G(dB) = G(CH1) – G(CH2) 15 10 5 5 0 –1.0 –0.8 –0.6 –0.4 –0.2 0.1 0.3 0.5 0.7 0.9 DELTA GAIN – dB 0 –1.0 –0.8 –0.6 –0.4 –0.2 0.1 0.3 0.5 0.7 0.9 DELTA GAIN – dB –1.5 –2.0 0.2 0.7 1.2 1.7 VGN – Volts 2.2 Figure 7. Gain Error vs. VGN for Different Gain Scalings REV. 0 2.7 Figure 8. Gain Match; VGN1 = VGN2 = 1.0 V –5– Figure 9. Gain Match: VGN1 = VGN2 = 2.50 V AD604–Typical Performance Characteristics (per Channel) (Unless otherwise noted G (preamp) = +14 dB, VREF = 2.5 V (20 dB/V Scaling), f = 1 MHz, RL = 500 V, CL = 5 pF, TA = +258C, VSS = 65 V) 2.55 50 VGN = 2.5V 2.54 VGN = 2.9V 20 VGN = 1.5V 10 VGN = 0.5V 190 2.52 VOUT – Volts GAIN – dB –40°C 2.53 30 0 210 VOCM = 2.50V VGN = 0.1V –10 –20 NOISE – nV/√H z 40 2.51 2.50 +25°C 2.49 2.48 –30 2.47 VGN = 0.0V –40 +85°C 170 +85°C 150 +25°C 130 110 2.46 –50 100k 1M 10M FREQUENCY – Hz 2.45 0.2 100M Figure 10. AC Response –40°C 0.7 1.2 1.7 VGN – Volts 2.2 90 0.1 2.7 Figure 11. Output Offset vs. VN 0.9 1.3 1.7 2.1 VGN – Volts 2.5 2.9 Figure 12. Output Referred Noise vs. VGN 770 900 1000 0.5 VGN = 2.9V VGN = 2.9V 765 850 10 NOISE – pV/√H z NOISE – pV/√H z NOISE – nV/√H z 100 800 750 700 760 755 750 1 745 650 0.5 0.9 1.3 1.7 VGN – Volts 2.1 2.5 600 –40 2.9 Figure 13. Input Referred Noise vs. VGN dB NOISE – nV/√H z VGN = 2.9V RSOURCE ALONE 0.1 1 10 100 RSOURCE – Ω 1k Figure 16. Input Referred Noise vs. RSOURCE 0 20 40 60 TEMPERATURE – °C 80 90 Figure 14. Input Referred Noise vs. Temperature 10 1 –20 740 100k 1M FREQUENCY – Hz 10M Figure 15. Input Referred Noise vs. Frequency 40 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VGN = 2.9V RS = 240Ω 35 30 25 dB 0.1 0.1 20 15 10 5 0 1 10 100 RIN 1k 10k Figure 17. Noise Figure vs. RSOURCE –6– 0 0.4 0.8 1.2 1.6 2.0 VGN – Volts 2.4 2.8 Figure 18. Noise Figure vs. VGN REV. 0 AD604 –30 –50 HD2 –55 HD3 –60 –65 –20 VO = 1V p-p RS –40 HD2(10MHz) –45 –50 –55 HD3(10MHz) –60 –65 –70 HD2(1MHz) –75 –70 100k 1M 10M FREQUENCY – Hz Figure 19. Harmonic Distortion vs. Frequency –40 2.5 –5 PIN – dBm –60 –70 –80 –10 HD2(10MHz) HD3(10MHz) –50 HD2(1MHz) –60 HD3(1MHz) –70 0 15 10MHz –15 –20 5 –110 –30 –10 –120 –35 0.1 0.9 1.3 1.7 2.1 VGN – Volts 2.5 –15 0.4 2.9 Figure 23. 1 dB Compression vs. VGN 2V f = 10MHz 0 1MHz 0.5 f = 1MHz 10 –5 Figure 22. Intermodulation Distortion 250 VO = 1V p-p 20 INPUT SIGNAL LIMIT 800mV p-p –25 10.04 200 100 150 RSOURCE – Ω Figure 21. Harmonic Distortion vs. RSOURCE –100 9.98 10 10.02 FREQUENCY – MHz 50 25 –90 9.96 VO = 1V p-p VGN = 1.0V –40 2.9 0 –50 POUT – dBm 2.1 1.3 1.7 VGN – Volts 5 VO = 1V p-p VGN = 1.0V 500Ω –80 0.9 Figure 20. Harmonic Distortion vs. VGN –20 –30 DUT 50Ω –30 HD3(1MHz) –80 0.5 100M HARMONIC DISTORTION – dBc –35 IP3 – dBm –45 VO = 1V p-p VGN = +1.0V HARMONIC DISTORTION – dBc HARMONIC DISTORTION – dBc –40 0.9 1.4 1.9 VGN – Volts 2.4 2.9 Figure 24. 3rd Order Intercept vs. VGN 200 VO = 200mV p-p VGN = 1.5V VO = 2V p-p VGN = 1.5V 500mV 100 90 VGN – Volts 40mV / DIV 400mV / DIV 2.9V TRIG'D 10 0% 0V 500mV –2V 253ns 1.253µs 100ns / DIV Figure 25. Large Signal Pulse Response REV. 0 –200 253ns 200ns 1.253µs 100ns / DIV Figure 26. Small Signal Pulse Response –7– Figure 27. Power-Up/Down Response AD604 0 0 –10 500mV 100 90 –10 VGN = 2.9V –20 10 –20 CMRR – dB VGN2 = 2.9V CROSSTALK – dB VGN – Volts 2.9V VGN1 = 1V VOUT1 = 1V p-p VIN2 = GND –30 –40 VGN2 = 2.0V –30 VGN = 2.0V –40 –50 VGN2 = 1.5V 0% 0.1V 500mV –50 –60 100ns Figure 28. Gain Response 10M 1M FREQUENCY – Hz 100M Figure 29. Crosstalk (CH1 to CH2) vs. Frequency 1M –60 100k 27.6 40 27.4 35 100 10 SUPPLY CURRENT – mA INPUT BIAS CURRENT – µA 1k 27.2 27.0 26.8 26.6 26.4 26.2 26.0 10k 100k 1M FREQUENCY – Hz 10M 25.8 –40 100M Figure 31. Input Impedance vs. Frequency –20 20 0 60 40 TEMPERATURE – °C 80 90 Figure 32. Input Bias Current vs. Temperature 100M +IS (AD604) = +IS (PA) + +IS (DSX) – IS (AD604) = –IS (PA) 30 AD604 (+IS) 25 DSX (+IS) 20 15 10 PRE-AMP (±I S) 5 +IS (VGN = 0) 0 –40 –20 40 0 20 60 TEMPERATURE – °C 80 90 Figure 33. Supply Current (One Channel) vs. Temperature 20 18 16 DELAY – ns 1 1k 1M 10M FREQUENCY – Hz Figure 30. DSX Common-Mode Rejection vs. Frequency 100k 10k VGN = 0.1V VGN2 = 0.1V –70 100k INPUT IMPEDANCE – Ω VGN = 2.5V 14 VGN = 0.1V 12 10 VGN = 2.9V 8 6 100k 1M 10M FREQUENCY – Hz 100M Figure 34. Group Delay vs. Frequency –8– REV. 0 AD604 Since the two channels are identical, only Channel 1 will be used to describe their operation. VREF and VOCM are the only inputs that are shared by the two channels, and since they are normally ac grounds, crosstalk between the two channels is minimized. For highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accuracy 20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode the gain scaling will be determined by the midpoint between +VCC and GND, so care should be taken to control the supply voltage to +5 V. The input resistance looking into the VREF pin is 10 kΩ ± 20%. THEORY OF OPERATION The AD604 is a dual channel, variable gain amplifier with an ultralow noise preamplifier. Figure 35 shows the simplified block diagram of one channel. Each channel consists of: (1) a preamplifier with gain setting resistors R5, R6 and R7 (2) a single-supply X-AMP (hereafter called, DSX, Differential Single-supply X-AMP) made up of: (a) a precision passive attenuator (differential ladder) (b) a gain control block (c) a VOCM buffer with supply splitting resistors R3 and R4 The DSX portion of the AD604 is a single-supply circuit and the VOCM pin is used to establish the dc level of the midpoint of this portion of the circuit. VOCM needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (+5 V, GND); however, if the dc level of the output is important to the user (see APPLICATIONS section for AD9050 example), then VOCM can be specifically set. The input resistance looking into the VOCM pin is 45 kΩ ± 20%. (d) an Active Feedback Amplifier1 (AFA) with gain setting resistors R1 and R2 The preamplifier is powered by a ± 5 V supply, while the DSX uses a single +5 V supply. The linear-in-dB gain response of the AD604 can generally be described by Equation 1: G (dB) = (Gain Scaling (dB/V)) × (Gain Control (V )) + ((Preamp Gain (dB)) – 19 dB) (1) Preamplifier Each channel provides between 0 dB to +48.4 dB through +6 dB to +54.4 dB of gain depending on the user determined preamplifier gain. The center 40 dB of gain is exactly linear-in-dB while the gain error increases at the top and bottom of the range. The gain of the preamplifier is typically either +14 dB or +20 dB, but can be set to intermediate values by a single external resistor (see PREAMPLIFIER section for details). The gain of the DSX can vary from –14 dB to +34.4 dB which is determined by the gain control voltage (VGN). The VREF input establishes the gain scaling – the useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and 1.25 V respectively. For example, if the preamp gain was set to +14 dB and VREF was set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation would simplify to: The input capability of the following single-supply DSX (2.5 ± 2 V for a +5 V supply) limits the maximum input voltage of the preamplifier to ± 400 mV for the 14 dB gain configuration or ± 200 mV for the 20 dB gain configuration. The preamplifier’s gain can be programmed to +14 dB or +20 dB; by either shorting the FBK1 node to PAO1 (+14 dB), or leaving node FBK1 open (+20 dB). These two gain settings are very accurate since they are set by the ratio of on-chip resistors. Any intermediate gain can be achieved by connecting the appropriate resistor value between PAO1 and FBK1 according to Equations 2 and 3: G= G (dB) = (20 (dB/V )) × (VGN (V )) – 5 dB The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control voltage range of 0.1 V to 2.9 V. Maximum gain can be achieved at a VGN of 2.9 V. V OUT (R7iREXT ) + R5 + R6 = V IN R6 REXT = VREF VGN [R6 ×G −(R5 + R6)]× R7 R7 −(R6 ×G )+(R5 + R6) GAIN CONTROL PAI PAO R7 40Ω C1 +DSX 175Ω DISTRIBUTED GM EXT. FBK C2 DIFFERENTIAL ATTENUATOR –DSX G1 R5 32Ω Ao 175Ω VPOS R6 8Ω G2 R3 200kΩ COM R2 20Ω VOCM C3 EXT. R1 820Ω R4 200kΩ Figure 35. Simplified Block Diagram of a Single Channel of the AD604 1 To understand the active-feedback amplifier topology, refer to the AD830 data sheet. The AD830 is a practical implementation of the idea. REV. 0 –9– OUT (2) (3) AD604 Since the internal resistors have an absolute tolerance of ± 20%, the gain can be in error by as much as 0.33 dB when REXT is 30 Ω, where it was assumed that REXT is exact. To achieve its optimum specifications, power and ground management are critical to the AD604. Large dynamic currents result because of the low resistances needed for the desired noise performance. Most of the difficulty is with the very low gain setting resistors of the preamplifier that allow for a total input referred noise, including the DSX, as low as 0.8 nV/√Hz. The consequently large dynamic currents have to be carefully handled to maintain performance even at large signal levels. Figure 36 shows how the preamplifier is set to gains of +14, +17.5 and +20 dB. The gain range of a single channel of the AD604 is 0 dB to +48 dB when the preamplifier is set to +14 dB (Figure 36a), 3.5 dB to +51.5 dB for a preamp gain of +17.5 dB (Figure 36b), and 6 dB to 54 dB for the highest preamp gain of +20 dB (Figure 36c). To accommodate these large dynamic currents as well as a ground referenced input, the preamplifier is operated from a dual ± 5 V supply. This causes the preamplifiers output to also be ground referenced, which requires a common-mode level shift into the single-supply DSX. The two external coupling capacitors (C1, C2 in Figure 35) connected to nodes PAO1 and +DSX, and –DSX and ground, respectively, perform this function (see AC Coupling Section). In addition, they eliminate any offset that would otherwise be introduced by the preamplifier. It should be noted that an offset of 1 mV at the input of the DSX will get amplified by +34.4 dB (× 52.5) when the gain-control voltage is at its maximum, this equates to 52.5 mV at the output. AC coupling is consequently required to keep the offset from degrading the output signal range. PAI1 PAO1 R5 32Ω R6 8Ω R7 40Ω COM1 FBK1 a. Preamp Gain = 14 dB PAO1 PAI1 R10 40Ω R7 40Ω R5 32Ω R6 8Ω COM1 FBK1 b. Preamp Gain = 17.5 dB The internal feedback resistors setting the gain of the preamplifier are so small (nominally 8 Ω and 32 Ω) that even an additional 1 Ω in the “ground” connection at pin COM1, which serves as the input common-mode reference, will seriously degrade gain accuracy and noise performance. This node is very sensitive and careful attention is necessary to minimize the ground impedance. All connections to node COM1 should be as short as possible. PAI1 PAO1 R5 32Ω R6 8Ω R7 40Ω FBK1 COM1 c. Preamp Gain = 20 dB Figure 36. Preamplifier Gain Programmability For a preamplifier gain of +14 dB, the preamplifier’s –3 dB small-signal bandwidth is 130 MHz; when the gain is at the high end (+20 dB), the bandwidth will be reduced by a factor of two to 65 MHz. Figure 37 shows the ac responses for the three preamp gains discussed above; note that the gain for an REXT of 40 Ω should be 17.5 dB, but the mismatch between the internal resistors and the external resistor has caused the actual gain for this particular preamplifier to be 17.7 dB. The –3 dB small-signal bandwidth of one complete channel of the AD604 (preamplifier and DSX) is 40 MHz and is independent of gain. 20 OPEN 19 40Ω 18 GAIN – dB 16 15 SHORT 14 12 IN 150Ω VIN 50Ω 8Ω 32Ω 40Ω REXT 11 10 100k 1M REXT – Ω 10M The preamplifier can drive 40 Ω (the nominal feedback resistors) and the following 175 Ω ladder load of the DSX with low distortion. For example, at 10 MHz and ± 1 V at the output, the preamplifier has less than –45 dB of second and third harmonic distortion when driven from a low (25 Ω) source resistance. In some cases one may need more than 48 dB of gain range, in which case two AD604 channels could be cascaded. Since the preamplifier has limited input signal range, consumes over half (120 mW) of the total power (220 mW), and its ultralow noise is not necessary after the first AD604 channel, a shutdown mechanism that disables only the preamplifier is built in. All that is required to shut down the preamplifier is to tie the COM1 and/or COM2 pin to the positive supply. The DSX will be unaffected and can be used as before (see APPLICATIONS section for further details). 17 13 The preamplifier including the gain setting resistors has a noise performance of 0.71 nV/√Hz and 3 pA/√Hz. Note that a significant portion of the total input referred voltage noise is due to the feedback resistors. The equivalent noise resistance presented by R5 and R6 in parallel is nominally 6.4 Ω, which contributes 0.33 nV/√Hz to the total input referred voltage noise. The larger portion of the input referred voltage noise is coming from the amplifier with 0.63 nV/√Hz. The current noise is independent of gain and depends only on the bias current in the input stage of the preamplifier—it is 3 pA/√Hz. 100M Figure 37. AC Responses for Preamplifier Gains Shown in Figure 36. –10– REV. 0 AD604 1 –DSX1 VGN1 24 2 +DSX1 VREF 23 3 PAO1 OUT1 22 4 FBK1 GND1 21 5 PAI1 VPOS 20 6 COM1 VNEG 19 7 COM2 AD604 applied between nodes +DSX and –DSX will result in zero current into node MID, but a single-ended signal applied to either input +DSX or –DSX while the other input is ac grounded, will cause the current delivered by the source to flow into the VOCM buffer via node MID. VNEG 18 8 PAI2 VPOS 17 9 FBK2 GND2 16 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 13 Figure 38. Shutdown of Preamplifiers Only Differential Ladder (Attenuator) The attenuator before the fixed gain amplifier of the DSX is realized by a differential seven-stage R-1.5R resistive ladder network with an untrimmed input resistance of 175 Ω single-ended or 350 Ω differentially. The signal applied at the input of the ladder network (Figure 39) is attenuated by 6.908 dB per tap; thus, the attenuation at the first tap is 0 dB, at the second, 13.816 dB, and so on, all the way to the last tap where the attenuation is 48.356 dB. A unique circuit technique is used to interpolate continuously between the tap points, thereby providing continuous attenuation from 0 to –48.36 dB. You can think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer. Since the DSX is a single-supply circuit, some means of biasing its inputs must be provided. Node MID together with the VOCM buffer performs this function. Without internal biasing, the user would have had to dc bias the inputs externally. If not done carefully, the biasing network can introduce additional noise and offsets. By providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the DSX. It should be made clear again that the input to the DSX is still fully differential if driven differentially, i.e., pins +DSX and –DSX see the same signal but with opposite polarity (see Differential Input VGA Application). What changes is the load as seen by the driver; it is 175 Ω when each input is driven single ended, but 350 Ω when driven differentially. This can be easily explained when thinking of the ladder network as just two 175 Ω resistors connected back-to-back with the middle node, MID, being biased by the VOCM buffer. A differential signal R –6.908dB R –13.82dB R +DSX 1.5R 1.5R –20.72dB R The ladder resistor value of 175 Ω was chosen to provide the optimum balance between the load driving capability of the preamplifier and the noise contribution of the resistors. One feature of the X-AMP architecture is that the output referred noise is constant versus gain over most of the gain range. This can be easily explained by looking at Figure 39 and observing that the tap resistance is equal for all taps after only a few taps away from the inputs. The resistance seen looking into each tap is 54.4 Ω which makes 0.95 nV/√Hz of Johnson noise spectral density. Since there are two attenuators, the overall noise contribution of the ladder network is √2 times 0.95 nV/√Hz or 1.34 nV/√Hz, a large fraction of the total DSX noise. The rest of the DSX circuit components contribute another 1.20 nV/√Hz which together with the attenuator produces 1.8 nV/√Hz of total DSX input referred noise. AC Coupling As already mentioned, the DSX portion of the AD604 is a single-supply circuit and therefore its inputs need to be ac coupled to accommodate ground-based signals. External capacitors C1 and C2 in Figure 35 level shift the ground referenced preamplifier output from ground to the dc value established by VOCM (nominal 2.5 V). C1 and C2, together with the 175 Ω looking into each of DSX inputs (+DSX and –DSX), will act as high pass filters with corner frequencies depending on the values chosen for C1 and C2. For example, if C1 and C2 are 0.1 µF, then together with the 175 Ω input resistance seen into each side of the differential ladder of the DSX, a –3 dB high pass corner at 9.1 kHz is formed. If the AD604 output needs to be ground referenced, then another ac coupling capacitor will be required for level shifting. This capacitor will also eliminate any dc offsets contributed by the DSX. With a nominal load of 500 Ω and a 0.1 µF coupling capacitor, this adds a high pass filter with –3 dB corner frequency at about 3.2 kHz. The choice for all three of these coupling capacitors depends on the application. They should allow the signals of interest to pass unattenuated, while at the same time they can be used to limit the low frequency noise in the system. –27.63dB 1.5R R –34.54dB R 1.5R 1.5R –41.45dB R 1.5R –48.36dB 1.5R 175Ω 1.5R 175Ω MID 1.5R R R 1.5R R 1.5R 1.5R 1.5R R R 1.5R R –DSX NOTE: R = 96Ω 1.5R = 144Ω Figure 39. R–1.5R Dual Ladder Network. REV. 0 –11– R AD604 Gain Control Interface Active Feedback Amplifier (Fixed Gain Amp) The gain-control interface provides an input resistance of approximately 2 MΩ at Pin VGN1 and gain scaling factors from 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V respectively. The gain scales linearly-in-dB for the center 40 dB of gain range, that is for VGN equal to 0.4 V to 2.4 V for the 20 dB/V scale, and 0.2 V to 1.2 V for the 40 dB/V scale. Figure 40 shows the ideal gain curves for a nominal preamplifier gain of 14 dB which are described by the following equations: To achieve single supply operation and a fully differential input to the DSX, an active-feedback amplifier (AFA) is utilized. The AFA is basically an op amp with two gm stages; one of the active stages is used in the feedback path (therefore the name), while the other is used as a differential input. Note that the differential input is an open-loop gm stage that requires that it be highly linear over the expected input signal range. In this design, the gm stage that senses the voltages on the attenuator is a distributed one; for example, there are as many gm stages as there are taps on the ladder network. Only a few of them are on at any one time, depending on the gain-control voltage. G (20 dB/V) = 20 × VGN – 5, VREF = 2.500 V (4) G (30 dB/V) = 30 × VGN – 5, VREF = 1.666 V (5) G (40 dB/V) = 40 × VGN – 5, VREF = 1.250 V (6) 50 45 40 GAIN – dB 35 40dB/V 30dB/V 20dB/V 30 25 LINEAR-IN-dB RANGE OF AD604 WITH PREAMPLIFIER SET TO 14dB 20 15 The AFA makes a differential input structure possible since one of its inputs (G1) is fully differential; this input is made up of a distributed gm stage. The second input (G2) is used for feedback. The output of G1 will be some function of the voltages sensed on the attenuator taps which is applied to a high gain amplifier (A0). Because of negative feedback, the differential input to the high gain amplifier has to be zero; this in turn implies that the differential input voltage to G2 times gm2 (the transconductance of G2) has to be equal to the differential input voltage to G1 times gm1 (the transconductance of G1). Therefore the overall gain function of the AFA is: 10 V OUT g R1+ R2 = m1 × V ATTEN g m2 R2 5 0 0.5 –5 1.0 1.5 2.0 GAIN CONTROL VOLTAGE – VGN 2.5 where VOUT is the output voltage, VATTEN is the effective voltage sensed on the attenuator, (R1+R2)/R2 = 42, and gm1/gm2 = 1.25; the overall gain is thus 52.5 (34.4 dB). 3.0 Figure 40. Ideal Gain Curves vs. VREF. From these equations you can see that all gain curves intercept at the same –5 dB point; this intercept will be 6 dB higher (+1 dB) if the preamplifier gain is set to +20 dB or 14 dB, lower (–19 dB) if the preamplifier is not used at all. Outside of the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 dB of range. For a given gain scaling you can calculate VREF as shown in Equation 7: V REF = 2.500 V × 20 dB / V Gain Scale (8) (7) Usable gain control voltage ranges are 0.1 V to 2.9 V for 20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN voltages of less than 0.1 V are not used for gain control since below 50 mV the channel (preamp and DSX) is powered down. This can be used to conserve power and at the same time gateoff the signal. The supply current for a powered-down channel is 1.9 mA, the response time to power the device on-or-off, is less than 1 µs. The AFA has additional features: (1) inverting the signal by switching the positive and negative input to the ladder network, (2) the possibility of using the DSX1 input as a second signal input, (3) fully differential high impedance inputs when both preamplifiers are used with one DSX (the other DSX could still be used alone), and (4) independent control of the DSX commonmode voltage. Under normal operating conditions it is best to connect a decoupling capacitor to pin VOCM in which case the common-mode voltage of the DSX is half the supply voltage; this allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew-rate of the VOCM buffer. If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again this is done for level shifting and to eliminate any dc offsets contributed by the DSX (see AC Coupling section). –12– REV. 0 AD604 APPLICATIONS The most basic circuit in Figure 41 shows the connections for one channel of the AD604. The signal is applied at Pin 5. RGN is normally zero, in which case the preamplifier is set to a gainof-five (14 dB). When Pin FBK1 is left open, the preamplifier is set to a gain-of-ten (20 dB) and the gain range shifts up by 6 dB. The ac coupling capacitors before pins –DSX1 and +DSX1 should be selected according to the required lower cutoff frequency. In this example the 0.1 µF capacitors together with the 175 Ω seen looking into each of the DSX input pins, provides a –3 dB high pass corner of about 9.1 kHz. The upper cutoff frequency is determined by the bandwidth of the channel which is 40 MHz. Note, the signal can be simply inverted by connecting the output of the preamplifier to pin –DSX1 instead of +DSX1, this is due to the fully differential input of the DSX. 0.1µF 0.1µF RGN VIN 1 –DSX1 VGN1 24 2 +DSX1 VREF 23 3 PAO1 OUT1 22 4 FBK1 GND1 21 5 PAI1 6 COM1 VNEG 19 +5V 7 COM2 VNEG 18 –5V AD604 VGN 0.1µF OUT RL 500Ω VPOS 20 8 PAI2 VPOS 17 9 FBK2 GND2 16 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 13 2.500V Pin VREF requires a voltage of 1.25 V to 2.5 V, with between 40 dB/V and 20 dB/V gain scaling respectively. Voltage VGN controls the gain; its nominal operating range is from 0.25 V to 2.65 V for 20 dB/V gain scaling, and 0.125 V to 1.325 V for 40 dB/V scaling. When this pin is taken to ground, the channel will power down and disable its output. Pin COM1 is the main signal ground for the preamplifier and needs to be connected with as short a connection as possible to the input ground. Since the internal feedback resistors of the preamplifier are very small for noise reasons (8 Ω and 32 Ω nominally), it is of utmost importance to keep the resistance in this connection to a minimum! Furthermore, excessive inductance in this connection may lead to oscillations. As a consequence of the AD604’s ultralow noise and wide bandwidth, large dynamic currents will be flowing to and from the power supply. To insure the stability of the part, extreme attention to supply decoupling is required. A large storage capacitor in parallel with a smaller high frequency capacitor connected right at the supply pins, together with a ferrite bead coming from the supply should be used to insure high frequency stability. To provide for additional flexibility, Pin COM1 can be used to depower the preamplifier. When COM1 is connected to VP, the preamplifier will be off, yet the DSX portion can be used independently. This may be of value when one desires to cascade the two DSX stages in the AD604. In this case the first DSX output signal with respect to noise will be large and using the second preamplifier at this point would be a waste of power (see AGC Amplifier Application). 0.1µF An Ultralow Noise AGC Amplifier with 82 to 96 dB Gain Range Figure 41. Basic Connections for a Single Channel Figure 42 shows an implementation of an AGC amplifier with 82 dB of gain range using a single AD604. First, the connections for the two channels of the AD604 will be discussed, and second, how the detector circuitry that closes the loop works. As shown here, the output is ac coupled for optimum performance. In the case of connecting to the AD9050, ac coupling can be eliminated as long as pin VOCM is biased by the same 3.3 V common-mode voltage as the AD9050 (see Figure 50). C1 0.1µF C2 0.1µF VIN (MAX 800mV p-p) 1 –DSX1 VGN1 24 2 +DSX1 VREF 23 VREF AD604 R1 49.9Ω 3 PAO1 OUT1 22 4 FBK1 GND1 21 5 PAI1 VPOS 20 6 COM1 VNEG 19 VSET (<0V) +5V R8 2kΩ –5V 7 COM2 VNEG 18 –5V 8 PAI2 VPOS 17 +5V 9 FBK2 GND2 16 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 13 – R4 2kΩ C8 0.33µF LOW PASS FILTER 1V +5V C3 0.1µF V1 = VIN * G C7 0.33µF C7 0.1µF 8 7 6 5 X1 X2 VP W R3 1kΩ R2 453Ω Y2 VN Z 1 2 3 4 –5V RF OUT C12 0.1µF C13 0.1µF +5V FB –5V C9 0.33µF R5 2kΩ ALL SUPPLY PINS ARE DECOUPLED AS SHOWN. Figure 42. AGC Amplifier with 82 dB of Gain Range REV. 0 –13– NC 8 +VS 7 +5V AD711 –5V 3 OUT 6 4 OFFS NULL 5 – (A)2 R6 2kΩ OFFS NULL 2 2 C4 0.1µF FB C10 1µF Y1 1 R7 1kΩ AD835 C6 0.56µF C11 1µF (V1)2 –VS IF V1 = A*cos (wt) VG AD604 The signal is applied to connector VIN, and since the signal source was 50 Ω, a terminating resistor (R1) of 50 Ω was added. The signal is then amplified by 14 dB (Pin FBK1 shorted to PAO1) through the Channel 1 preamplifier, and is further processed by the Channel 1 DSX. Next the signal is applied directly to the Channel 2 DSX. The second preamplifier is powered down by connecting its COM2 pin to the positive supply as explained in the preamplifier section earlier. Capacitors C1 and C2 level shift the signal from the preamplifier into the first DSX and at the same time eliminate any offset contribution of the preamp. C3 and C4 have the same offset cancellation purpose for the second DSX. Each set of capacitors together with the 175 Ω input resistance of the corresponding DSX provides a high pass filter with –3 dB corner frequency of about 9.1 kHz. Pin VOCM is decoupled to ground by a 0.1 µF capacitor, while VREF can be externally provided; in this application the gain scale is set to 20 dB/V by applying 2.500 V. Since each of the DSX amplifiers operates from a single +5 V supply, the output is ac coupled via C6 and C7. The output signal can be monitored at the connector labeled RF OUT. Figures 43 and 44 show the gain range and gain error for the AD604 connected as shown. The gain range is –14 dB to +82 dB; the useful range is 0 dB to +82 dB if the RF output amplitude is controlled to ± 400 mV (+2 dBm). The main limitation on the lower end of the signal range is the input capability of the 90 80 f = 1MHz 70 60 GAIN – dB 50 40 30 20 10 0 –10 –20 –30 0.1 0.5 0.9 1.3 1.7 VGN – Volts 2.1 2.5 2.9 Figure 43. AD604 Cascaded Gain vs. VGN 4 f = 1MHz 3 GAIN ERROR – dB 2 1 0 –1 –2 –3 –4 0.2 0.7 1.2 1.7 VGN – Volts 2.2 2.7 Figure 44. AD604 Cascaded Gain Error vs. VGN preamplifier. This can be overcome by adding an attenuator in front of the preamplifier, but that would defeat the advantage of the ultralow noise preamplifier. It should be noted that the second preamplifier is not used since its ultralow noise and the associated high power consumption are overkill after the first DSX stage. It is disabled in this application by connecting the COM2 pin to the positive supply. Nevertheless, the second preamplifier can be used if so desired and the useful gain range will shift up by 14 dB, to encompass 0 dB to +96 dB of gain. For the same +2 dBm output this would allow signals as small as –94 dBm to be measured. To achieve the highest gains, the input signal has to ultimately be bandlimited to reduce the noise; this is especially true if the second preamplifier is used. If the maximum signal at Pin OUT2 of the AD604 is limited to be ± 400 mV (+2 dBm), then the input signal level at the AGC threshold is 25 µV rms (–79 dBm). The circuit as shown has about 40 MHz of noise bandwidth; the 0.8 nV/√Hz of input referred voltage noise spectral density of the AD604 results in an rms noise of 5.05 µV in the 40 MHz bandwidth. The 50 Ω termination resistor, together with the 50 Ω source resistance of the signal generator, combine to an effective resistance as seen by the input of the preamplifier of 25 Ω which makes 4.07 µV of rms noise in 40 MHz. The noise floor of this channel is consequently the rms sum of these two main noise sources, 6.5 µV rms. This means that the minimum dectectable signal (MDS) for this circuit is 6.5 µV rms (–90.7 dBm). As a general rule of thumb the measured signal should be about a factor-of-three larger than the noise floor, in this case 19.5 µV rms. As we can see the 25 µV rms signal that this AGC circuit can correct for is just slightly above the MDS. Of course, the sensitivity of the input can be improved by bandlimiting the signal; if the noise bandwidth is reduced by a factor-of-four to 10 MHz, the noise floor of the AGC circuit with 50 Ω termination resistor will drop to 3.25 µV rms (–96.7 dBm). Further noise improvement can be achieved by an input matching network or by transformer coupling of the input signal. Next we will describe the functioning of the detector circuitry comprised of a squarer, a low-pass filter, and an integrator. At this point it is necessary to make some assumptions about the input signal. The following explanation of the detector circuitry presumes an amplitude modulated RF carrier where the modulating signal is at a much lower frequency than the RF signal. The AD835 multiplier functions as the detector by squaring the output signal presented to it by the AD604. A low-pass filter following the squaring operation removes the RF signal component at twice the incoming signal frequency, while passing the low frequency AM information. The following integrator with a time constant of 2 ms set by R8 and C11 integrates the error signal presented by the low-pass filter and changes VG until the error signal is equal to VSET. For example, if the signal presented to the detector is V1 = A*cos(ωt) as indicated in Figure 42, then the output of the squarer is –(V1)2/1 V. The reason for all the minus signs in the detection circuitry comes from the necessity of providing negative feedback in the control loop; actually if VSET becomes greater-than 0 V, the control loop provides positive feedback. Squaring A*cos(ωt) results in two terms, one at dc and one at 2ω; the following low-pass filter passes only the –(A)2/2 dc term. –14– REV. 0 AD604 This dc voltage will now be forced equal to the voltage, VSET, by the control loop. The squarer together with the low-pass filter functions as a mean-square detector. As should be evident, by controlling the value of VSET, we can set the amplitude of the voltage V1 at the input of the AD835; if VSET equals minus 80 mV, the AGC output signal amplitude will be ± 400 mV. Figure 45 shows the control voltage, VGN, versus the input power at frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at an output regulated level of +2 dBm (800 mV p-p). The AGC threshold is evident at a PIN of about –79 dBm; the highest input power that could still be accommodated was about +3 dBm. At this level the output starts being distorted because of clipping in the preamplifier. C6 560pF R2 499Ω C3 0.1µF C5 0.1µF 1 –DSX1 VGN1 24 2 +DSX1 VREF 23 3 PAO1 OUT1 22 4 FBK1 GND1 21 5 PAI1 6 COM1 VNEG 19 7 COM2 VNEG 18 AD604 VPOS 20 8 PAI2 VPOS 17 9 FBK2 GND2 16 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 13 FB FAIR-RITE #2643000301 4.5 Figure 46. Modifications of AGC Amplifier to Get 96 dB of Gain Range 3.5 3.0 4.5 2.5 4.0 2.0 10MHz 1MHz CONTROL VOLTAGE – Volts CONTROL VOLTAGE – Volts 4.0 1.5 1.0 0.5 –80 –70 –60 –50 –40 –30 PIN – dBm –20 –10 0 10 Figure 45. Control Voltage vs. Input Power of Circuit in Figure 42 3.0 2.5 1MHz 2.0 1.5 1.0 0.5 As mentioned already, the second preamplifier can be used to extend the range of the AGC circuit in Figure 42. Figure 46 shows the modifications that need to be made to Figure 44 to achieve 96 dB of gain and dynamic range. Because of the extremely high gain, the bandwidth needs to be limited to reject some of the noise; furthermore, limiting the bandwidth will help suppress high frequency oscillations. The added components act as a low-pass filter and dc block (C5 level shifts the output of the first DSX from 2.5 V to ground); the ferrite bead has an impedance of about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz. Together with R2 and C6, the bead makes a low-pass filter which attenuates higher frequencies; at 1 MHz the attenuation is about –0.2 dB, while at 10 MHz it increases to –6 dB, on to –28 dB at 100 MHz. Signals now have to be less than about 1 MHz to not be significantly affected by the added circuitry. In Figure 47 we see the control voltage vs. input power at 1 MHz to the circuit in Figure 46; note that the AGC threshold is at –95 dBm. The output signal level was set to 800 mV p-p by applying –80 mV to the VSET connector. REV. 0 3.5 0 –100 –90 –80 –70 –60 –50 –40 –30 PIN – dBm –20 –10 0 10 Figure 47. Control Voltage vs. Input Power of Circuit in Figure 46 –15– AD604 plug-in. R1 and R2 were inserted to insure a nominal load of 500 Ω at each output. The differential gain of the circuit was set to +20 dB by applying a control voltage, VGN, of 1 V; the gain scaling was 20 dB/V for a VREF of 2.500 V; the input frequency was 10 MHz and the differential input amplitude 100 mV p-p. The resulting differential output amplitude was 1 V p-p as can be seen on the scope photo when reading the vertical scale as 200 mV/div. Ultralow Noise, Differential Input-Differential Output VGA Figure 48 shows how to use both preamplifiers and DSXs to create a high impedance, differential input-differential output variable gain amplifier. This application takes advantage of the differential inputs to the DSXs. It should be pointed out that the input is not truly differential, in the sense that the commonmode voltage needs to be at ground to achieve maximum input signal swing. This has mainly to do with the limited output swing capability of the output drivers of the preamplifiers; they clip around ± 2.2 V due to having to drive an effective load of about 30 Ω. If a different input common-mode voltage needs to be accommodated, ac coupling (as was done in Figure 46) is recommended. The differential gain range of this circuit runs from +6 dB to +54 dB. This is 6 dB higher than each individual channel of the AD604 because the DSX inputs now see twice the signal amplitude compared to when they are driven single ended. 20mV 20ns ACTUAL VOUT +500mV 100 90 10 –500mV 0% 20mV C1 0.1µF C2 0.1µF VIN+ VGN1 24 2 +DSX1 VREF 23 3 PAO1 OUT1 22 4 FBK1 GND1 21 5 PAI1 VPOS 20 6 COM1 VNEG 19 –5V 7 COM2 VNEG 18 –5V 8 PAI2 VPOS 17 +5V 9 FBK2 GND2 16 AD604 VIN– C4 0.1µF 1 –DSX1 C3 0.1µF 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 13 VREF NOTE 1. OUTPUT AFTER 10x ATTENUATER FORMED BY 453Ω TOGETHER WITH 50Ω OF 7A24 PLUG-IN. VOUT+ C7 0.1µF R1 453Ω Figure 49. Output of VGA in Figure 48 for VG = 1 V +5V Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40 MSPS A/D C6 0.1µF The AD604 is an ideal candidate for the TGC (Time Gain Control) amplifier that is required in medical ultrasound systems to limit the dynamic range of the signal that is presented to the A/D converter. Figure 50 shows a schematic of an AD604 driving an AD9050 in a typical medical ultrasound application. R2 453Ω VOUT– VG C5 0.1µF C12 0.1µF C13 0.1µF FB +5V FB –5V The gain is controlled by means of a digital byte that is input to an AD7226 D/A converter that outputs the analog gain control signal. The output common-mode voltage of the AD604 is set to VPOS/2 by means of an internal voltage divider. The VOCM pin is bypassed with a 0.1 µF to ground. ALL SUPPLY PINS ARE DECOUPLED AS SHOWN. Figure 48. Ultralow Noise, Differential Input–Differential Output VGA Figure 49 displays the output signals VOUT+ and VOUT– after a –20 dB attenuator formed between the 453 Ω resistors shown in Figure 48 and the 50 Ω loads presented by the oscilloscope The DSX output is optionally filtered and then buffered by an AD9631 op amp, a low distortion, low noise amplifier. The op amp output is ac coupled into the self-biasing input of an AD9050 A/D converter which is capable of outputting 10 bits at a 40 MSPS sampling rate. –16– REV. 0 AD604 0.1µF J2 ANALOG INPUT 50Ω 50Ω 0.1µF (MSB) D9 15 0.1µF 0.1µF 1 –DSX1 VGN1 24 2 +DSX1 VREF 23 3 PAO1 OUT1 22 4 FBK1 GND1 21 5 PAI1 VPOS 20 6 COM1 VNEG 19 7 COM2 VNEG 18 8 PAI2 VPOS 17 9 FBK2 GND2 16 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 13 AD604 0.1µF AD9050 1kΩ FILTER AD9631 2 3 OUT 6 0.1µF D7 17 4 VREFIN D6 18 5 COMP D5 19 6 REFBP D4 24 9 AINB D3 25 10 AIN +IN D1 27 (LSB) D0 28 OPTIONAL +5V 20 0.1µF +5V 22 CLK VOUTB VOUTC 20 VOUTA VOUTD 19 3 VSS 4 VREF +15V VDD 18 AD7226 0.1µF 0.1µF 0.1µF 2 A/D OUTPUT D2 26 13 ENCODE 1kΩ 1 A0 17 5 AGND A1 16 6 8 DGND DB7 (MSB) DB6 WR 15 DB0 14 (LSB) DB1 13 9 DB5 DB2 12 10 DB4 DB3 11 7 –IN VREFOUT 14 OR 100Ω VREF 1kΩ D8 16 3 DIGITAL GAIN CONTROL Figure 50. TGC Circuit for Medical Ultrasound Application C3 0.1µF C1 0.1µF PAO1 NOTE 2 R2 RGN –DSX1 VGN1 24 2 +DSX1 VREF 23 3 PAO1 OUT1 22 GND1 21 4 FBK1 AD604 IN1 IN2 PAO2 R3 RGN C6 0.1µF HP3577B VG1 1 20 5 PAI1 VPOS 6 COM1 VNEG 19 7 COM2 VNEG 18 8 PAI2 VPOS 17 9 FBK2 GND2 16 10 PAO2 OUT2 15 11 +DSX2 VOCM 14 12 –DSX2 VGN2 OUT A HP11636B C4 0.1µF C2 5pF C12 0.1µF R1 500Ω POWER SPLITTER OUT1 50Ω PAI NOTE 3 OPTIONAL C11 0.1µF 0.1µF AD604 450Ω DUT 49.9Ω +5V –5V C10 0.1µF Figure 52. Setup for Gain Measurements C9 0.1µF C8 5pF C7 0.1µF NOTE 3 R4 500Ω OUT2 VOCM 13 C5 0.1µF VG2 NOTES: 1. PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS. 2. RGN = 0 NOMINALLY; PREAMP GAIN = 5, RGN = OPEN; PREAMP GAIN = 10 3. WHEN MEASURING BW WITH 50Ω SPECTRUM ANALYZER, USE 450Ω IN SERIES. Figure 51. Basic Test Board REV. 0 R VREF –17– AD604 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP Package (N-24) Small Outline IC Package (R-24) 1.275 (32.30) 1.125 (28.60) 0.6141 (15.60) 0.5985 (15.20) 13 1 12 PIN 1 0.210 (5.33) MAX 0.0291 (0.74) x 45° 0.0098 (0.25) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) MIN 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) SEATING PLANE 0.045 (1.15) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.0500 (1.27) 0.0157 (0.40) 8° 0.0192 (0.49) 0° SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) Shrink Small Outline Package (RS-24) 0.328 (8.33) 0.318 (8.08) 24 13 1 12 0.311 (7.9) 0.301 (7.64) 0.0500 (1.27) BSC 0.060 (1.52) 0.015 (0.38) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.280 (7.11) 0.240 (6.10) 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.212 (5.38) 0.205 (5.207) 12 0.4193 (10.65) 0.3937 (10.00) 1 0.0118 (0.30) 0.0040 (0.10) 24 13 0.2992 (7.60) 0.2914 (7.40) 24 0.07 (1.78) 0.066 (1.67) 8° 0.015 (0.38) 0° SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) –18– 0.037 (0.94) 0.022 (0.559) REV. 0 –19– –20– PRINTED IN U.S.A. C2190–9–10/96