Dual IF Receiver AD6643 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0± D10± OEB REFERENCE CLOCK DIVIDER SYNC PDWN SERIAL PORT SCLK SDIO CSB CLK+ CLK– NOTES 1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A AND CHANNEL B LVDS OUTPUT DATA. 09638-001 Performance with NSR enabled SNR: 76.1 dBFS in a 40 MHz band to 90 MHz at 185 MSPS SNR: 73.6 dBFS in a 60 MHz band to 90 MHz at 185 MSPS Performance with NSR disabled SNR: 66.5 dBFS up to 90 MHz at 185 MSPS SFDR: 88 dBc up to 185 MHz at 185 MSPS Total power consumption: 706 mW at 200 MSPS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) Differential analog inputs with 400 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes User-configurable, built-in self test (BIST) capability Figure 1. APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios GENERAL DESCRIPTION The AD6643 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multiantenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. (continued on Page 3) Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD6643 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 21 Applications....................................................................................... 1 Clock Input Considerations...................................................... 21 General Description ......................................................................... 1 Power Dissipation and Standby Mode .................................... 22 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 23 Revision History ............................................................................... 2 Noise Shaping Requantizer (NSR) ............................................... 24 Product Highlights ........................................................................... 3 22% BW Mode (>40 MHz at 184.32 MSPS)........................... 24 Specifications..................................................................................... 4 33% BW Mode (>60 MHz at 184.32 MSPS)........................... 25 ADC DC Specifications................................................................. 4 Channel/Chip Synchronization.................................................... 26 ADC AC Specifications ................................................................. 5 Serial Port Interface (SPI).............................................................. 27 Digital Specifications ..................................................................... 6 Configuration Using the SPI..................................................... 27 Switching Specifications ................................................................ 8 Hardware Interface..................................................................... 27 Timing Specifications .................................................................. 8 SPI Accessible Features.............................................................. 28 Absolute Maximum Ratings.......................................................... 10 Memory Map .................................................................................. 29 Thermal Characteristics ............................................................ 10 Reading the Memory Map Register Table............................... 29 ESD Caution................................................................................ 10 Memory Map Register Table..................................................... 30 Pin Configurations and Function Descriptions ......................... 11 Memory Map Register Description ......................................... 32 Typical Performance Characteristics ........................................... 15 Applications Information .............................................................. 34 Equivalent Circuits ......................................................................... 18 Design Guidelines ...................................................................... 34 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 35 ADC Architecture ...................................................................... 19 Ordering Guide .......................................................................... 35 Analog Input Considerations.................................................... 19 REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD6643 When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required. After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are LVDS and support ANSI-644 levels. The AD6643 is available in a Pb-free, RoHS compliant, 64-lead, 9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. The AD6643 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing. 3. 4. 5. 6. Rev. 0 | Page 3 of 36 Two ADCs are contained in a small, space-saving, 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. LVDS digital output interface configured for low cost FPGA families. Operation from a single 1.8 V supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. AD6643 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span Input Capacitance 2 Input Resistance 3 Input Common-Mode Voltage POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 POWER CONSUMPTION Sine Wave Input1 (DRVDD = 1.8 V) Standby Power 4 Power-Down Power Temperature Full Min 11 Full Full Full Full Full Typ Max Unit Bits ±10 +2/−6 ±0.25 ±0.25 mV % FSR LSB LSB ±13 −2/+3.5 mV % FSR Guaranteed ±0.1 ±0.2 25°C 25°C Full Full ±15 ±50 ppm/°C ppm/°C 25°C 0.614 LSB rms Full Full Full Full 1.75 2.5 20 0.9 V p-p pF kΩ V Full Full 1.8 1.8 1.9 1.9 V V Full Full 238 154 260 215 mA mA Full Full Full 706 90 10 855 mW mW mW 1 1.7 1.7 Measured using a 10 MHz, 0 dBFS sine wave, and 100 Ω termination on each LVDS output pair. Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured using a dc input and the CLK± pins inactive (set to AVDD or AGND). 2 Rev. 0 | Page 4 of 36 AD6643 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR) NSR Disabled fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz NSR Enabled 22% BW Mode fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz 33% BW Mode fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz Temperature 25°C 25°C Full 25°C 25°C 25°C Min Typ Max 66.6 66.5 Unit 66.4 66.2 66.0 dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 76.1 75.5 74.7 74.2 dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 73.6 73.1 72.6 72.1 dBFS dBFS dBFS dBFS 25°C 25°C Full 25°C 25°C 25°C 65.6 65.5 dBFS dBFS dBFS dBFS dBFS dBFS 66.2 65.1 65.3 65.1 64.9 25°C 25°C Full 25°C 25°C 25°C −92 −91 25°C 25°C Full 25°C 25°C 25°C 92 91 25°C 25°C Full 25°C 25°C 25°C Rev. 0 | Page 5 of 36 −80 −88 −88 −84 dBc dBc dBc dBc dBc dBc 80 88 88 84 −94 −94 −80 −95 −94 −93 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD6643 Parameter 1 TWO TONE SFDR fIN = 184.12 MHz, 187.12 MHz (−7 dBFS) CROSSTALK 2 FULL POWER BANDWIDTH 3 NOISE BANDWIDTH 4 Temperature Min Typ Max Unit 25°C Full 88 95 dBc dB 25°C 25°C 400 1000 MHz MHz 1 For a complete set of definitions, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. 3 Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved. 4 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and it is not attenuated internally. 2 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, default SPI, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range Input Current Level High Low Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range Input Voltage Level High Low Input Current Level High Low Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 Input Voltage Level High Low Input Current Level High Low Input Resistance Input Capacitance LOGIC INPUT (SCLK) 2 Input Voltage Level High Low Temperature Min Full Full Full Full CMOS/LVDS/LVPECL 0.9 0.3 3.6 AGND AVDD 0.9 1.4 Full Full Full Full Typ 10 −22 8 Max 22 −10 4 10 Unit V V p-p V V 12 μA μA pF kΩ CMOS/LVDS 0.9 Full Full AGND AVDD V V Full Full 1.2 AGND AVDD 0.6 V V Full Full Full Full −5 −100 +5 +100 20 μA μA pF kΩ Full Full 1.22 0 2.1 0.6 V V Full Full Full Full −5 −80 +5 −45 μA μA kΩ pF Full Full 1.22 0 2.1 0.6 V V Rev. 0 | Page 6 of 36 12 1 16 26 2 AD6643 Parameter Input Current Level High Low Input Resistance Input Capacitance LOGIC INPUTS (SDIO)1 Input Voltage Level High Low Input Current Level High Low Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)2 Input Voltage Level High Low Input Current Level High Low Input Resistance Input Capacitance DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD) ANSI Mode Reduced Swing Mode Output Offset Voltage (VOS) ANSI Mode Reduced Swing Mode 1 2 Temperature Min Full Full Full Full 45 −5 Full Full Max Unit 70 +5 μA μA kΩ pF 1.22 0 2.1 0.6 V V Full Full Full Full 45 −5 70 +5 μA μA kΩ pF Full Full 1.22 0 2.1 0.6 V V Full Full Full Full 45 −5 70 +5 μA μA kΩ pF Full Full 250 150 350 200 450 280 mV mV Full Full 1.15 1.15 1.25 1.25 1.35 1.35 V V Pull up. Pull down. Rev. 0 | Page 7 of 36 Typ 26 2 26 5 26 5 AD6643 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Period—Divide-by-1 Mode 2 CLK Pulse Width High2 Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, OR) LVDS Mode Data Propagation Delay2 DCO Propagation Delay2 DCO to Data Skew2 Pipeline Delay (Latency) NSR Enabled Aperture Delay 4 Aperture Uncertainty (Jitter)4 Wake-Up Time (from Standby) Wake-Up Time (from Power-Down) OUT-OF-RANGE RECOVERY TIME Symbol tCLK tCH tPD tDCO tSKEW tA tJ Temperature Min Full Full Full 40 4.0 Full Full Full 2.25 2.375 0.8 Full Full Full Full Full Full Full Full Full Full 0.1 Typ 2.5 2.5 4.8 5.5 0.7 10 13 1.0 0.1 10 250 3 Max Unit 625 200 MHz MSPS ns 2.75 2.625 ns ns ns 1.3 ns ns ns Cycles 3 Cycles3 ns ps rms μs μs Cycles 1 Conversion rate is the clock rate after the divider. See Figure 2 for timing diagram. Cycles refers to ADC input sample rate cycles. 4 Not shown in timing diagrams. 2 3 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Conditions See Figure 3 for timing details SYNC to the rising edge of CLK setup time SYNC to the rising edge of CLK hold time See Figure 45 for SPI timing diagram Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 45) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 45) Rev. 0 | Page 8 of 36 Min Typ 0.3 0.4 Max Unit ns ns 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns AD6643 Timing Diagrams tA N–1 N+4 N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCO– DCO+ tSKEW PARALLEL INTERLEAVED D0 (LSB) CH A N – 10 CH B N – 10 CH A N–9 CH B N–9 CH A N–8 CH B N–8 CH A N–7 CH B N–7 CH A N–6 D11 (MSB) CH A N – 10 CH B N – 10 CH A N–9 CH B N–9 CH A N–8 CH B N–8 CH A N–7 CH B N–7 CH A N–6 CHANNEL MULTIPLEXED 0/D0± (EVEN/ODD) MODE (LSB) CH A0 N – 10 CH A1 N – 10 CH A0 N–9 CH A1 N–9 CH A0 N–8 CH A1 N–8 CH A0 N–7 CH A1 N–7 CH A0 N–6 D9/D10± (MSB) CH A10 N – 10 CH A11 N – 10 CH A10 N–9 CH A11 N–9 CH A10 N–8 CH A11 N–8 CH A10 N–7 CH A11 N–7 CH A10 N–6 CHANNEL MULTIPLEXED 0/D0± (EVEN/ODD) MODE (LSB) CH B0 N – 10 CH B1 N – 10 CH B0 N–9 CH B1 N–9 CH B0 N–8 CH B1 N–8 CH B0 N–7 CH B1 N–7 CH B0 N–6 CH B10 N – 10 CH B11 N – 10 CH B10 N–9 CH B11 N–9 CH B10 N–8 CH B11 N–8 CH B10 N–7 CH B11 N–7 CH B10 N–6 CHANNEL A AND CHANNEL B CHANNEL A CHANNEL B . . . . . . . . . D9/D10± (MSB) Figure 2. LVDS Modes for Data Output Timing Latency, NSR Disabled (Enabling NSR Adds an Additional Three Clock Cycles of Latency) CLK+ tHSYNC 09638-003 tSSYNC SYNC Figure 3. SYNC Timing Inputs Rev. 0 | Page 9 of 36 09638-002 tPD AD6643 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND PDWN to AGND OR+/OR− to AGND D0−/D0+ Through D10−/D10+ to AGND DCO+/DCO− to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the printed circuit board (PCB) increases the reliability of the solder joints, maximizing the thermal capability of the package. Typical θJA is specified for a 4-layer PCB that uses a solid ground plane. As listed in Table 7, airflow increases heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. Table 7. Thermal Resistance Package Type 64-Lead LFCSP 9 mm × 9 mm (CP-64-4) 1 Airflow Velocity (m/sec) 0 1.0 2.0 θJA1, 2 26.8 21.6 20.2 θJC1, 3 1.14 θJB1, 4 10.4 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 −40°C to +85°C 150°C ESD CAUTION −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 10 of 36 Unit °C/W °C/W °C/W AD6643 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD DNC VCM DNC DNC AVDD AVDD VIN–A VIN+A AVDD AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD6643 INTERLEAVED PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK SDIO OR+ OR– D10+ (MSB) D10– (MSB) D9+ D9– DRVDD D8+ D8– D7+ D7– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 09638-004 D1– D1+ DRVDD D2– D2+ D3– D3+ DCO– DCO+ D4– D4+ DRVDD D5– D5+ D6– D6+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC DNC DNC DNC DNC DNC DNC DRVDD DNC DNC DNC DNC D0– (LSB) D0+ (LSB) Figure 4. Pin Configuration (Top View), LFCSP Interleaved Parallel LVDS Table 8. Pin Function Descriptions for the Interleaved Parallel LVDS Mode Pin No. ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 4 to 9, 11 to 14, 55, 56, 58 0 ADC Analog 51 52 62 61 57 1 2 Digital Input 3 Digital Outputs 15 16 18 17 21 20 23 22 Mnemonic Type Description DRVDD AVDD DNC AGND, Exposed Paddle Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Do Not Connect. Do not connect to these pins. Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the device. This exposed paddle must be connected to ground for proper operation. VIN+A VIN−A VIN+B VIN−B VCM Input Input Input Input Output CLK+ CLK− Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. ADC Clock Input—True. ADC Clock Input—Complement. SYNC Input Digital Synchronization Pin. Slave mode only. D0− (LSB) D0+ (LSB) D1+ D1− D2+ D2− D3+ D3− Output Output Output Output Output Output Output Output Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Channel A/Channel B LVDS Output Data 2—True. Channel A/Channel B LVDS Output Data 2—Complement. Channel A/Channel B LVDS Output Data 3—True. Channel A/Channel B LVDS Output Data 3—Complement. Ground Rev. 0 | Page 11 of 36 AD6643 Pin No. 27 26 30 29 32 31 34 33 36 35 39 38 41 40 43 42 25 24 SPI Control 45 44 46 Output Enable and Power-Down 47 48 Mnemonic D4+ D4− D5+ D5− D6+ D6− D7+ D7− D8+ D8− D9+ D9− D10+ (MSB) D10− (MSB) OR+ OR− DCO+ DCO− Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Description Channel A/Channel B LVDS Output Data 4—True. Channel A/Channel B LVDS Output Data 4—Complement. Channel A/Channel B LVDS Output Data 5—True. Channel A/Channel B LVDS Output Data 5—Complement. Channel A/Channel B LVDS Output Data 6—True. Channel A/Channel B LVDS Output Data 6—Complement. Channel A/Channel B LVDS Output Data 7—True. Channel A/Channel B LVDS Output Data 7—Complement. Channel A/Channel B LVDS Output Data 8—True. Channel A/Channel B LVDS Output Data 8—Complement. Channel A/Channel B LVDS Output Data 9—True. Channel A/Channel B LVDS Output Data 9—Complement. Channel A/Channel B LVDS Output Data 10—True. Channel A/Channel B LVDS Output Data 10—Complement. Channel A/Channel B LVDS Overrange—True. Channel A/Channel B LVDS Overrange—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. SCLK Input SDIO Input/Output CSB Input SPI Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. SPI Serial Data I/O. A dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip Select Bar (Active Low). CSB gates the read and write cycles. OEB PDWN Input/Output Input/Output Output Enable Input (Active Low). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). Rev. 0 | Page 12 of 36 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD DNC VCM DNC DNC AVDD AVDD VIN–A VIN+A AVDD AVDD AD6643 PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD6643 CHANNEL MULTIPLEXED (EVEN/ODD) LVDS MODE TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK SDIO OR+ OR– A D9+/D10+ (MSB) A D9–/D10– (MSB) A D7+/D8+ A D7–/D8– DRVDD A D5+/D6+ A D5–/D6– A D3+/D4+ A D3–/D4– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 09638-005 B D5–/D6– B D5+/D6+ DRVDD B D7–/D8– B D7+/D8+ B D9–/D10– (MSB) B D9+/D10+ (MSB) DCO– DCO+ DNC DNC DRVDD A 0/D0– (LSB) A 0/D0+ (LSB) A D1–/D2– A D1+/D2+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC DNC DNC DNC DNC DNC DNC DRVDD B 0/D0– (LSB) B 0/D0+ (LSB) B D1–/D2– B D1+/D2+ B D3–/D4– B D3+/D4+ Figure 5. Pin Configuration (Top View), LFCSP Channel Multiplexed (Even/Odd) LVDS Table 9. Pin Function Descriptions for the Channel Multiplexed (Even/Odd) LVDS Mode Pin No. ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 4 to 9, 26, 27, 55, 56, 58 0 Mnemonic Type Description DRVDD AVDD Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). DNC Do Not Connect. Do not connect to these pins. AGND, Exposed Paddle Ground The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. VIN+A VIN−A VIN+B VIN−B VCM Input Input Input Input Output CLK+ CLK− Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. ADC Clock Input—True. ADC Clock Input—Complement. SYNC Input Digital Synchronization Pin. Slave mode only. B 0/D0− (LSB) Output 12 B 0/D0+ (LSB) Output 13 14 15 B D1−/D2− B D1+/D2+ B D3−/D4− Output Output Output Channel B LVDS Output 0/Data 0—Complement. The output bit on the rising edge of the data clock output (DCO) from this output is always a Logic 0. Channel B LVDS Output 0/Data 0—True. The output bit on the rising edge of the data clock output (DCO) from this output is always a Logic 0. Channel B LVDS Output Data 1/Data 2—Complement. Channel B LVDS Output Data 1/Data 2—True. Channel B LVDS Output Data 3/Data 4—Complement. ADC Analog 51 52 62 61 57 1 2 Digital Input 3 Digital Outputs 11 Rev. 0 | Page 13 of 36 AD6643 Pin No. 16 17 18 20 21 22 23 29 Mnemonic B D3+/D4+ B D5−/D6− B D5+/D6+ B D7−/D8− B D7+/D8+ B D9−/D10− (MSB) B D9+/D10+ (MSB) A 0/D0− (LSB) Type Output Output Output Ouput Output Output Output Output A 0/D0+ (LSB) Output A D1−/D2− A D1+/D2+ A D3−/D4− A D3+/D4+ A D5−/D6− A D5+/D6+ A D7−/D8− A D7+/D8+ A D9−/D10− (MSB) A D9+/D10+ (MSB) OR+ OR− DCO+ DCO− Output Output Output Output Output Output Output Output Output Output Output Output Output Output SCLK Input 44 SDIO Input/Output 46 CSB Input OEB PDWN Input Input 30 31 32 33 34 35 36 38 39 40 41 43 42 25 24 SPI Control 45 ADC Configuration 47 48 Description Channel B LVDS Output Data 3/Data 4—True. Channel B LVDS Output Data 5/Data 6—Complement. Channel B LVDS Output Data 5/Data 6—True. Channel B LVDS Output Data 7/Data 8—Complement. Channel B LVDS Output Data 7/Data 8—True. Channel B LVDS Output Data 9/Data 10—Complement. Channel B LVDS Output Data 9/Data 10—True. Channel B LVDS Output 0/Data 1—Complement. The first output bit from this output is always a Logic 0. Channel B LVDS Output 0/Data 1—True. The first output bit from this output is always a Logic 0. Channel A LVDS Output Data 1/Data 0—Complement. Channel A LVDS Output Data 1/Data 0—True. Channel A LVDS Output Data 3/Data 2—Complement. Channel A LVDS Output Data 3/Data 2—True. Channel A LVDS Output Data 5/Data 4—Complement. Channel A LVDS Output Data 5/Data 4—True. Channel A LVDS Output Data 7/Data 6—Complement. Channel A LVDS Output Data 7/Data 6—True. Channel A LVDS Output Data 9/Data 8—Complement. Channel A LVDS Output Data 9/Data 8—True. Channel A/Channel B LVDS Overrange Output—True. Channel A/Channel B LVDS Overrange Output—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. SPI Serial Clock (SCKL). The serial shift clock input, which is used to synchronize serial interface reads and writes. SPI Serial Data Input/Output (SDIO). A dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. SPI Chip Select Bar (Active Low). An active low control that gates the read and write cycles. Output Enable Input (Active Low). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). Rev. 0 | Page 14 of 36 AD6643 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 200 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted. 0 0 200MSPS 30.1MHz @ –1dBFS SNR = 65.8dB (66.8dBFS) SFDR = 88dBc –20 AMPLITUDE (dBFS) –60 –80 –100 –60 THIRD HARMONIC –80 –100 –120 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 –140 09638-006 0 0 Figure 6. Single Tone FFT, fIN = 30.1 MHz AMPLITUDE (dBFS) 80 90 100 200MSPS 220.1MHz @ –1dBFS SNR = 65dB (66dBFS) SFDR = 84dBc –60 –80 –100 –120 –40 –60 THIRD HARMONIC SECOND HARMONIC –80 –100 –120 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 –140 09638-007 0 0 Figure 7. Single Tone FFT, fIN = 90.1 MHz 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 90 100 09638-010 AMPLITUDE (dBFS) 40 50 60 70 FREQUENCY (MHz) –20 –40 Figure 10. Single Tone FFT, fIN = 220.1 MHz 0 0 200MSPS 140.1MHz @ –1dBFS SNR = 65.4dB (66.4dBFS) SFDR = 87.5dBc –20 AMPLITUDE (dBFS) –60 200MSPS 305.1MHz @ –1dBFS SNR = 64.4dB (65.4dBFS) SFDR = 79dBc –20 –40 THIRD HARMONIC –80 –100 –120 –40 –60 THIRD HARMONIC –80 –100 –120 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 09638-008 AMPLITUDE (dBFS) 30 0 200MSPS 90.1MHz @ –1dBFS SNR = 65.5dB (66.5dBFS) SFDR = 88dBc –20 –140 20 Figure 9. Single Tone FFT, fIN = 185.1 MHz 0 –140 10 09638-009 –120 –40 Figure 8. Single Tone FFT, fIN = 140.1 MHz –140 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 Figure 11. Single Tone FFT, fIN = 305.1 MHz Rev. 0 | Page 15 of 36 09638-011 AMPLITUDE (dBFS) –40 –140 200MSPS 185.1MHz @ –1dBFS SNR = 65.2dB (66.2dBFS) SFDR = 87.5dBc –20 AD6643 120 –20 SNR (dBFS) SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 100 0 80 SFDR (dBFS) 60 40 20 SFDR (dBc) SNR (dBc) SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 09638-012 –90 –120 –90.0 100 0 95 –20 SFDR (dBc) 90 80 75 70 200MSPS 89.12MHz @ –7dBFS 92.12MHz @ –7dBFS SFDR = 89dBc (96dBFS) –60 –80 –100 85 95 105 115 125 135 145 155 165 175 185 195 FREQUENCY (MHz) –140 09638-013 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 Figure 16. Two Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz 0 0 200MSPS 184.12MHz @ –7dBFS 187.12MHz @ –7dBFS SFDR = 86dBc (93dBFS) –20 –20 –40 AMPLITUDE (dBFS) SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 –21.0 –7.0 09638-014 –67.0 –55.5 –44.0 –32.5 INPUT AMPLITUDE (dBFS) –80 –100 –120 IMD3 (dBFS) –78.5 –60 Figure 14. Two Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz –140 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 Figure 17. Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz Rev. 0 | Page 16 of 36 09638-017 75 09638-016 –120 Figure 13. Single Tone SNR/SFDR vs. Input Frequency (fIN) SFDR/IMD3 (dBc AND dBFS) –7.0 SNR (dBFS) 65 –120 –90.0 –21.0 –40 85 60 65 –67.0 –55.5 –44.0 –32.5 INPUT AMPLITUDE (dBFS) Figure 15. Two Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN), fIN = 90.1 MHz –78.5 09638-015 IMD3 (dBFS) 0 –100 AD6643 100 SNR/SFDR (dBc AND dBFS) 95 90 85 80 SNR, CHANNEL B SFDR, CHANNEL B SNR, CHANNEL A SFDR, CHANNEL A 75 70 60 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 SAMPLE RATE (MSPS) 09638-018 65 Figure 18. Single Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90.1 MHz 12,000 0.614LSB rms 16,384 TOTAL HITS 8000 6000 4000 2000 0 N N+1 OUTPUT CODE 09638-019 NUMBER OF HITS 10,000 Figure 19. Grounded Input Histogram Rev. 0 | Page 17 of 36 AD6643 EQUIVALENT CIRCUITS AVDD 350Ω SCLK OR PDWN 26kΩ 09638-027 09638-031 VIN Figure 24. Equivalent SCLK or PDWN Input Circuit Figure 20. Equivalent Analog Input Circuit AVDD AVDD AVDD AVDD CSB OR OEB 0.9V 350Ω CLK– 09638-028 CLK+ 15kΩ 09638-032 15kΩ 26kΩ Figure 21. Equivalent Clock lnput Circuit Figure 25. Equivalent CSB or OEB Input Circuit DRVDD AVDD AVDD V+ V– DATAOUT– DATAOUT+ V– SYNC 0.9V V+ Figure 26. Equivalent SYNC Input Circuit Figure 22. Equivalent LVDS Output Circuit DRVDD 350Ω 26kΩ 09638-030 SDIO 09638-033 09638-053 16kΩ 0.9V Figure 23. Equivalent SDIO Circuit Rev. 0 | Page 18 of 36 AD6643 THEORY OF OPERATION The AD6643 has two analog input channels and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port(s) as a filtered, and optionally decimated, digital signal. ANALOG INPUT CONSIDERATIONS ADC ARCHITECTURE The clock signal alternatively switches the input between sample mode and hold mode (see Figure 27). When the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output drive current. During power-down, the output buffers enter a high impedance state. The AD6643 dual IF receiver can simultaneously digitize two channels, making it ideal for diversity reception and digital predistortion (DPD) observation paths in telecommunication systems. The dual IF receiver design can be used for diversity reception of signals, whereas the ADCs operate identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can input frequencies from dc to 300 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in performance. Operation to 400 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. Synchronization capability is provided to allow synchronized timing between multiple devices. Programming and control of the AD6643 are accomplished using a 3-wire SPI-compatible serial interface. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, any shunt capacitors placed across the inputs should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. For more information, refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters,” available at www.analog.com. BIAS S S CFB CS VIN+ CPAR1 CPAR2 H S S CS VIN– CPAR1 CPAR2 S S BIAS CFB 09638-034 The AD6643 architecture consists of dual front-end sampleand-hold circuits, followed by pipelined, switched capacitor ADCs. The quantized outputs from each stage are combined into a final 11-bit result in the digital correction logic. Alternately, the 11-bit result can be processed through the noise shaping requantizer (NSR) block before it is sent to the digital correction logic. The analog input to the AD6643 is a differential switched capacitor circuit designed for optimum performance in differential signal processing. Figure 27. Switched Capacitor Input For best dynamic performance, match the source impedances driving VIN+ and VIN− and differentially balance the inputs. Input Common Mode The analog inputs of the AD6643 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Place this Rev. 0 | Page 19 of 36 AD6643 decoupling capacitor close to the VCM pin to minimize series resistance and inductance between the device and this capacitor. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. Differential Input Configurations Optimum performance is achieved by driving the AD6643 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, ADA4930-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD6643. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 30). In this configuration, the input is ac-coupled, and the CML is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD6643 (see Figure 28), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 15pF In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters the value of the input resistors and capacitors may need to be adjusted, or some components may need to be removed. Table 10 lists recommended values to set the RC network for different input frequency ranges. However, because these values are dependent on the input signal and bandwidth, they are to be used as a starting guide only. Note that the values given in Table 10 are for each R1, R2, C2, and R3 component shown in Figure 29 and Figure 30. 200Ω 76.8Ω 33Ω 90Ω 15Ω VIN– AVDD 5pF ADC ADA4930-2 0.1µF 15Ω 33Ω 120Ω VCM VIN+ 15pF 33Ω 09638-035 200Ω 0.1µF Figure 28. Differential Input Configuration Using the ADA4930-2 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration, as shown in Figure 29. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. Table 10. Example RC Network Frequency Range (MHz) 0 to 100 100 to 300 C2 R3 R2 ADC C1 R2 R1 0.1µF R3 VCM VIN– 33Ω R2 Series (Ω) 0 0 0.1µF C2 09638-036 49.9Ω C1 Differential (pF) 8.2 3.9 Figure 29. Differential Transformer-Coupled Configuration C2 R3 R1 0.1µF 0.1µF 2V p-p R2 VIN+ 33Ω PA S S C2 Shunt (pF) 15 8.2 R3 Shunt (Ω) 49.9 49.9 An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use an amplifier with variable gain. The AD8375 or AD8376 digital variable gain amplifiers (DVGAs) provide good performance for driving the AD6643. Figure 31 shows an example of the AD8376 driving the AD6643 through a band-pass antialiasing filter. VIN+ R1 2V p-p R1 Series (Ω) 33 15 P 0.1µF 33Ω 0.1µF ADC C1 R1 R2 R3 VIN– 33Ω C2 Figure 30. Differential Double Balun Input Configuration Rev. 0 | Page 20 of 36 VCM 0.1µF 09638-037 VIN AD6643 1000pF 180nH 220nH 301Ω 5.1pF 1µH AD8376 VPOS 1µH 15pF 165Ω 3.9pF 1nF 1000pF 180nH AD6643 VCM 1nF 165Ω 68nH 2.5kΩ║2pF 220nH 09638-038 NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. Figure 31. Differential Input Configuration Using the AD8376 A stable and accurate voltage reference is built into the AD6643. The full-scale input range can be adjusted by varying the reference voltage via the SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD6643 sample clock inputs (CLK+ and CLK−) by using a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 32) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. clock from feeding through to other portions of the AD6643, yet preserves the fast rise and fall times of the signal, which are critical to low jitter performance. Mini-Circuits® ADT1-1WT, 1:1Z 390pF XFMR 390pF CLOCK INPUT 50Ω ADC CLK+ 100Ω 390pF CLK– SCHOTTKY DIODES: HSMS2822 09638-040 VOLTAGE REFERENCE Figure 33. Transformer-Coupled Differential Clock (Up to 200 MHz) AVDD 390pF CLOCK INPUT 0.9V CLK+ 390pF CLK– SCHOTTKY DIODES: HSMS2822 25Ω 4pF 09638-041 CLK– 09638-039 4pF ADC 390pF Figure 34. Balun-Coupled Differential Clock (Up to 625 MHz) Figure 32. Equivalent Clock Input Circuit Clock Input Options The AD6643 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 33 and Figure 34 show two preferred methods for clocking the AD6643 (at clock rates of up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6643 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 35. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, and the ADCLK905/ADCLK907/ADCLK925, clock drivers offer excellent jitter performance. CLK+ AD95xx CLOCK INPUT ADC 0.1µF 0.1µF CLOCK INPUT 0.1µF PECL DRIVER 100Ω 0.1µF CLK– 50kΩ 50kΩ 240Ω 240Ω Figure 35. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 36. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers offer excellent jitter performance. Rev. 0 | Page 21 of 36 09638-042 CLK+ 25Ω AD6643 CLK+ 0.1µF PECL DRIVER 80 0.1µF 75 09638-043 CLK– 50kΩ 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps MEASURED 100Ω 50kΩ 70 SNR (dBc) Figure 36. Differential LVDS Sample Clock (Up to 625 MHz) Input Clock Divider 65 The AD6643 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The duty cycle stabilizer (DCS) is enabled by default on power-up. The AD6643 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. 60 55 50 1 10 100 INPUT FREQUENCY (MHz) 1k 09638-044 AD95xx CLOCK INPUT ADC 0.1µF 0.1µF CLOCK INPUT undersampling applications are particularly sensitive to jitter, as shown in Figure 37. Figure 37. SNR vs. Input Frequency and Jitter Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In cases where aperture jitter may affect the dynamic range of the AD6643, treat the clock input as an analog signal. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. The AD6643 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, thereby providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6643. Refer to the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and the AN-756 Application Note, Sample Systems and the Effects of Clock Phase Noise and Jitter, for more information about jitter performance as it relates to ADCs (see www.analog.com). Jitter on the rising edge of the input clock is of paramount concern and is not reduced by the duty cycle stabilizer. The duty cycle control loop does not function for clock rates of less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the DCS. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. POWER DISSIPATION AND STANDBY MODE 0.8 0.7 0.20 TOTAL POWER 0.5 0.15 0.4 IDRVDD 0.3 0.10 0.2 SUPPLY CURRENT (A) 0.6 High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by 0.05 0.1 0 40 SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ] In the equation, the rms aperture jitter represents the root mean square of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF 0.25 IAVDD 60 80 100 120 140 160 ENCODE FREQUENCY (MSPS) 180 0 200 09638-045 Jitter Considerations As shown in Figure 38, the power dissipated by the AD6643 is proportional to its sample rate. The data in Figure 38 was taken using the same operating conditions as those used for the Typical Performance Characteristics. TOTAL POWER (W) Clock Duty Cycle Figure 38. AD6643 Power and Current vs. Sample Rate By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD6643 is placed in power-down mode. In this state, the ADC typically dissipates 10 mW. During Rev. 0 | Page 22 of 36 AD6643 power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD6643 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Description section and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, available at www.analog.com for additional details. DIGITAL OUTPUTS The AD6643 output drivers can be configured for either ANSI LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Digital Output Enable Function (OEB) The AD6643 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI interface. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI interface, the data outputs of each channel can be independently three-stated by using the output disable bar bit (Bit 4) in Register 0x14. Because the output data is interleaved, if only one of the two channels is disabled, the data from the remaining channel is repeated in both the rising and falling output clock cycles. Timing The AD6643 provides latched data with a pipeline delay of 10 input sample clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. To reduce transients within the AD6643, minimize the length of the output data lines and loads that are placed on them. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6643 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD6643 also provides data clock output (DCO) intended for capturing the data in an external register. Figure 2 shows a graphical timing diagram of the AD6643 output modes. Table 11. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN−, Input Span = 1.75 V p-p (V) Less than −0.875 −0.875 0 + 0.875 Greater than + 0.875 Offset Binary Output Mode 000 0000 0000 000 0000 0000 100 0000 0000 111 1111 1111 111 1111 1111 Rev. 0 | Page 23 of 36 Twos Complement Mode (Default) 100 0000 0000 100 0000 0000 000 0000 0000 011 1111 1111 011 1111 1111 OR 1 0 0 0 1 AD6643 NOISE SHAPING REQUANTIZER (NSR) 200MSPS 140.1MHz @ –1.6dBFS SNR = 73.4dB (75dBFS) SFDR = 86dBc (IN BAND) –20 –40 Two different bandwidth modes are provided; the mode can be selected from the SPI port. In each of the two modes, the center frequency of the band can be tuned such that IFs can be placed anywhere in the Nyquist band. –60 –80 –100 –120 –140 0 10 20 30 22% BW MODE (>40 MHz at 184.32 MSPS) 70 80 90 Figure 40. 22% BW Mode, Tuning Word = 28 (fS/4 Tuning) 0 200MSPS 140.1MHz @ –1.6dBFS SNR = 73.5dB (75.1dBFS) SFDR = 86dBc (IN BAND) –20 –40 AMPLITUDE (dBFS) The first bandwidth mode offers excellent noise performance over 22% of the ADC sample rate (44% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR control register (Address 0x3C) to 000. In this mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x3E). There are 57 possible tuning words (TW); each step is 0.5% of the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right band edge (f1), respectively: 40 50 60 FREQUENCY (Hz) 09638-047 The NSR feature can be independently controlled per channel via the SPI. 0 AMPLITUDE (dBFS) The AD6643 features a noise shaping requantizer (NSR) to allow higher than 11-bit SNR to be maintained in a subset of the Nyquist band. The harmonic performance of the receiver is unaffected by the NSR feature. When enabled, the NSR contributes an additional 0.6 dB of loss to the input signal, such that a 0 dBFS input is reduced to −0.6 dBFS at the output pins. f0 = fADC × .005 × TW –60 –80 –100 –120 –140 f1 = f0 + 0.22 × fADC Figure 39 to Figure 41 show the typical spectrum that can be expected from the AD6643 in the 22% BW mode for three different tuning words. 0 200MSPS 140.1MHz @ –1.6dBFS SNR = 73.6dB (75.2dBFS) SFDR = 86dBc (IN BAND) –20 –60 –80 –100 –120 –140 0 10 20 30 40 50 60 FREQUENCY (Hz) 70 80 90 09638-046 AMPLITUDE (dBFS) –40 Figure 39. 22% BW Mode, Tuning Word = 13 Rev. 0 | Page 24 of 36 0 10 20 30 40 50 60 FREQUENCY (Hz) 70 Figure 41. 22% BW Mode, Tuning Word = 41 80 90 09638-048 fCENTER = f0 + 0.11 × fADC AD6643 0 33% BW MODE (>60 MHZ AT 184.32 MSPS) 200MSPS 140.1MHz @ –1.6dBFS SNR = 71.4dB (73dBFS) SFDR = 86dBc (IN BAND) –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 f0 = fADC × .005 × TW 0 10 20 30 fCENTER = f0 + 0.165 × fADC 40 50 60 FREQUENCY (Hz) 70 80 90 09638-050 The second bandwidth mode offers excellent noise performance over 33% of the ADC sample rate (66% of the Nyquist band) and can be centered by setting the NSR mode bits in the NSR control register (Address 0x3C) to 001. In this mode, the useful frequency range can be set using the 6-bit tuning word in the NSR tuning register (Address 0x3E). There are 34 possible tuning words (TW); each step is 0.5% of the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right band edge (f1), respectively: Figure 43. 33% BW Mode, Tuning Word = 17 (fS/4 Tuning) f1 = f0 + 0.33 × fADC 0 Figure 42 to Figure 44 show the typical spectrum that can be expected from the AD6643 in the 33% BW mode for three different tuning words. 200MSPS 140.1MHz @ –1.6dBFS SNR = 71.3dB (72.9dBFS) SFDR = 86dBc (IN BAND) –20 –40 –60 –80 –100 –120 0 10 20 30 40 50 60 FREQUENCY (Hz) 70 Figure 44. 33% BW Mode, Tuning Word = 27 0 10 20 30 40 50 60 FREQUENCY (Hz) 70 80 90 Figure 42. 33% BW Mode, Tuning Word = 5 Rev. 0 | Page 25 of 36 80 90 09638-051 –140 –100 –140 –60 –120 –80 09638-049 AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) 0 200MSPS 140.1MHz @ –1.6dBFS SNR = 71.2dB (72.8dBFS) SFDR = 86dBc (IN BAND) –20 AD6643 CHANNEL/CHIP SYNCHRONIZATION The AD6643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A. The SYNC input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between multiple parts, synchronize the SYNC input signal to the input clock signal. Drive the SYNC input using a single-ended CMOS type signal. Using Bit 1 in Register 0x59, the SYNC input can be set to either level or edge sensitive mode. If the SYNC input is set to edge sensitive mode, use Bit 0 of Register 0x59 to determine whether the rising or falling edge is used. Rev. 0 | Page 26 of 36 AD6643 SERIAL PORT INTERFACE (SPI) The AD6643 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin is used to synchronize the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 12. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 45 and Table 5. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 bit and the W1 bit. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, available at www.analog.com. HARDWARE INTERFACE The pins described in Table 12 comprise the physical interface between the user’s programming device and the serial port of the AD6643. Both the SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6643 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD6643. Rev. 0 | Page 27 of 36 AD6643 SPI ACCESSIBLE FEATURES Table 13. Features Accessible Using the SPI Table 13 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI (available at www.analog.com). The AD6643 partspecific features are described in the Memory Map Register Description section. Feature Name Power Mode Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage Allows the user to enable the synchronization features Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Digital Processing tHIGH tDS tS tDH tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 45. Serial Port Interface Timing Diagram Rev. 0 | Page 28 of 36 D4 D3 D2 D1 D0 DON’T CARE 09638-052 SCLK DON’T CARE AD6643 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x25); and the digital feature control registers (Address 0x3A to Address 0x59). An explanation of logic level terminology follows: The memory map register table (see Table 14) documents the default hexadecimal value for each hexadecimal address listed. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x05. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0x25. The remaining registers, from Register 0x3A to Register 0x59, are documented in the Memory Map Register Description section. Address 0x08 to Address 0x20, and Address 0x3A to Address 0x59 are shadowed. Writes to these addresses do not affect device operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Open Locations All address and bit locations that are not included in Table 14 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6643 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 14. • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Channel Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 14 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 14 affect the entire device or the channel features where independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. 0 | Page 29 of 36 AD6643 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0 0x00 SPI port configuration (global) 1 0x01 Chip ID (global) 0x02 Chip grade (global) Open Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) LSB first Soft reset 1 1 Soft reset LSB first 0 Open 8-Bit Chip ID[7:0] (AD6643 = 0x84) (default) Speed grade ID Open Open 10 = 200 MSPS Default Value (Hex) 0x18 0x84 Open Open Open Open Open Open Open ADC B (default) ADC A (default) 0x03 0xFF Open Open Open Open Open Open Open Transfer 0x00 ADC Functions 0x08 Power modes (local) Open Open Open Open Open 0x09 Global clock (global) Open Open External powerdown pin function (local) 0 = powerdown 1 = standby Open Open Open Open 0x0B Clock divide (global) Open Open Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles Rev. 0 | Page 30 of 36 Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = reserved Open Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Duty cycle stabilizer (default) The nibbles are mirrored so LSB-first mode or MSB-first mode registers correctly, regardless of shift mode Read only Speed grade ID used to differentiate devices; read only Channel Index and Transfer Registers 0x05 Channel Open index (global) Transfer (global) Default Notes/ Comments 0x00 Bits are set to determine which device on the chip receives the next write command; applies to local registers only Synchronously transfers data from the master shift register to the slave Determines various generic modes of chip operation 0x01 0x00 Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active AD6643 Addr (Hex) 0x0D Register Name Test mode (local) Bit 7 (MSB) User test mode control 0= continuous/ repeat pattern 1 = single pattern then zeros 0x0E BIST enable (local) Offset adjust (local) Output mode Open Open Open Open 0x15 Output adjust (global) Open Open Open 0x16 Clock phase control (global) DCO output delay (global) Invert DCO clock Open Open Enable DCO clock delay Open Open 0x18 Input span select (global) Open Open Open 0x19 User Test Pattern 1 LSB (global) User Test Pattern 1 MSB (global) User Test Pattern 2 LSB (global) User Test Pattern 2 MSB (global) 0x10 0x14 0x17 0x1A 0x1B 0x1C Open Bit 6 Open Bit 5 Reset PN long gen Open Open Open Bit 4 Reset PN short gen Bit 3 Bit 2 Bit 0 (LSB) Bit 1 Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output Open Open Reset BIST Open BIST sequence enable Offset adjust in LSBs from +31 to −32 (twos complement format) Output format Output Open Output invert (local) 00 = offset disable 1 = normal (default) 0 = inverted binary (local) 01 = twos complement (default) 10 = gray code 11 = reserved (local) Open LVDS output drive current adjust 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved Open Open Open Open Open Default Value (Hex) 0x00 0x00 0x00 0x05 Configures the outputs and the format of the data 0x01 0x00 0x00 DCO clock delay [delay = (3100 ps × register value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps Full-scale input voltage selection 01111 = 2.087 V p-p … 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p User Test Pattern 1[7:0] 0x00 User Test Pattern 1[15:8] 0x00 User Test Pattern 2[7:0] 0x00 User Test Pattern 2[15:8] 0x00 Rev. 0 | Page 31 of 36 Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data 0x00 Full-scale input adjustment in 0.022 V steps AD6643 Addr (Hex) 0x1D Register Bit 7 Name (MSB) User Test Pattern 3 LSB (global) 0x1E User Test Pattern 3 MSB (global) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) Digital Feature Control Registers 0x3A Sync control Open (global) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 User Test Pattern 3[7:0] Bit 1 Bit 0 (LSB) Default Notes/ Comments 0x00 User Test Pattern 3[15:8] 0x00 User Test Pattern 4[7:0] 0x00 User Test Pattern 4[15:8] 0x00 BIST signature[7:0] 0x00 Read only BIST signature[15:8] 0x00 Read only 0x00 Control register to synchronize the clock divider 0x00 Noise shaping requantizer (NSR) controls 0x1C NSR frequency tuning word Open Open Open Open Open Open Clock divider sync enable 0 = off 1 = on NSR mode 000 = 22% BW mode 001 = 33% BW mode Master sync enable 0 = off 1 = on NSR enable 0 = off 1 = on 0x3C NSR control (local) Open Open Open 0x3E NSR tuning word (local) Open Open 0x59 SYNC pin control (local) Open Open NSR tuning word See the Noise Shaping Requantizer (NSR) section Equations for the tuning word are dependent on the NSR mode SYNC pin Open Open Open Open SYNC pin edge sensitivity sensitivity 0 = sync on 0 = sync high level on 1 = sync on negative edge edge 1 = sync on positive edge 1 Default Value (Hex) The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. MEMORY MAP REGISTER DESCRIPTION Bit 1—Clock Divider Sync Enable For more information on functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, available at www.analog.com. Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 0—Master Sync Buffer Enable Bit 2—Clock Divider Next Sync Only If the master sync enable buffer bit (Address 0x3A, Bit0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs. Bit 0 must be set high to enable any of the sync functions. If the sync capability is not used this bit should remain low to conserve power. Rev. 0 | Page 32 of 36 AD6643 NSR Control (Register 0x3C) Bits[7:4]—Reserved SYNC Pin Control (Register 0x59) Bits[7:2]—Reserved Bits[3:1]—NSR Mode Bit 1—SYNC Pin Sensitivity Bits[3:1] determine the bandwidth mode of the NSR. When Bits[3:1] are set to 000, the NSR is configured for a 22% BW mode that provides enhanced SNR performance over 22% of the sample rate. When Bits[3:1] are set to 001, the NSR is configured for a 33% BW mode that provides enhanced SNR performance over 33% of the sample rate. If Bit 1 is set to a 0, the SYNC input responds to a level. If this bit is set to high, the SYNC input responds to the edge (rising or falling) set in Bit 0 of Address 0x59. Bit 0—NSR Enable Bit 0—SYNC Pin Edge Sensitivity If Bit 1 is set high, setting Bit 0 to a 0 causes the SYNC input to respond to a falling edge. Likewise, if Bit 0 is set to 1, the SYNC input responds to a rising edge. The NSR is enabled when Bit 0 is high and disabled when Bit 0 is low. NSR Tuning Word (Register 0x3E) Bits[7:6]—Reserved Bits[5:0]—NSR Tuning Word The NSR tuning word sets the band edges of the NSR band. In 22% BW mode, there are 57 possible tuning words; in 33% BW mode, there are 34 possible tuning words. For either mode, each step represents 0.5% of the ADC sample rate. For the equations that are used to calculate the tuning word based on the BW mode of operation, see the Noise Shaping Requantizer (NSR) section. Rev. 0 | Page 33 of 36 AD6643 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD6643, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD6643, it is recommended that two separate 1.8 V supplies be used: one supply for analog (AVDD) and a separate supply for the digital outputs (DRVDD). The designer can employ several different decoupling capacitors to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the pins of the device using minimal trace length. To maximize the coverage and adhesion between the ADC and the PCB, overlay a silkscreen to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). VCM A single PCB ground plane should be sufficient when using the AD6643. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Decouple the VCM pin to ground with a 0.1 μF capacitor, as shown in Figure 29. For optimal channel-to-channel isolation, a 33 Ω resistor should be included between the AD6643 VCM pin and the Channel A analog input network connection and between the AD6643 VCM pin and the Channel B analog input network connection. Exposed Paddle Thermal Heat Slug Recommendations SPI Port It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD6643 exposed paddle, Pin 0. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6643 to keep these signals from transitioning at the converter inputs during critical sampling periods. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. Rev. 0 | Page 34 of 36 AD6643 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 49 1 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 33 32 16 17 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 6.35 6.20 SQ 6.05 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 091707-C 8.75 BSC SQ TOP VIEW Figure 46. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD6643BCPZ-200 AD6643BCPZRL7-200 AD6643-200EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD6643 Z = RoHS Compliant Part. Rev. 0 | Page 35 of 36 Package Option CP-64-4 CP-64-4 AD6643 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09638-0-4/11(0) Rev. 0 | Page 36 of 36