LC2MOS Quad 8-Bit D/A Converter AD7226 FEATURES Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages Microprocessor-Compatible TTL/CMOS-Compatible No User Trims Extended Temperature Range Operation Single Supply Operation Possible APPLICATIONS Process Control Automatic Test Equipment Automatic Calibration of Large System Parameters, e.g., Gain/Offset FUNCTIONAL BLOCK DIAGRAM VREF MSB DATA (8-BIT) LSB VDD LATCH A DAC A A VOUTA D A T A LATCH B DAC B B VOUTB B U S LATCH C DAC C C VOUTC LATCH D DAC D D VOUTD WR A1 CONTROL LOGIC AD7226 A0 VSS AGND AGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7226 contains four 8-bit voltage-output digital-toanalog converters, with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve full specified performance for the part. 1. DAC-to-DAC Matching Since all four DACs are fabricated on the same chip at the same time, precise matching and tracking between the DACs is inherent. Separate on-chip latches are provided for each of the four D/A converters. Data is transferred into one of these data latches through a common 8-bit TTL/CMOS (5 V) compatible input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. The control logic is speed-compatible with most 8-bit microprocessors. 2. Single-Supply Operation The voltage mode configuration of the DACs allows the AD7226 to be operated from a single power supply rail. Each D/A converter includes an output buffer amplifier capable of driving up to 5 mA of output current. The amplifiers’ offsets are laser-trimmed during manufacture, thereby eliminating any requirement for offset nulling. Specified performance is guaranteed for input reference voltages from 2 V to 12.5 V with dual supplies. The part is also specified for single supply operation at a reference of 10 V. The AD7226 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC2MOS) process, which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip. 3. Microprocessor Compatibility The AD7226 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered. 4. Small Size Combining four DACs and four op amps plus interface logic into a 20-pin package allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all the analog inputs and outputs at one end of the package and all the digital inputs at the other. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781-461-3113 © 2011 Analog Devices, Inc. All rights reserved. AD7226–SPECIFICATIONS (VDD = 11.4 V to 16.5 V, VSS = –5 V 10%, AGND = DGND = 0 V; VREF = +2 V to (VDD – 4 V)1, unless otherwise noted. All Specifications TMIN to TMAX unless otherwise noted.) DUAL SUPPLY Parameter K, B Versions2 Unit STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Temperature Coefficient Zero Code Error Zero Code Error Temperature Coefficient 8 ±1 ± 0.5 ±1 ± 0.5 ± 20 ± 20 ± 50 Bits LSB max LSB max LSB max LSB max ppm/∞C typ mV max mV/∞C typ 2 to (VDD – 4) 2 50 200 V min to V max kW min pF min pF max DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance Input Coding 2.4 0.8 ±1 8 Binary V min V max mA max pF max DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Digital Crosstalk Minimum Load Resistance 2.5 4 10 2 V/ms min ms max nV secs typ kW min VOUT = 10 V POWER SUPPLIES VDD Range IDD ISS 11.4/16.5 13 11 V min/V max mA max mA max For Specified Performance Outputs Unloaded; VIN = VINL or VINH Outputs Unloaded; VIN = VINL or VINH SWITCHING CHARACTERISTICS4, 5 Address to Write Setup Time, tAS Address to Write Hold Time, tAH Data Valid to Write Setup Time, tDS Data Valid to Write Hold Time, tDH Write Pulsewidth, tWR 0 0 50 0 50 ns min ns min ns min ns min ns min REFERENCE INPUT Voltage Range Input Resistance Input Capacitance3 Conditions/Comments VDD = 15 V ± 5%, VREF = 10 V Guaranteed Monotonic VDD = 14 V to 16.5 V, VREF = +10 V Occurs when each DAC is loaded with all 0s. Occurs when each DAC is loaded with all 1s. VIN = 0 V or VDD VREF = 10 V; Settling Time to ± 1/2 LSB NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K Version: –40∞C to +85∞C B Version: –40∞C to +85∞C 3 Guaranteed by design. Not production tested. 4 Sample Tested at 25∞C to ensure compliance. 5 Switching Characteristics apply for single and dual supply operation. Specifications subject to change without notice. –2– REV. D AD7226 (VDD = 15 V 5%, VSS = AGND = DGND = O V; VREF = 10 V unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) 1 SINGLE SUPPLY Parameter K, B Versions2 Unit Conditions/Comments STATIC PERFORMANCE Resolution Total Unadjusted Error Differential Nonlinearity 8 ±2 ±1 Bits LSB max LSB max Guaranteed Monotonic 2 50 200 kW min pF min pF max Occurs when each DAC is loaded with all 0s. Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance Input Coding 2.4 0.8 ±1 8 Binary V min V max mA max pF max DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Digital Crosstalk Minimum Load Resistance 2 4 10 2 V/ms min ms max nV secs typ kW min VOUT = +10 V POWER SUPPLIES VDD Range IDD 14.25/15.75 13 V min/V max mA max For Specified Performance Outputs Unloaded; VIN = VINL or VINH REFERENCE INPUT Input Resistance Input Capacitance3 NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K Version: –40∞C to +85∞C B Version: –40∞C to +85∞C 3 Guaranteed by design. Not production tested. 4 Sample Tested at 25∞C to ensure compliance. Specifications subject to change without notice. VIN = 0 V or VDD Settling Time to ± 1/2 LSB ABSOLUTE MAXIMUM RATINGS 1 VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, VDD VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, VDD VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 500 mW Derates above 75∞C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/∞C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . . –40∞C to +85∞C Industrial (B Version) . . . . . . . . . . . . . . . . . –40∞C to +85∞C Storage Temperature . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 50 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. D –3– AD7226 PIN CONFIGURATIONS DIP and SOIC/SSOP VOUTB 1 20 VOUTC VOUTA 2 19 VOUTD VSS 3 18 VDD VREF 4 17 A0 16 A1 AGND 5 AD7226 TOP VIEW 15 WR (Not to Scale) 14 DB0(LSB) DB7 (MSB) 7 DGND 6 DB6 8 13 DB1 DB5 9 12 DB2 DB4 10 11 DB3 VOUTD 2 VOUTB VOUTA 3 VOUTC VSS PLCC 1 20 19 18 VDD V REF 4 17 A0 AGND 5 AD7226 DGND 6 16 A1 TOP VIEW (Not to Scale) DB7 (MSB) 7 15 WR 14 DB0(LSB) DB8 8 13 DB1 12 DB2 DB3 11 DB4 10 DB5 9 TERMINOLOGY DIFFERENTIAL NONLINEARITY TOTAL UNADJUSTED ERROR Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. This is a comprehensive specification that includes full-scale error, relative accuracy and zero code error. Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB (ideal) is VREF/ 256. The LSB size will vary over the VREF range. Hence the zero code error will, relative to the LSB size, increase as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSB’s over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of 10 V. DIGITAL CROSSTALK The glitch impulse transferred to the output of one converter due to a change in the digital input code to another of the converters. It is specified in nV secs and is measured at VREF = 0 V. FULL SCALE ERROR Full-Scale Error is defined as: Measured Value – Zero Code Error – Ideal Value RELATIVE ACCURACY Relative Accuracy or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full-scale error and is normally expressed in LSB’s or as a percentage of full-scale reading. –4– REV. D AD7226 In single supply operation (VSS = 0 V = AGND), with the output approaching AGND (i.e., digital code approaching all 0s) CIRCUIT INFORMATION D/A SECTION The AD7226 contains four identical, 8-bit, voltage mode digital-toanalog converters. The output voltages from the converters have the same polarity as the reference voltage allowing single supply operation. A novel DAC switch pair arrangement on the AD7226 allows a reference voltage range from 2 V to 12.5 V. VDD I/P Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS, single-pole, double-throw switches. The simplified circuit diagram for one channel is shown in Figure 1. Note that VREF (Pin 4) and AGND (Pin 5) are common to all four DACs. O/P 400A VSS Figure 2. Amplifier Output Stage R 2R R the current load ceases to act as a current sink and begins to act as a resistive load of approximately 2 kW to AGND. This occurs as the NMOS transistors come out of saturation. This means that, in single supply operation, the sink capability of the amplifiers is reduced when the output voltage is at or near AGND. A typical plot of the variation of current sink capability with output voltage is shown in Figure 3. VOUT R 2R 2R 2R 2R DB0 DB5 DB6 DB7 VREF AGND SHOWN FOR ALL 1s ON DAC 500 Figure 1. D/A Simplified Circuit Diagram The input impedance at the VREF pin of the AD7226 is the parallel combination of the four individual DAC reference input impedances. It is code dependent and can vary from 2 kW to infinity. The lowest input impedance (i.e., 2 KW) occurs when all four DACs are loaded with the digital code 01010101. Therefore, it is important that the reference presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 100 pF to 250 pF. VSS = –5V ISINK (A) 400 200 0 (1) 0 2 4 6 8 10 VOUT (V) where DX is fractional representation of the digital input code and can vary from 0 to 255/256. Figure 3. Variation of ISINK with VOUT If the full sink capability is required with output voltages at or near AGND (= 0 V), then VSS can be brought below 0 V by 5 V and thereby maintain the 400 mA current sink as indicated in Figure 3. Biasing VSS below 0 V also gives additional headroom in the output amplifier which allows for better zero code error performance on each output. Also improved is the slew rate and negative-going settling time of the amplifiers (discussed later). The source impedance is the output resistance of the buffer amplifier. OP AMP SECTION Each voltage-mode D/A converter output is buffered by a unity gain, noninverting CMOS amplifier. This buffer amplifier is capable of developing 10 V across a 2 kW load and can drive capacitive loads of 3300 pF. The output stage of this amplifier consists of a bipolar transistor from the VDD line and a current load to the VSS, the negative supply for the output amplifiers. This output stage is shown in Figure 2. Each amplifier offset is laser trimmed during manufacture to eliminate any requirement for offset nulling. DIGITAL SECTION The digital inputs of the AD7226 are both TTL and CMOS (5 V) compatible from VDD = 11.4 V to 16.5 V. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode from DGND to each MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible. The NPN transistor supplies the required output current drive (up to 5 mA). The current load consists of NMOS transistors which normally act as a constant current sink of 400 mA to VSS, giving each output a current sink capability of approximately 400 mA if required. The AD7226 can be operated single or dual supply resulting in different performance in some parameters from the output amplifiers. REV. D VDD = +15V VSS = 0 100 Each VOUT pin can be considered as a digitally programmable voltage source with an output voltage of: VOUTX = DX V REF 300 –5– AD7226 INTERFACE LOGIC INFORMATION Address lines A0 and A1 select which DAC will accept data from the input port. Table I shows the selection table for the four DACs with Figure 4 showing the input control logic. When the WR signal is LOW, the input latches of the selected DAC are transparent and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high the analog outputs remain at the value corresponding to the data held in their respective latches. A0 AD7226 Operation H L No Operation Device Not Selected DAC A Transparent DAC A Latched DAC B Transparent DAC B Latched DAC C Transparent DAC C Latched DAC D Transparent DAC D Latched L L L X L L L L H H H H X L L H H L L H H TO LATCH B A1 TO LATCH C TO LATCH D WR Table I. AD7226 Truth Table AD7226 Control Inputs WR A1 A0 TO LATCH A Figure 4. Input Control Logic tDS VDD VINH DATA VINL 0 tAH tAS ADDRESS tDH VDD VINH VINL 0 tWR WR VDD L = Low State, H = High State, X = Don’t Care 0 NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. tr = tf = 20ns OVER VDD RANGE. 2. TIMING MEASUREMENT REFERENCE LEVEL IS VINH + VINL 2 3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS. Figure 5. Write Cycle Timing Diagram –6– REV. D Typical Performance Characteristics–AD7226 (TA = 25C, VDD = 15 V, VSS = –5 V) 1.5 VREF = 10V 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 1 0 –1 –2 –3 2 4 6 8 VREF (V) 10 12 14 TPC 3. Differential Nonlinearity vs. VREF 2.0 3 1.5 ZERO CODE ERROR (LSBs) RELATIVE ACCURACY (LSBs) 2 0 AD7226K, B 4 3 –4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 INPUT CODE (DECIMAL EQUIVALENT) TPC 1. Channel-to-Channel Matching 2 1 0 –1 –2 –3 1.0 0.5 VOUT A 0 VOUTD VOUTB –0.5 VOUTC –1.0 –1.5 –4 –2.0 0 2 4 6 8 VREF (V) 10 12 14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 TEMPERATURE (C) TPC 4. Zero Code Error vs. Temperature TPC 2. Relative Accuracy vs. VREF REV. D AD7226K, B 4 DIFFERENTIAL NONLINEARITY (LSBs) TOTAL UNADJUSTED ERROR (LSBs) 2.0 –7– AD7226 SPECIFICATION RANGES In order for the DACs to operate to their specifications, the reference voltage must be at least 4 V below the VDD power supply voltage. This voltage differential is required for correct generation of bias voltages for the DAC switches. DATA +1/2 LSB The AD7226 is specified to operate over a VDD range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V) with a VSS of –5 V ± 10%. Operation is also specified for a single +15 V ± 5% VDD supply. Applying a VSS of –5 V results in improved zero code error, improved output sink capability with outputs near AGND and improved negative-going settling time. O/P –1/2 LSB Performance is specified over a wide range of reference voltages from 2 V to (VDD – 4 V) with dual supplies. This allows a range of standard reference generators to be used such as the AD780, a 2.5 V band gap reference and the AD584, a precision 10 V reference. Note that in order to achieve an output voltage range of 0 V to 10 V a nominal 15 V ± 5% power supply voltage is required by the AD7226. Figure 7a. Positive Step Settling Time (VSS = –5 V) DATA SETTLING TIME +1/2 LSB The output stage of the buffer amplifiers consists of a bipolar NPN transistor from the VDD line and a constant current load to VSS. VSS is the negative power supply for the output buffer amplifiers. As mentioned in the op amp section, in single supply operation the NMOS transistor will come out of saturation as the output voltage approaches AGND and will act as a resistive load of approximately 2 kW to AGND. As a result, the settling time for negative-going signals approaching AGND in single supply operation will be longer than for dual supply operation where the current load of 400 mA is maintained all the way down to AGND. Positive-going settling-time is not affected by VSS. O/P –1/2 LSB Figure 7b. Negative Step Settling Time (VSS = –5 V) GROUND MANAGEMENT The settling-time for the AD7226 is limited by the slew-rate of the output buffer amplifiers. This can be seen from Figure 6 which shows the dynamic response for the AD7226 for a full scale change. Figures 7a and 7b show expanded settling-time photographs with the output waveforms derived from a differential input to an oscilloscope. Figure 7a shows the settling time for a positive-going step and Figure 7b shows the settling time for a negative-going output step. AC or transient voltages between AGND and DGND can cause noise at the analog output. This is especially true in microprocessor systems where digital noise is prevalent. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7226. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7226 AGND and DGND pins (IN914 or equivalent). Unipolar Output Operation This is the basic mode of operation for each channel of the AD7226, with the output voltage having the same positive polarity as +VREF. The AD7226 can be operated single supply (VSS = AGND) or with positive/negative supplies (see op amp section which outlines the advantages of having negative VSS). The code table for unipolar output operation is shown in Table II. Note that the voltage at VREF must never be negative with respect to DGND in order to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in Figure 8. DATA VOUT Figure 6. Dynamic Response (VSS = –5 V) –8– REV. D AD7226 With R1 = R2 VDD VREF VOUT = (2D A – 1) ¥ V REF MSB where DA is a fractional representation of the digital word in latch A. VOUTA DB7 DAC A Mismatch between R1 and R2 causes gain and offset errors and therefore these resistors must match and track over temperature. Once again the AD7226 can be operated in single supply or from positive/negative supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 9 with R1 = R2. VOUTB DB0 LSB DAC B VOUTC WR (4) DAC C VREF A1 R1 VDD VREF VOUTD A0 DAC D AD7226* R2 +15V VOUTA VSS AGND DGND VOUT DAC A –15V R1, R2 = 10k 0.1% Figure 8. AD7226 Unipolar Output Circuit VSS AGND DGND *DIGITAL INPUTS OMITTED FOR CLARITY Table II. Unipolar Code Table Figure 9. AD7226 Bipolar Output Circuit DAC Latch Contents MSB LSB Analog Output 1111 1111 Ê 255 ˆ +V REF Á ˜ Ë 256 ¯ 1000 0001 Ê 129 ˆ +V REF Á ˜ Ë 256 ¯ 1000 0000 Table III. Bipolar (Offset Binary) Code Table DAC Latch Contents MSB LSB Ê 128 ˆ V REF +V REF Á ˜=+ Ë 256 ¯ 2 Analog Output 1111 1111 Ê 127 ˆ +V REF Á ˜ Ë 128 ¯ 1000 0001 Ê 1 ˆ +V REF Á ˜ Ë 128 ¯ 1000 0000 0V 0111 1111 Ê 1 ˆ –V REF Á ˜ Ë 128 ¯ 0111 1111 Ê 127 ˆ +V REF Á ˜ Ë 256 ¯ 0000 0001 Ê 1 ˆ +V REF Á ˜ Ë 256 ¯ 0000 0001 Ê 127 ˆ –V REF Á ˜ Ë 128 ¯ 0000 0000 0V 0000 0000 Ê 128 ˆ –V REF Á ˜ = –V REF Ë 128 ¯ Ê 1 ˆ Note: LSB = (VREF ) 2–8 = VREF Á ˜ Ë 256 ¯ ( ) AGND BIAS (2) The AD7226 AGND pin can be biased above system GND (AD7226 DGND) to provide an offset “zero” analog output voltage level. Figure 10 shows a circuit configuration to achieve this for channel A of the AD7226. The output voltage, VOUTA, can be expressed as: Bipolar Output Operation Each of the DACs of the AD7226 can be individually configured to provide bipolar output operation. This is possible using one external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the AD7226. In this case Ê Ê R2 ˆ R2 ˆ VOUT = Á1 + ¥ ( DAVREF ) – Á ˜ ¥ (VREF ) R1 ˜¯ Ë Ë R1 ¯ REV. D VOUT A = VBIAS + DA (VIN ) (5) where DA is a fractional representation of the digital input word (0 £ D £ 255/256). (3) –9– AD7226 generated in software with each D/A converter being loaded from a separate loop. The loops run through the look-up table producing successive triads of sinusoidal values with 120∞ separation which are loaded to the D/A converters producing three sine wave voltages 120∞ apart. A complete sine wave cycle is generated by stepping through the full look-up table. If a 256-element sine wave table is used then the resolution of the circuit will be 1.4∞ (360∞/256). Figure 13 shows typical resulting waveforms. The sine waves can be smoothed by filtering the D/A converter outputs. VDD VREF AD7226* VOUTA DAC A AGND 5 VBIAS VSS DGND *DIGITAL INPUTS OMITTED FOR CLARITY Figure 10. AGND Bias Circuit For a given VIN, increasing AGND above system GND will reduce the effective VDD–VREF which must be at least 4 V to ensure specified operation. Note that because the AGND pin is common to all four DACs, this method biases up the output voltages of all the DACs in the AD7226. Note that VDD and VSS of the AD7226 should be referenced to DGND. 3-PHASE SINE WAVE The circuit of Figure 11 shows an application of the AD7226 in the generation of 3-phase sine waves which can be used to control small 3-phase motors. The proper codes for synthesizing a full sine wave are stored in EPROM, with the required phaseshift of 120∞ between the three D/A converter outputs being generated in software. Data is loaded into the three D/A converters from the sine EPROM via the microprocessor or control logic. Three loops are The fourth D/A converter of the AD7226, DAC D, may be used in a feedback configuration to provide a programmable reference voltage for itself and the other three converters. This configuration is shown in Figure 11. The relationship of VREF to VIN is dependent upon digital code and upon the ratio of RF to R and is given by the formula. V REF = SINE EPROM ¥ V IN (6) where G = RF/R and DD is a fractional representation of the digital word in latch D. Alternatively, for a given VIN and resistance ratio, the required value of DD for a given value of VREF can be determined from the expression V R DD = (1 + R / R F ) ¥ IN – (7) V REF R F Figure 12 shows typical plots of VREF versus digital code for three different values of RF. With VIN = 2.5 V and RF = 3 R the peak-to-peak sine wave voltage from the converter outputs will vary between 2.5 V and 10 V over the digital input code range of 0 to 255. ADDRESS BUS MICROPROCESSOR OR CONTROL LOGIC (1 + G ) (1 + G ¥ DD ) VIN VREF ADDRESS DECODE A0 A1 VOUTA VOUTB RF WR VOUTC AD7226 R VOUTD DATA BUS Figure 11. 3-Phase Sine Wave Generation Circuit 4.0 V IN 3.5 V IN VDD = +15 V VSS = –5 V VOUTA RF = 3R VREF 3.0 V IN 2.5 V IN 2.0 V IN VOUTB RF = 2R VOUTC 1.5 V IN VIN RF = R 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 DIGITAL CODE (Decimal Equivalent) Figure 13. 3-Phase Sine Wave Output Figure 12. Variation of VREF with Feedback Configuration –10– REV. D AD7226 STAIRCASE WINDOW COMPARATOR VTEST FROM D.U.T. In many test systems, it is important to be able to determine whether some parameter lies within defined limits. The staircase window comparator of Figure 14a is a circuit that can be used, for example, to measure the VOH and VOL thresholds of a TTL device under test. Upper and lower limits on both VOH and VOL can be programmably set using the AD7226. Each adjacent pair of comparators forms a window of programmable size. If VTEST lies within a window, then the output for that window will be high. With a reference of 2.56 V applied to the VREF input, the minimum window size is 10 mV. 10k VREF 5V VDD WINDOW 1 VOUTA VOUTB AD7226 5V 10k WINDOW 2 VOUTC VOUTD VTEST FROM D.U.T. 1/4 CA339 5V AGND 10k WINDOW 3 10k VREF 5V VDD WINDOW 1 Figure 15a. Overlapping Windows VOH (HIGH) VREF VOUTA 5V 10k WINDOW 1 WINDOW 2 VOUTB VOUTA VOH (LOW) WINDOW 2 VOUTB VOUTD 5V AD7226 10k VOUTC WINDOW 3 WINDOW 3 AGND VOL (HIGH) VOUTC Figure 15b. Window Structure 5V 10k WINDOW 4 +15V +4V VOUTD 15k VOL (LOW) 10k 5V AGND –4V WINDOW 5 10k VDD VREF *DIGITAL INPUTS OMITTED FOR CLARITY Figure 14a. Logic Level Measurement AD7226* VOUTA DAC A VREF WINDOW 1 VOUTA VOUTB VSS WINDOW 2 WINDOW 3 AGND DGND Figure 16. Varying Reference Signal VOUTC WINDOW 4 VOUTD WINDOW 5 AGND Figure 14b. Window Structure The circuit can easily be adapted to allow for overlapping of windows as shown in Figure 15a. If the three outputs from this circuit are decoded then five different nonoverlapping programmable windows can again be defined. REV. D VARYING REFERENCE SIGNAL In some applications, it may be desirable to have a varying signal applied to the reference input of the AD7226. The AD7226 has multiplying capability within upper and lower limits of reference voltage when operated with dual supplies. The upper and lower limits are those required by the AD7226 to achieve its linearity specification. Figure 16 shows a sine wave signal applied to the reference input of the AD7226. For input signal frequencies up to 50 kHz, the output distortion typically remains less than 0.1%. Typical 3 dB bandwidth figure is 700 kHz. –11– AD7226 OFFSET ADJUST +10V Figure 17 shows how the AD7226 can be used to provide programmable input offset voltage adjustment for the AD544 op amp. Each output of the AD7226 can be used to trim the input offset voltage on one AD544. The 620 kW resistor tied to 10 V provides a fixed bias current to one offset node. For symmetrical adjustment, this bias current should equal the current in the other offset node with the half-full scale code (i.e., 10000000) on the DAC. Changing the code on the DAC varies the bias current and hence provides offset adjust for the AD544. For example, the input offset voltage on the AD544J, which has a maximum of ± 2 mV, can be programmably trimmed to ± 10 mV. +15V VDD VREF AD7226* 7 VOUTA DAC A 500k VSS AGND 1 4 5 620k DGND –15V *DIGITAL INPUTS OMITTED FOR CLARITY Figure 17. Offset Adjust for AD544 6502 8085A A15 A15 ADDRESS BUS ADDRESS BUS A0 A8 ADDRESS EN DECODE WR AD7226* R/W WR 2 EN ADDRESS EN DECODE A0 A1 WR A0 AD7226* A1 ALE DS2 8212 DB7 DB7 DB0 DB0 D7 D7 DATA BUS ADDRESS/DATA BUS D0 D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 20. AD7226 to 6502 Interface Figure 18. AD7226 to 8085A Interface 6809 Z-80 A15 A15 ADDRESS BUS ADDRESS BUS A0 A0 R/W EN ADDRESS EN DECODE A0 A1 WR WR ADDRESS EN DECODE A0 A1 WR AD7226* AD7226* E DB7 DB7 DB0 DB0 D7 D7 DATA BUS DATA BUS D0 D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 21. AD7226 to Z-80 Interface Figure 19. AD7226 to 6809 Interface –12– REV. D AD7226 OUTLINE DIMENSIONS 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 20 11 1 10 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070706-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 1. 20-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-20) Dimensions shown in inches and (millimeters) 0.098 (2.49) MAX 0.005 (0.13) MIN 20 11 1 10 0.310 (7.87) 0.220 (5.59) PIN 1 0.200 (5.08) MAX 1.060 (26.92) MAX 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 2. 20-Lead Ceramic Dual In-Line Package [CERDIP] (Q-20) Dimensions shown in inches and (millimeters) Rev. D | Page 1 AD7226 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 0.65 BSC 8° 4° 0° SEATING PLANE 0.95 0.75 0.55 060106-A 0.38 0.22 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX COMPLIANT TO JEDEC STANDARDS MO-150-AE Figure 3. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 10 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) Rev. D | Page 14 1.27 (0.0500) 0.40 (0.0157) 06-07-2006-A 1 AD7226 0.180 (4.57) 0.165 (4.19) 0.048 (1.22 ) 0.042 (1.07) 3 0.048 (1.22) 0.042 (1.07) 4 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) MIN 19 PIN 1 IDENTIFIER 18 TOP VIEW 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) (PINS DOWN) 14 8 0.020 (0.51) R 9 0.020 (0.50) R BOTTOM VIEW (PINS UP) 13 0.045 (1.14) R 0.025 (0.64) 0.356 (9.04) SQ 0.350 (8.89) 0.120 (3.04) 0.090 (2.29) 0.395 (10.03) SQ 0.385 (9.78) COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 5. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 AD7226BQ AD7226BRSZ AD7226KN AD7226KNZ AD7226KP AD7226KP-REEL AD7226KPZ AD7226KPZ-REEL AD7226KR AD7226KR-REEL AD7226KRZ AD7226KRZ-REEL AD7226BCHIPS Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Total Unadjusted Error2 ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB Package Description 20 Lead CERDIP 20 Lead SSOP 20 Lead PDIP 20 Lead PDIP 20 Lead PLCC 20 Lead PLCC 20 Lead PLCC 20 Lead PLCC 20 Lead SOIC - Wide 20 Lead SOIC - Wide 20 Lead SOIC - Wide 20 Lead SOIC - Wide Chips or Die Package Option3 Q-20 RS-20 N-20 N-20 P-20A P-20A P-20A P-20A RW-20 RW-20 RW-20 RW-20 1 Z = ROHS Compliant Part. Dual supply operation. 3 N = plastic DIP; P = plastic leaded chip carrier; Q = CERDIP; RW = SPIC; RS = SSOP. 2 REVISION HISTORY 1/11—Rev. C to Rev. D Changes to Ordering Guide ...........................................................15 3/03—Rev. B to Rev. C Title Revision ..................................................................................... 1 Edits to Ordering Guide ................................................................... 3 Edits to Absolute Maximum Ratings .............................................. 3 Edits to Pin Configurations ............................................................. 4 Edits to Specifications Ranges ......................................................... 8 Outline Dimensions Updated........................................................ 13 RS-20 Package Added ..................................................................... 13 Updated RS-20 Package Outline Dimensions ............................. 13 3/03—Rev. A to Rev. B Edits to Features ................................................................................ 1 Edits to Specifications ....................................................................... 2 Rev. D | Page AD7226 NOTES ©2003-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00987-0-1/11(D) Rev. D | Page