+30 V/±15 V Operation 128-Position Digital Potentiometer AD7376 FEATURES APPLICATIONS High voltage DAC Programmable power supply Programmable gain and offset adjustment Programmable filters, delays Actuator control Audio volume control Mechanical potentiometer replacement FUNCTIONAL BLOCK DIAGRAM AD7376 SDO VDD Q A 7-BIT SERIAL REGISTER 7 7-BIT LATCH 7 W SDI D CK B R SHDN CLK CS VSS GND RS SHDN 01119-001 128 positions 10 kΩ, 50 kΩ, 100 kΩ 20 V to 30 V single-supply operation ±10 V to ±15 V dual-supply operation 3-wire SPI®-compatible serial interface THD 0.006% typical Programmable preset Power shutdown: less than 1 µA iCMOS™ process technology Figure 1. GENERAL DESCRIPTION The AD73761 is one of the few high voltage, high performance digital potentiometers2 on the market. This device can be used as a programmable resistor or resistor divider. The AD7376 performs the same electronic adjustment function as mechanical potentiometers, variable resistors, and trimmers with enhanced resolution, solid-state reliability, and programmability. With digital rather than manual control, the AD7376 provides layout flexibility and allows closed-loop dynamic controllability. 1 2 The AD7376 features sleep-mode programmability in shutdown that can be used to program the preset before device activation, thus providing an alternative to costly EEPROM solutions. The AD7376 is available in 14-lead TSSOP and 16-lead wide body SOIC packages in 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are guaranteed to operate over the −40°C to +85°C extended industrial temperature range. Patent number: 54952455. The terms digital potentiometer and RDAC are used interchangeably. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1997–2011 Analog Devices, Inc. All rights reserved. AD7376 TABLE OF CONTENTS Features .............................................................................................. 1 Programming the Variable Resistor ......................................... 12 Applications ....................................................................................... 1 Programming the Potentiometer Divider ............................... 13 Functional Block Diagram .............................................................. 1 3-Wire Serial Bus Digital Interface .......................................... 13 General Description ......................................................................... 1 Daisy-Chain Operation ............................................................. 14 Revision History ............................................................................... 2 ESD Protection ........................................................................... 14 Specifications..................................................................................... 3 Terminal Voltage Operating Range ......................................... 14 Electrical Characteristics—10 kΩ Version................................ 3 Power-Up and Power-Down Sequences.................................. 14 Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 4 Layout and Power Supply Biasing ............................................ 15 Timing Specifications .................................................................. 5 Applications Information .............................................................. 16 3-Wire Digital Interface ................................................................... 6 High Voltage DAC...................................................................... 16 Absolute Maximum Ratings ............................................................ 7 Programmable Power Supply ................................................... 16 ESD Caution .................................................................................. 7 Audio Volume Control .............................................................. 17 Pin Configurations and Function Descriptions ........................... 8 Outline Dimensions ....................................................................... 18 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 19 Theory of Operation ...................................................................... 12 REVISION HISTORY 8/11—Rev. C to Rev. D Changes to Output Logic Low Conditions, Table 1 ..................... 3 Changes to Output Logic Low Conditions, Table 2 ..................... 5 Changes to Figure 28 ...................................................................... 14 Updates Outline Dimensions ........................................................ 18 7/09—Rev. B to Rev. C Changes to Features Section............................................................ 1 Updates Outline Dimensions ........................................................ 19 Changes to Ordering Guide .......................................................... 20 3/07—Rev. A to Rev. B Updated Format ..................................................................Universal Changes to Absolute Maximum Ratings ....................................... 7 Changes to ESD Protection Section ............................................. 14 Changes to Ordering Guide .......................................................... 19 11/05—Rev. 0 to Rev. A Updated Format .................................................................. Universal Deleted DIP Package .......................................................... Universal Changes to Features ..........................................................................1 Separated Electrical Characteristics into Table 1 and Table 2 .....3 Separated Interface Timing into Table 3 ........................................5 Changes to Table 1 Through Table 3...............................................3 Added Table 4 ....................................................................................6 Added Figure 2...................................................................................6 Changes to Absolute Maximum Ratings Section ..........................7 Deleted Parametric Test Circuits Section .......................................7 Changes to Typical Performance Characteristics..........................9 Added Daisy-Chain Operation Section ...................................... 14 Added ESD Protection Section ..................................................... 14 Added Terminal Voltage Operating Range Section ................... 14 Added Power-Up and Power-Down Sequences Section ........... 14 Added Layout and Power Supply Biasing Section ..................... 15 Added Applications Section .......................................................... 16 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 10/97—Revision 0: Initial Version Rev. D | Page 2 of 20 AD7376 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—10 kΩ VERSION VDD/VSS = ±15 V ± 10%, VA = VDD, VB = VSS/0 V, −40°C < TA < +85°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS— RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Integral Nonlinearity 4 Differential Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Capacitance 6 A, B Capacitance6 Shutdown Supply Current 7 Shutdown Wiper Resistance Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Power Supply Range Positive Supply Current Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB)/∆T × 106 RW RWB, VA = NC, VDD/VSS = ±15 V RWB, VA = NC, VDD/VSS = ±15 V TA = 25°C VAB = VDD, wiper = no connect VDD/VSS = ±15 V VDD/VSS = ±5 V −1 −1 −30 ±0.5 ±0.5 +1 +1 +30 LSB LSB % ppm/°C Ω Ω INL DNL (∆VW/VW)/∆T × 106 VDD/VSS = ±15 V VDD/VSS = ±15 V Code = 0x40 −1 −1 ±0.5 ±0.5 5 +1 +1 LSB LSB ppm/°C VWFSE VWZSE Code = 0x7F, VDD/VSS = ±15 V Code = 0x00, VDD/VSS = ±15 V −3 0 −1.5 1.5 0 3 LSB LSB VDD 45 V pF 60 pF VA, B, W CA, B CW IA_SD RW_SD ICM VSS f = 1 MHz, measured to GND, code = 0x40 f = 1 MHz, measured to GND, code = 0x40 VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = 15 V VA = V B = V W VIH VIL VOH VOL IIL CIL VDD = 5 V or 15 V VDD = 5 V or 15 V RPull-Up = 2.2 kΩ to 5 V IOL = 1.6 mA, VDD = 15 V VIN = 0 V or 5 V VDD/VSS VDD IDD Dual-supply range Single-supply range, VSS = 0 VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V ΔVDD/ΔVSS = ±15 V ± 10% Negative Supply Current ISS Power Dissipation 8 Power Supply Rejection Ratio PDISS PSRR −300 120 260 0.02 170 1 200 1 400 2.4 0.8 4.9 0.4 ±1 5 Rev. D | Page 3 of 20 ±4.5 4.5 12 −0.2 ±0.05 ±16.5 33 2 25 −0.1 −0.1 31.5 +0.2 µA Ω nA V V V V µA pF V V mA µA mA mA mW %/% AD7376 Parameter DYNAMIC CHARACTERISTICS6, 9,10 Bandwidth −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Symbol Conditions BW THDW tS eN_WB Code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 10 V, VB = 0 V, ±1 LSB error band RWB = 5 kΩ, f = 1 kHz Min Typ 1 Max 470 0.006 4 0.9 Unit kHz % µs nV√Hz Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic. 3 Pb-free parts have a 35 ppm/°C temperature coefficient (tempco). 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. A terminal is open circuit in shutdown mode. 8 PDISS is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation. 9 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 10 All dynamic characteristics use VDD = 15 V and VSS = −15 V. 1 2 ELECTRICAL CHARACTERISTICS—50 kΩ, 100 kΩ VERSIONS VDD/VSS = ±15 V ± 10% or ±5 V ± 10%, VA = VDD, VB = VSS/0 V, −40°C < TA < +85°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient 3 Wiper Resistance DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Integral Nonlinearity 4 Differential Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Capacitance 6 A, B Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL RWB, VA = NC RWB, VA = NC, RAB = 50 kΩ RWB, VA = NC, RAB = 100 kΩ TA = 25°C VAB = VDD, wiper = no connect VDD/VSS = ±15 V VDD/VSS = ±5 V −1 −1.5 −1 −30 ±0.5 ±0.5 ±0.5 +1 +1.5 +1 +30 LSB LSB LSB % ppm/°C Ω Ω ∆RAB (∆RAB/RAB)/∆T × 106 RW INL DNL (∆VW/VW)/∆T × 106 Code = 0x40 VWFSE VWZSE Code = 0x7F Code = 0x00 VA, B, W CA, B Capacitance6 CW Shutdown Supply Current 7 Shutdown Wiper Resistance Common-Mode Leakage IA_SD RW_SD ICM −300 120 260 −1 −1 ±0.5 ±0.5 5 +1 +1 LSB LSB ppm/°C −2 0 −0.5 0.5 0 1 LSB LSB VDD 45 V pF 60 pF VSS f = 1 MHz, measured to GND, code = 0x40 f = 1 MHz, measured to GND, code = 0x40 VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = 15 V VA = V B = V W Rev. D | Page 4 of 20 200 0.02 170 1 1 400 µA Ω nA AD7376 Parameter DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Power Supply Range Positive Supply Current Negative Supply Current Power Dissipation 8 Power Supply Rejection Ratio DYNAMIC CHARACTERISTICS6, 9, 10 Bandwidth −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Symbol Conditions Min VIH VIL VOH VOL IIL CIL VDD = 5 V or 15 V VDD = 5 V or 15 V RPull-Up = 2.2 kΩ to 5 V IOL = 1.6 mA, VDD = 15 V VIN = 0 V or 5 V 2.4 VDD/VSS VDD IDD Dual-supply range Single-supply range, VSS = 0 VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V ISS PDISS PSRR BW THDW tS eN_WB Typ 1 Max 0.8 4.9 0.4 ±1 5 ±4.5 4.5 12 −0.25 RAB = 50 kΩ, code = 0x40 RAB = 100 kΩ, code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 10 V, VB = 0 V, ±1 LSB error band RWB = 25 kΩ, f = 1 kHz ±0.1 ±16.5 33 2 25 −0.1 −0.1 31.5 +0.25 90 50 0.002 4 2 Unit V V V V µA pF V V mA µA mA mA mW %/% kHz kHz % µs nV√Hz Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic. 3 Pb-free parts have a 35 ppm/°C temperature coefficient. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. A terminal is open circuit in shutdown mode. 8 PDISS is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation. 9 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 10 All dynamic characteristics use VDD = 15 V and VSS = −15 V. 1 2 TIMING SPECIFICATIONS Table 3. Parameter INTERFACE TIMING CHARACTERISTICS 1, 2 Clock Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay 3 CS Setup Time CS High Pulse Width Reset Pulse Width CLK Fall to CS Fall Hold Time CLK Rise to CS Rise Hold Time CS Rise to Clock Rise Setup Symbol fCLK tCH, tCL tDS tDH tPD tCSS tCSW tRS tCSH0 tCSH tCS1 Conditions Min Clock level high or low 120 30 20 10 120 150 120 10 120 120 RPull-Up = 2.2 kΩ, CL < 20 pF Typ Max Unit 4 MHz ns ns ns ns ns ns ns ns ns ns 100 Guaranteed by design and not subject to production test. See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 15 V and VSS = −15 V. 3 Propagation delay depends on value of VDD, RPull-Up, and CL. 1 2 Rev. D | Page 5 of 20 AD7376 3-WIRE DIGITAL INTERFACE Table 4. AD7376 Serial Data-Word Format 1 MSB D6 26 D4 D3 D2 D1 Data is loaded MSB first. 1 SDI D6 0 D5 D4 D3 D2 D1 D0 1 CLK 0 1 CS RDAC REGISTER LOAD 0 01119-002 1 VOUT 0 Figure 2. AD7376 3-Wire Digital Interface Timing Diagram (VA = VDD, VB = 0 V, VW = VOUT) SDI (DATA IN) 1 DX DX 0 tDS tDH SDO (DATA OUT) 1 D'X D'X 0 tPD_MAX tCH 1 tCS1 CLK 0 tCSH0 1 CS tCL tCSS tCSH tCSW 0 tS VDD VOUT 0V ±1 LSB ERROR BAND ±1 LSB Figure 3. Detail Timing Diagram Rev. D | Page 6 of 20 01119-003 1 D5 LSB D0 20 AD7376 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB ≤ 6 kΩ, A open, VDD/VSS = 30 V/0 V) 1 IWA Continuous (RWA ≤ 6 kΩ, B open, VDD/VSS = 30 V/0 V)1 Digital Input and Output Voltages to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) 2 Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Thermal Resistance θJA 16-Lead SOIC_W 14-Lead TSSOP Rating −0.3 V to +35 V +0.3 V to −16.5 V −0.3 V to +35 V VSS to VDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ±20 mA ±5 mA ±5 mA 0 V to VDD + 0.3 V −40°C to +85°C 150°C −65°C to +150°C 260°C 20 sec to 40 sec (TJMAX − TA)/θJA 120°C/W 240°C/W Maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX – TA)/θJA. 1 Rev. D | Page 7 of 20 AD7376 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 14 W B 2 13 NC AD7376 VSS 3 GND 4 16 15 NC VSS 3 14 VDD GND 4 12 VDD CS 5 TOP VIEW 11 SDO (Not to Scale) 10 SHDN W A 1 B 2 AD7376 TOP VIEW 13 SDO (Not to Scale) 12 SHDN 11 SDI 9 SDI CLK 7 10 NC CLK 7 8 NC NC 8 9 NC NC = NO CONNECT 01119-004 RS 6 RS 6 CS 5 NC = NO CONNECT Figure 4. 14-Lead TSSOP Pin Configuration 01119-005 A 1 Figure 5. 16-Lead SOIC_W Pin Configuration Table 6.Pin Function Descriptions 14-Lead TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 Pin No. 16-Lead SOL 1 2 3 4 5 6 7 8, 9, 10 11 12 13 14 15 16 Mnemonic A B VSS GND CS RS CLK NC SDI SHDN SDO VDD NC W Description A Terminal. VSS ≤ VA ≤ VDD. B Terminal. VSS ≤ VB ≤ VDD. Negative Power Supply. Digital Ground. Chip Select Input, Active Low. When CS returns high, data is loaded into the wiper register. Reset to Midscale. Serial Clock Input. Positive edge triggered. No Connect. Let it float or ground. Serial Data Input (data loads MSB first). Shutdown. A terminal open ended; W and B terminals shorted. Can be used as programmable preset. 1 Serial Data Output. Positive Power Supply. No Connect. Let it float or ground. Wiper Terminal. VSS ≤ VW ≤ VDD. Assert shutdown and program the device during power-up. Then, deassert the shutdown to achieve the desirable preset level. Rev. D | Page 8 of 20 AD7376 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 +85°C 0.2 +25°C 0.1 0 –40°C –0.1 –0.2 01119-006 –0.3 –0.4 –0.5 0 16 32 48 64 80 96 112 VDD = +15V VSS = –15V 0.4 POTENTIOMETER MODE DNL (LSB) 0.4 0.3 0.2 +85°C 0.1 +25°C 0 –0.1 –40°C –0.2 –0.3 –0.4 –0.5 128 0 16 32 80 96 112 128 20 0.5 VDD = +15V VSS = –15V 0.4 IDD @ VDD/VSS = 30V/0V 16 0.3 SUPPLY CURRENT (µA) +85°C 0.2 0.1 0 –0.1 –40°C +25°C –0.2 –0.3 IDD @ VDD/VSS = ±15V 12 8 4 ISS @ VDD/VSS = 30V/0V 0 01119-007 RHEOSTAT MODE DNL (LSB) 64 Figure 9. Potentiometer Divider Differential Nonlinearity Error vs. Code Figure 6. Resistance Step Position Nonlinearity Error vs. Code –0.4 –0.5 0 16 32 48 64 80 96 112 ISS @ VDD/VSS = ±15V –4 –40 128 –20 0 CODE (Decimal) 20 40 60 80 100 120 TEMPERATURE (°C) Figure 7. Relative Resistance Step Change from Ideal vs. Code Figure 10. Supply Current (IDD, ISS) vs. Temperature 0.5 0.5 VDD = +15V VSS = –15V 0.4 0.3 0.2 SHUTDOWN CURRENT (µA) +85°C +25°C 0.1 0 –40°C –0.1 –0.2 0.2 0.1 0 –0.1 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 0 16 32 48 64 80 96 112 –0.5 –40 128 CODE (Decimal) 01119-011 0.3 0.4 01119-008 POTENTIOMETER MODE INL (LSB) 48 CODE (Decimal) CODE (Decimal) 01119-010 RHEOSTAT MODE INL (LSB) 0.5 VDD = +15V VSS = –15V 01119-009 0.5 –20 0 20 40 60 80 100 TEMPERATURE (ºC) Figure 8. Potentiometer Divider Nonlinearity Error vs. Code Figure 11. Shutdown Current vs. Temperature Rev. D | Page 9 of 20 120 AD7376 120 VDD/VSS = ±15V 100 80 50kΩ 60 40 20 10kΩ 0 –40 –20 0 20 40 60 80 100 100 100kΩ 80 60 10kΩ 40 20 0 50kΩ –20 01119-015 100kΩ RHEOSTAT MODE TEMPCO (ppm/°C) VDD/VSS = ±15V 01119-012 TOTAL RESISTANCE, RAB (kΩ) 120 –40 120 0 16 32 48 64 80 96 112 128 CODE (Decimal) TEMPERATURE (°C) Figure 15. (ΔVWB/VWB)/ΔT Potentiometer Mode Tempco Figure 12. Total Resistance vs. Temperature 0 350 0x40 –6 RW @ VDD/VSS = ±5V 0x20 –12 0x10 250 –18 –24 200 (dB) WIPER RESISTANCE RW (Ω) 300 150 0x04 –30 –36 100 0x08 0x02 0x01 –42 RW @ VDD/VSS = ±15V 01119-013 0 –40 –20 0 20 40 60 80 100 01119-016 –48 50 –54 –60 1k 120 10k 1M Figure 16. 10 kΩ Gain vs. Frequency vs. Code Figure 13. Wiper Contact Resistance vs. Temperature 0 120 VDD/VSS = ±15V –6 100 –12 80 –18 0x40 0x20 0x10 0x08 60 –24 (dB) 10kΩ 40 50kΩ 20 0x04 –30 0x02 –36 0x01 –42 0 –40 0 16 32 48 64 80 96 112 01119-017 –48 100kΩ –20 01119-014 POTENTIOMETER MODE TEMPCO (ppm/°C) 100k (Hz) TEMPERATURE (°C) –54 –60 1k 128 CODE (Decimal) 10k 100k (Hz) Figure 14. (ΔRWB/RWB)/ΔT Rheostat Mode Tempco Figure 17. 50 kΩ Gain vs. Frequency vs. Code Rev. D | Page 10 of 20 1M AD7376 0.1 0 –6 0x20 –12 0x10 –18 10kΩ 0.01 THD + N (%) 0x08 –24 (dB) VDD/VSS = ±15V CODE = MIDSCALE VIN = 1Vrms 0x40 0x04 –30 0x02 –36 0x01 100kΩ 50kΩ 0.001 –42 –54 –60 1k 10k 0.0001 10 1M 100k 01119-021 01119-018 –48 100 1k 10k 100k FREQUENCY (Hz) (Hz) Figure 21. Total Harmonic Distortion Plus Noise vs. Frequency Figure 18. 100 kΩ Gain vs. Frequency vs. Code 1 VDD/VSS = ±15V CODE = MIDSCALE fIN = 1kHz 0.1 10kΩ THD + N (%) 2 50kΩ 0.01 01119-019 CH2 5V M2µs T 50% A CH1 0.001 0.001 4.20V 6 –PSRR @ V DD/VSS = ±15V DC ± 10% p-p AC +PSRR @ VDD/VSS = ±5V DC ± 10% p-p AC 01119-020 PSRR (–dB) THEORETICAL IWB_MAX (mA) –PSRR @ VDD/VSS = ±5V DC ± 10% p-p AC 0 100 1k 10k 100k RAB = 10kΩ 5 +PSRR @ VDD/VSS = ±15V DC ± 10% p-p AC 40 20 1 10 Figure 22. Total Harmonic Distortion Plus Noise vs. Amplitude CODE = 40H, VA = VDD, VB = VSS 60 0.1 AMPLITUDE (V) Figure 19. Midscale to Midscale − 1 Transition Glitch 80 0.01 1M FREQUENCY (Hz) Figure 20. Power Supply Rejection vs. Frequency VDD/VSS = 30V/0V VA = VDD VB = 0V 4 3 RAB = 50kΩ 2 1 RAB = 100kΩ 0 0 16 32 01119-023 CH1 5V 01119-022 100kΩ 1 48 64 80 CODE (Decimal) 96 112 Figure 23. Theoretical Maximum Current vs. Code Rev. D | Page 11 of 20 128 AD7376 THEORY OF OPERATION PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The part operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or tied to the W terminal as shown in Figure 24. A A W B W W B 01119-024 A B Figure 24. Rheostat Mode Configuration The nominal resistance between Terminals A and B, RAB, is available in 10 kΩ, 50 kΩ, and 100 kΩ with ±30% tolerance and has 128 tap points accessed by the wiper terminal. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings. Figure 25 shows a simplified RDAC structure. A SWA The AD7376 wiper switches are designed with the transmission gate CMOS topology, and the gate voltage is derived from the VDD. Each switch’s on resistance, RW, is a function of VDD and temperature (see Figure 13). Contrary to the temperature coefficient of RAB, the temperature coefficient of the wiper resistance is significantly higher because the wiper resistance doubles with every 100° increase. As a result, the user must take into consideration the contribution of RW on the desirable resistance. On the other hand, each switch’s on resistance is insensitive to the tap point potential and remains relatively flat at 120 Ω typical at a VDD of 15 V and a temperature of 25°C. Assuming that a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for programming code 0x00, where SWB is closed. The minimum resistance between Terminals W and B is therefore 120 Ω in general. The second connection is the first tap point, which corresponds to 198 Ω (RWB = 1/128 × RAB + RW = 78 Ω + 120 Ω) for programming code 0x01, and so on. SHDN Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,042 Ω (RAB – 1 LSB + RW). Regardless of which settings the part is operating with, care should be taken to limit the current conducted between any A and B, W and A, or W and B terminals to a maximum dc current of 5 mA and a maximum pulse current of 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. RS D6 D5 D4 D3 D2 D1 D0 0x7F RS RS W RDAC LATCH AND DECODER Similar to the mechanical potentiometer, the resistance of the RDAC between the W and A terminals also produces a digitally controlled complementary resistance, RWA. 0x01 SWB B RS = RNOMINAL/128 When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded into the latch increases in value. The general equation for this operation is 01119-025 0x00 RS Figure 25. AD7376 Equivalent RDAC Circuit The general equation determining the digitally programmed output resistance between the W and the B terminals is RWB (D) D R AB RW 128 RWA (D) (1) where: D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register from 0 to 127. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. Rev. D | Page 12 of 20 128 D R AB RW 128 (2) AD7376 PROGRAMMING THE POTENTIOMETER DIVIDER 3-WIRE SERIAL BUS DIGITAL INTERFACE Voltage Output Operation The AD7376 contains a 3-wire digital interface (CS, CLK, and SDI). The 7-bit serial word must be loaded MSB first. The format of the word is shown in Figure 2. The positive edgesensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. When CS is low, the clock loads data into the serial register upon each positive clock edge. The digital potentiometer easily generates a voltage divider at Wiper W to Terminal B and Wiper W to Terminal A that is proportional to the input voltage at Terminal A to Terminal B. Unlike the polarity of VDD to GND, which must be positive, voltage across Terminal A to Terminal B, Wiper W to Terminal A, and Wiper W to Terminal B can be at either polarity. The data setup and hold times in Table 3 determine the valid timing requirements. The AD7376 uses a 7-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. VI A VO B 01119-026 W Figure 26. Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for the purpose of approximation, connecting the Terminal A to 30 V and the Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is equal to the voltage applied across Terminals A and B divided by the 128 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminals A and B is VW (D) = D VA 128 (3) A more accurate calculation that includes the effect of wiper resistance, VW, is VW (D) = R (D ) RWB (D) V A + WA VB R AB R AB (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike when in rheostat mode, the output voltage in divider mode is primarily dependent on the ratio, not the absolute values, of the internal resistors RWA and RWB. Therefore, the temperature drift reduces to 5 ppm/°C. The AD7376 powers up at a random setting. However, the midscale preset or any desirable preset can be achieved by manipulating RS or SHDN with an extra I/O. When the reset (RS) pin is asserted, the wiper resets to the midscale value. Midscale reset can be achieved dynamically or during power-up if an extra I/O is used. When the SHDN pin is asserted, the AD7376 opens SWA to let the Terminal A float and to short Wiper W to Terminal B. The AD7376 consumes negligible power during the shutdown mode and resumes the previous setting once the SHDN pin is released. On the other hand, the AD7376 can be programmed with any settings during shutdown. With an extra programmable I/O asserting shutdown during power-up, this unique feature allows the AD7376 with programmable preset at any desirable level. Table 7 shows the logic truth table for all operations. Table 7. Input Logic Control Truth Table 1 CLK L P CS L L RS H H SHDN H H X X X P H X H H L H H H X X H H P H H L 1 Register Activity Enables SR, enables SDO pin. Shifts one bit in from the SDI pin. The seventh previously entered bit is shifted out of the SDO pin. Loads SR data into 7-bit RDAC latch. No operation. Sets 7-bit RDAC latch to midscale, wiper centered, and SDO latch cleared. Latches 7-bit RDAC latch to 0x40. Opens circuits resistor of Terminal A, connects Wiper W to Terminal B, turns off SDO output transistor. P = positive edge, X = don’t care, and SR = shift register. Rev. D | Page 13 of 20 AD7376 DAISY-CHAIN OPERATION ESD PROTECTION All digital inputs are protected with a series input resistor and an ESD structure shown in Figure 29. These structures apply to digital input pins CS, CLK, SDI, RS, and SHDN. SHDN CS SDO Q VDD CK RS 01119-027 CLK RS Figure 27. Detailed SDO Output Schematic of the AD7376 LOGIC PINS Figure 27 shows the details of the serial data output pin (SDO). SDO shifts out the SDI content in the previous frame; therefore, it can be used for daisy-chaining multiple devices. The SDO pin contains an open-drain N-Channel MOSFET and requires a pull-up resistor if the SDO function is used. Users need to tie the SDO pin of one package to the SDI pin of the next package. For example, in Figure 28, if two AD7376s are daisy-chained, a total of 14 bits of data are required for each operation. The first set of seven bits goes to U2; the second set of seven bits goes to U1. CS should be kept low until all 14 bits are clocked into their respective serial registers. Then CS is pulled high to complete the operation. GND Figure 29. Equivalent ESD Protection Circuit All analog terminals are also protected by ESD protection diodes, as shown in Figure 30. VDD A W B When daisy-chaining multiple devices, users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO to SDI interface may induce a time delay to subsequent devices. VSS Figure 30. Equivalent ESD Protection Analog Pins 5V U1 µC MOSI SDI TERMINAL VOLTAGE OPERATING RANGE U2 AD7376 SDO RPU 2.2kΩ AD7376 SDI SDO SCLK SS CLK CS CLK 01119-028 CS Figure 28. Daisy-Chain Configuration INPUT 340Ω 01119-029 D 01119-030 SERIAL REGISTER SDI The AD7376 VDD and VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. Applied signals present on Terminals A, B, and W that are more positive than VDD or more negative than VSS will be clamped by the internal forward-biased diodes (see Figure 30). POWER-UP AND POWER-DOWN SEQUENCES Because of the ESD protection diodes that limit the voltage compliance at Terminals A, B, and W (see Figure 30), it is important to power VDD/VSS before applying voltage to Terminals A, B, and W. Otherwise, the diodes are forward biased such that VDD/VSS are powered unintentionally and affect the system. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is in the following order: GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS. Rev. D | Page 14 of 20 AD7376 It is a good practice to employ a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance. The ground pin of the AD7376 is a digital ground reference. To minimize the digital ground bounce, the AD7376 digital ground terminal should be joined remotely to the analog ground (see Figure 31). Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum or electrolytic capacitors should be applied at the supplies to minimize transient disturbances and filter low frequency ripple. Figure 31 illustrates the basic supply bypassing configuration for the AD7376. VDD C3 10µF C4 VSS VDD + C1 0.1µF AD7376 + C2 10µF 0.1µF VSS GND 01119-031 LAYOUT AND POWER SUPPLY BIASING Figure 31. Power Supply Bypassing Rev. D | Page 15 of 20 AD7376 APPLICATIONS INFORMATION HIGH VOLTAGE DAC PROGRAMMABLE POWER SUPPLY The AD7376 can be configured as a high voltage DAC as high as 30 V. The circuit is shown in Figure 32. The output is With a boost regulator such as ADP1611, AD7376 can be used as the variable resistor at the regulator’s FB pin to provide the programmable power supply (see Figure 33). The output is D R2 1.2 V 1 128 R1 (5) D 128 RAB VO 1.23 V 1 R2 Where D is the decimal code from 0 to 127. VDD VDD RBIAS U1A V+ Note that the AD7376’s VDD is derived from the output. Initially L1 acts as a short, and VDD is one diode voltage drop below +5 V. The output slowly establishes to the final value. U2 AD7376 100kΩ V– B U1B AD8512 VOUT The AD7376 shutdown sleep-mode programming can be used to program a desirable preset level at power-up. U1 AD7376 R2 R1 01119-032 ADR512 AD8512 D1 (6) C1 0.1µF Figure 32. High Voltage DAC VDD A R1 100kΩ B SD W 5V CIN 10µF IN ADP1611 RT 1.23V R2 8.5kΩ U2 CSS 22nF VOUT SW D1 FB SS L1 4.7µF COMP GND RC 220kΩ CC 150pF Figure 33. Programmable Power Supply Rev. D | Page 16 of 20 COUT 10µF 01119-033 VO (D ) AD7376 AUDIO VOLUME CONTROL In Figure 34, the lower trace shows that the volume level changes from a quarter scale to full scale when a signal change occurs near the zero-crossing window. Because of its good THD performance and high voltage capability, the AD7376 can be used for digital volume control. If AD7376 is used directly as an audio attenuator or gain amplifier, a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. To prevent this, a zero-crossing window detector can be inserted to the CS line to delay the device update until the audio signal crosses the window. Since the input signal can operate on top of any dc levels rather than absolute zero volt level, zero-crossing, in this case, means the signal is ac-coupled and the dc offset level is the signal zero reference point. The AD7376 shutdown sleep-mode programming feature can be used to mute the device at power-up by holding SHDN low and programming zero scale. 1 The configuration to reduce zipper noise and the result of using this configuration are shown in Figure 35 and Figure 34, respectively. The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B. U6 is used to establish the signal zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or 0.005 V window) in this example. This output is AND’ed with the chip select signal such that the AD7376 updates whenever the signal crosses the window. To avoid constant update of the device, the chip select signal should be programmed as two pulses, rather than the one shown in Figure 2. 01119-035 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p NOTES 1. THE LOWER TRACE SHOWS THAT THE VOLUME LEVEL CHANGES FROM QUARTER SCALE TO FULL SCALE, WITH THE CHANGE OCCURRING NEAR THE ZERO-CROSSING WINDOW. Figure 34. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 35 C1 1µF +5V U1 R1 100kΩ +15V +5V V+ ADCM371 V– R2 200Ω R4 90kΩ C2 0.1µF –15V U4B 4 +5V 7408 5 R5 10kΩ U6 V+ AD8541 V– R3 100Ω 6 1 2 U3 V+ ADCM371 V– +5V VDD A C3 0.1µF U2 +15V VSS CS CLK CLK SDI SDI CS W 100kΩ U4A 7408 AD7376 VOUT V– B –15V GND Figure 35. Audio Volume Control with Zipper Noise Reduction Rev. D | Page 17 of 20 U5 V+ 01119-034 VIN 2 AD7376 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 0.30 0.19 0.75 0.60 0.45 8° 0° SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 37. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. D | Page 18 of 20 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B 1 AD7376 ORDERING GUIDE Model 1 AD7376ARUZ10 AD7376ARUZ10-R7 AD7376ARWZ10 AD7376ARWZ10-RL AD7376ARUZ50-REEL7 AD7376ARUZ50 AD7376ARWZ50 AD7376ARUZ100 AD7376ARUZ100-R7 AD7376ARWZ100 EVAL-AD7376EBZ kΩ 10 10 10 10 50 50 50 100 100 100 10 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 2, 3 14-Lead TSSOP 14-Lead TSSOP 16-Lead SOIC_W 16-Lead SOIC_W 14-Lead TSSOP 14-Lead TSSOP 16-Lead SOIC_W 14-Lead TSSOP 14-Lead TSSOP 16-Lead SOIC_W Package Option RU-14 RU-14 RW-16 RW-16 RU-14 RU-14 RW-16 RU-14 RU-14 RW-16 Ordering Quantity 96 1,000 47 1,000 1,000 96 47 96 1,000 47 1 Z = RoHS Compliant Part. In SOIC RW-16 package top marking: line 1 shows AD7376; line 2 shows the branding information, where A10 = 10 kΩ, A50 = 50 kΩ, and A100 = 100 kΩ; line 3 shows a “#” top marking with the date code in YYWW; and line 4 shows the lot number. 3 In TSSOP-14 package top marking: line 1 shows 7376; line 2 shows the branding information, where A10 = 10 kΩ, A50 = 50 kΩ, and A100 = 100 kΩ; line 3 shows a “#” top marking with the date code in YWW; back side shows the lot number. 1 2 Rev. D | Page 19 of 20 AD7376 NOTES ©1997–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01119-0-8/11(D) Rev. D | Page 20 of 20