128-Position I2C Compatible Digital Potentiometer AD5247 FUNCTIONAL BLOCK DIAGRAM 128-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Ultracompact SC70-6 (2 mm × 2.1 mm) package I2C® compatible interface Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 3 µA typical Wide operating temperature –40°C to +125°C Evaluation board available VDD SDA A I2C INTERFACE SCL W WIPER REGISTER B 03876-0-001 FEATURES GND Figure 1. APPLICATIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing LCD brightness and contrast adjustment Automotive electronics adjustment Gain control and offset adjustment 1 Note: The terms digital potentiometer, VR, and RDAC are used interchangeably in this document. GENERAL OVERVIEW The AD5247 provides a compact 2 mm × 2.1 mm packaged solution for 128-position adjustment applications. This device performs the same electronic adjustment function as a mechanical potentiometer or a variable resistor. Available in four different end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC1 latch. Operating from a 2.7 V to 5.5 V power supply and consuming 3 µA allows for usage in portable battery-operated applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD5247 TABLE OF CONTENTS Electrical Characteristics—5 kΩ Version ...................................... 3 Level Shifting for Bidirectional Interface ................................ 15 Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4 ESD Protection ........................................................................... 15 Timing Characteristics 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................ 5 Terminal Voltage Operating Range.......................................... 15 Absolute Maximum Ratings............................................................ 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 11 I2C Interface..................................................................................... 12 Operation......................................................................................... 13 Programming the Variable Resistor ......................................... 13 Programming the Potentiometer Divider ............................... 14 Maximum Operating Current .................................................. 15 Power-Up Sequence ................................................................... 15 Layout and Power Supply Bypassing ....................................... 16 Constant Bias to Retain Resistance Setting............................. 16 Evaluation Board ........................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 I2C Compatible 2-Wire Serial Bus............................................ 14 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD5247 ELECTRICAL CHARACTERISTICS—5 kΩ VERSION Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient RWB DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance6 A Capacitance6 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 8 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ1 Max Unit R-DNL R-INL ∆RAB ∆RAB/∆T RWB RWB, VA = No Connect RWB, VA = No Connect –1.5 –4 –30 ±0.1 ±0.75 +1.5 +4 +30 LSB LSB % ppm/°C Ω DNL INL ∆VW/∆T VWFSE VWZSE VB, W CA CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSSR BW_5K THDW tS eN_WB VA = VDD, Wiper = No Connect Code = 0x00 45 75 –1 –1 Code = 0x40 Code = 0x7F Code = 0x00 –3 0 ±0.1 ±0.2 15 –2 +1 GND f = 1 MHz, Measured to GND, Code = 0x40 f = 1 MHz, Measured to GND, Code = 0x40 VA = VDD/2 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 300 +1 +1 0 +2 LSB LSB ppm/°C LSB LSB VDD V 45 pF 60 1 pF nA 2.4 0.8 2.1 0.6 ±1 5 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, Code = Midscale RAB = 5 kΩ, Code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, ±1 LSB Error Band RWB = 2.5 kΩ, RS = 0 Ω 1 3 5.5 8 40 V µA µW ±0.003 ±0.05 %/% 1.2 MHz 0.05 1 6 % µs nV/√Hz Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 2 Rev. 0 | Page 3 of 20 V V V V µA pF AD5247 ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient RWB DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error (50 kΩ, 100 kΩ) Zero-Scale Error (50 kΩ, 100 kΩ) Full-Scale Error (10 kΩ) Zero-Scale Error (10 kΩ) RESISTOR TERMINALS Voltage Range5 Capacitance6 A Capacitance6 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 8 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (10 kΩ/50 kΩ/100 kΩ) Resistor Noise Voltage Density Symbol Conditions Min Typ1 Max Unit R-DNL R-INL ∆RAB ∆RAB/∆T RWB RWB, VA = No Connect RWB, VA = No Connect –1 –2 –20 ±0.1 ±0.25 +1 +2 +20 LSB LSB % ppm/°C Ω DNL INL ∆VW/∆T VWFSE VWZSE VWFSE VWZSE VA, W CA CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSSR BW THDW tS eN_WB VA = VDD, Wiper = No Connect Code = 0x00 45 75 –1 –1 Code = 0x40 Code = 0x7F Code = 0x00 Code = 0x7F Code = 0x00 –1 0 –2 0 ±0.1 ±0.2 15 –1 +0.4 –0.5 +0.5 GND f = 1 MHz, Measured to GND, Code = 0x40 f = 1 MHz, Measured to GND, Code = 0x40 VA = VDD/2 VDD = 5V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 300 +1 +1 0 +1 0 +1 LSB LSB ppm/°C LSB LSB LSB LSB VDD V 45 pF 60 1 pF nA 2.4 0.8 2.1 0.6 ±1 5 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, Code = Midscale RAB = 10 kΩ/50 kΩ/100 kΩ, Code = 0x40 VA =1 V rms, f = 1 kHz, RAB = 10 kΩ VA = 5 V ±1 LSB Error Band RWB = 5 kΩ, RS = 0 1 3 ±0.01 5.5 8 40 ±0.02 600/100/40 0.05 2 9 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VA = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 2 Rev. 0 | Page 4 of 20 V V V V µA pF V µA µW %/% kHz % µs nV/√Hz AD5247 TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted Parameter I2C INTERFACE TIMING CHARACTERISTICS2, 3 (Specifications Apply to All Parts) SCL Clock Frequency tBUF Bus Free Time between STOP and START tHD;STA Hold Time (Repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Repeated START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for STOP Condition Symbol fSCL t1 t2 Conditions Min Typ1 Max Unit 400 kHz µs 1.3 After this period, the first clock pulse is generated. t3 t4 t5 t6 t7 t8 t9 t10 0.6 1.3 0.6 0.6 50 0.9 100 300 300 0.6 1 Typical specifications represent average readings at 25°C and VDD = 5 V. Guaranteed by design and not subject to production test. 3 See timing diagrams (Figure 31, Figure 32, Figure 33) for locations of measured values. 2 Rev. 0 | Page 5 of 20 µs µs µs µs µs ns ns ns µs AD5247 ABSOLUTE MAXIMUM RATINGS Table 4. TA = 25°C, unless otherwise noted1 Parameter VDD to GND VA, VW to GND Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx Pulsed2 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance3 θJA: SC70-6 Value –0.3 V to +7 V VDD 1 ±20 mA ±5 mA 0 V to VDD + 0.3 V –40°C to +125°C 150°C –65°C to +150°C 300°C 340°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Package power dissipation = (TJMAX – TA)/θJA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 AD5247 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.25 TA = 25°C RAB = 10kΩ 0.2 0 VDD = 5.5V –0.2 –0.4 –0.6 –0.8 –1.0 0 16 32 64 80 48 CODE (Decimal) 96 112 0.15 0.10 0 –0.05 –0.10 –0.15 –0.20 –0.25 128 TA = –40°C, +25°C, +85°C, +125°C 0.05 03876-0-037 VDD = 2.7V 0.4 03876-0-034 RHEOSTAT MODE INL (LSB) 0.6 0 Figure 2. R-INL vs. Code vs. Supply Voltages 48 64 80 CODE (Decimal) 96 112 128 0 –0.1 VDD = 5.5V –0.2 03876-0-035 –0.3 –0.4 0 16 32 48 64 80 CODE (Decimal) 96 112 0.15 0.10 VDD = 2.7V 0.05 0 VDD = 5.5V –0.05 –0.10 –0.15 03876-0-038 VDD = 2.7V POTENTIOMETER MODE INL (LSB) 0.2 0.1 TA = 25°C RAB = 10kΩ 0.20 0.3 RHEOSTAT MODE DNL (LSB) 32 0.25 TA = 25°C RAB = 10kΩ 0.4 –0.20 –0.25 128 0 32 48 64 80 CODE (Decimal) 96 112 128 0.25 0.20 TA = +25°C 0.15 TA = +85°C TA = +125°C 0.10 TA = +25°C, +85°C, +125°C 0.05 0 –0.05 TA = –40°C –0.10 03876-0-036 –0.15 –0.20 0 16 32 48 64 80 CODE (Decimal) 96 112 0.20 VDD = 2.7V 0.15 VDD = 5.5V TA = 25°C RAB = 10kΩ 0.10 VDD = 2.7V 0.05 0 –0.05 VDD = 5.5V –0.10 –0.15 03876-0-039 VDD = 2.7V RAB = 10kΩ TA = –40°C POTENTIOMETER MODE DNL (LSB) 0.25 –0.25 16 Figure 6. INL vs. Code vs. Supply Voltages Figure 3. R-DNL vs. Code vs. Supply Voltages POTENTIOMETER MODE INL (LSB) 16 Figure 5. DNL vs. Code vs. Temperature 0.5 –0.5 VDD = 2.7V RAB = 10kΩ –40°C +25°C +85°C +125°C 0.20 POTENTIOMETER MODE DNL (LSB) 0.8 –0.20 –0.25 128 0 16 32 64 80 48 CODE (Decimal) 96 Figure 7. DNL vs. Code vs. Supply Voltages Figure 4. INL vs. Code vs. Temperature Rev. 0 | Page 7 of 20 112 128 AD5247 1.50 1.0 0.4 0.2 TA = +25°C 0 TA = +125°C –0.2 –0.4 TA = –40°C TA = +25°C –0.6 TA = +85°C –0.8 –1.0 TA = +125°C 0 16 32 64 80 48 CODE (Decimal) 96 112 1.00 VDD = 5.5V, VA = 5.5V 0.75 0.50 0.25 VDD = 2.7V, VA = 2.7V 0 –40 –25 128 Figure 8. R-INL vs. Code vs. Temperature IDD, SUPPLY CURRENT (µA) 0.2 TA = –40°C, +25°C, +85°C, +125°C 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 16 32 48 64 80 CODE (Decimal) 80 96 112 VDD = 5.5V 1 VDD = 2.7V 0.1 0.01 –40 –25 –10 128 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 12. Supply Current vs. Temperature 0 500 VDD = 2.7V RAB = 10kΩ 400 VDD = 5.5V, VA = 5.5V –1.0 –1.5 –2.0 VDD = 2.7V, VA = 2.7V –2.5 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 300 100 0 –100 –200 TA = –40°C to +125°C –300 –400 –500 110 125 TA = –40°C to +85°C 200 03876-0-045 RHEOSTAT MODE TEMPCO (ppm/°C) –0.5 03876-0-042 RHEOSTAT MODEERROR INL (LSB) FSE, FULL-SCALE (LSB) 110 125 10 Figure 9. R-DNL vs. Code vs. Temperature –3.0 –40 95 DIGITAL INPUTS = 0V CODE = 0x40 03876-0-041 RHEOSTAT MODE DNL (LSB) 0.3 20 35 50 65 TEMPERATURE (°C) 100 VDD = 2.7V RAB = 10kΩ –40°C +25°C +85°C +125°C 5 Figure 11. Zero-Scale Error vs. Temperature 0.5 0.4 –10 03876-0-043 ZSE, ZERO-SCALE ERROR (LSB) 1.25 03876-0-040 RHEOSTAT MODE INL (LSB) TA = –40°C TA = +85°C 0.6 03876-0-044 0.8 0 16 32 48 64 80 CODE (Decimal) 96 112 Figure 13. Rheostat Mode Tempco ∆RWB/∆T vs. Code Figure 10. Full-Scale Error vs. Temperature Rev. 0 | Page 8 of 20 128 AD5247 30 0 0x20 –12 20 0x10 –18 15 TA = –40°C TO +85°C GAIN (dB) POTENTIOMETER (ppm/°C) 0x40 –6 VDD = 2.7V RAB = 10kΩ 25 10 5 0x08 –24 0x04 –30 0x02 –36 0x01 –42 0 0 16 32 48 64 80 CODE (Decimal) 96 112 –54 –60 1k 128 Figure 14. Potentiometer Mode Tempco ∆VWB/∆T vs. Code 10k 100k FREQUENCY (Hz) GAIN (dB) 0x04 –30 0x02 0x01 –36 03876-0-047 –48 100k 1M 0x02 –36 –48 10k 0x04 –30 –42 –54 0x08 –24 –42 –60 1k 0x10 –18 0x08 –24 0x20 –12 0x10 –18 0x40 –6 0x20 –12 0x01 –54 –60 1k 10M 10k FREQUENCY (Hz) Figure 15. Gain vs. Frequency vs. Code, RAB = 5 kΩ 0x10 0x08 0x04 0x01 –36 –48 100k FREQUENCY (Hz) 1M 50kΩ –30 –48 –54 100kΩ –24 –42 10k 10kΩ –18 –42 –60 1k 5kΩ –12 0x02 –36 10M 03876-0-051 –30 –6 0x20 GAIN (dB) –24 1M 0 0x40 03876-0-048 GAIN (dB) –18 100k FREQUENCY (Hz) Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ 0 –6 10M 0 0x40 –6 –12 1M Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ 0 GAIN (dB) 03876-0-049 TA = –40°C TO +125°C 03876-0-050 –10 03876-0-046 –48 –5 –54 –60 1k 10M Figure 16. Gain vs. Frequency vs. Code, RAB = 10 kΩ 10k 100k FREQUENCY (Hz) 1M Figure 19. –3 dB Bandwidth @ Code = 0x80 Rev. 0 | Page 9 of 20 10M AD5247 0.30 0.25 VDD = 5.5V VA = 5.0V VB = 0V CODE 0x40 to 0x3F B - VDD = 5.5V CODE = 0x7F 0.20 C - VDD = 2.7V CODE = 0x55 0.15 D - VDD = 2.7V CODE = 0x7F VW 0.10 A C D 0 1k 10k 100k FREQUENCY (Hz) 03876-0-054 B 0.05 1M 200ns/DIV Figure 20. IDD vs. Frequency 150 Figure 23. Midscale Glitch, Code 0x40 to 0x3F TA = 25°C RAB = 50kΩ VDD = 5.5V VA = 5.0V VB = 0V CODE 0x00 to 0x7F 125 TA = 25°C RAB = 10kΩ 100 VDD = 2.7V VW 75 25 0 VDD = 5.5V 0 16 32 03876-0-055 50 03876-0-056 WIPER RESISTANCE (Ω) TA = 25°C RAB = 10kΩ 03876-0-052 IDD (µA) TA = 25°C A - VDD = 5.5V CODE = 0x55 80 48 64 CODE (Decimal) 96 112 128 4µs/DIV Figure 21. Wiper Resistance vs. Code vs. VDD Figure 24. Large Signal Settling Time TA = 25°C RAB = 10kΩ FCLK = 100kHz VDD = 5.5V VA = 5.0V VB = 0V VW 5V CLK 03876-0-053 0V 1µs/DIV Figure 22. Digital Feedthrough Rev. 0 | Page 10 of 20 AD5247 TEST CIRCUITS Figure 25 to Figure 30 define the test conditions used in the product Specification tables. A V+ W VMS ∆V MS% ∆V DD% VMS Figure 28. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Figure 25. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) NO CONNECT DUT DUT A PSS (%/%) = B 03876-0-022 B W ∆V (∆V MS ) DD 03876-0-025 VDD PSRR (dB) = 20 LOG IW +15V A VIN W W OP27 B VMS 03876-0-023 B VOUT 03876-0-028 A V+ = VDD 10% DUT V+ = VDD 1LSB = V+/2N DUT V+ VA –15V Figure 29. Test Circuit for Gain vs. Frequency Figure 26. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) NC DUT VW VDD B VMS1 RW = [VMS1 – VMS2]/ I W A GND B NC Figure 27. Test Circuit for Wiper Resistance W ICM VCM 03876-0-030 W DUT 03876-0-024 A VMS2 I W = VDD /R NOMINAL Figure 30. Test Circuit for Common-Mode Leakage Current Rev. 0 | Page 11 of 20 AD5247 I2C INTERFACE Table 5. Write Mode S 0 1 0 1 1 1 0 A W X D6 D5 D4 Slave Address Byte D3 D2 D1 D0 A P D2 D1 D0 A P Data Byte Table 6. Read Mode S 0 1 0 1 1 Slave Address Byte 1 0 R A 0 D6 D5 D4 D3 Data Byte S = Start Condition. W = Write. P = Stop Condition. R = Read. A = Acknowledge. D6, D5, D4, D3, D2, D1, D0 = Data Bits. X = Don’t Care. t8 t2 t9 SCL t6 t2 t3 t7 t4 t5 t10 t9 t8 t1 S S P Figure 31. I2C Interface, Detailed Timing Diagram 1 9 9 1 1 SCL 1 0 1 1 1 0 D6 D5 D4 ACK BY AD5247 FRAME 1 SLAVE ADDRESS BYTE START BY MASTER X R/W D3 D2 D1 D0 ACK BY AD5247 FRAME 2 DATA BYTE STOP BY MASTER 03876-0-004 0 SDA Figure 32. Writing to the RDAC Register 1 9 1 9 SCL SDA START BY MASTER 0 1 0 1 1 1 FRAME 1 SLAVE ADDRESS BYTE 0 0 R/W D6 ACK BY AD5247 D5 D4 D2 FRAME 2 RDAC REGISTER Figure 33. Reading from the RDAC Register Rev. 0 | Page 12 of 20 D3 D1 D0 NO ACK BY MASTER STOP BY MASTER 03876-0-005 P 03876-0-003 SDA AD5247 OPERATION The AD5247 is a 128-position, digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the default condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10, 50 kΩ = 50. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings. Assuming a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Since there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 178 Ω (RWB = RAB/128+ RW = 78 Ω + 2 × 50 Ω) for data 0x01. The third connection is the next tap point, representing 256 Ω (2 × 78 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW). Figure 34 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed. Ax D6 D5 D4 D3 D2 D1 D0 RS The general equation determining the digitally programmed output resistance between W and B is RWB(D) = (1) where D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 kΩ and the A terminal is open-circuited, the output resistance RWB shown in Table 7 will be set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance D (Dec.) 127 64 1 0 RWB (Ω) 10,100 5,100 178 100 Output State Full Scale (RAB + 2 × RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance) Note that in the zero-scale condition, a finite resistance of 100 Ω between terminals W and B is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RS RWA(D) = Wx 128 – D × RAB + 2 × RW 128 (2) For RAB = 10 kΩ and the B terminal open circuited, the output resistance RWA shown in Table 8 will be set for the indicated RDAC latch codes. RDAC Bx 03876-0-006 LATCH AND RS DECODER D × RAB + 2 × RW 128 Figure 34. AD5247 Equivalent RDAC Circuit Table 8. Codes and Corresponding RWA Resistance D (Dec.) 127 64 1 0 RWA (Ω) 178 5,100 9,961 10,100 Output State Full Scale Midscale 1 LSB Zero Scale Typical device-to-device matching is process lot dependent and may vary by up to ±30%. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/°C temperature coefficient. Rev. 0 | Page 13 of 20 AD5247 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of VDD to GND, which must be positive, voltage across A–B, W–A, and W–B can be at either polarity. If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 128 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is VW (D) = D VA 128 (3) 2. In write mode, after acknowledgement of the slave address byte, the next byte is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 5). 3. In read mode, after acknowledgment of the slave address byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference from write mode, where eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 33). 4. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 32). In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse, which goes high to establish a STOP condition (see Figure 33). For a more accurate calculation, which includes the effect of wiper resistance, VW, can be found as VW (D) = RWB(D) VA RAB (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike in rheostat mode, the output voltage in divider mode is dependent mainly on the ratio of internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C. I2C COMPATIBLE 2-WIRE SERIAL BUS The first byte of the AD5247 is a slave address byte (see Table 5 and Table 6). It has a 7-bit slave address and a R/W bit. The seven MSBs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode. 2 The 2-wire I C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 32). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing the part only once. For example, after the RDAC has acknowledged its slave address in the write mode, the RDAC output will update on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address and data byte. Similarly, a repeated read function of the RDAC is also allowed. Rev. 0 | Page 14 of 20 AD5247 VDD LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE VDD1 = 3.3V RP RP RP G D M1 SCL1 SDA2 G S D SCL2 M2 3.3V 5V AD5247 E2PROM 03876-0-007 S SDA1 W GND Figure 38. Maximum Terminal Voltages Set by VDD and GND MAXIMUM OPERATING CURRENT At low code values, the user should be aware that due to low resistance values, the current through the RDAC may exceed the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper, and the current through terminals W and B is plotted with respect to code. A line is also drawn denoting the 5 mA current limit. Note that at low code values (particularly for the 5 kΩ and 10 kΩ options), the current level increases significantly. Care should be taken to limit the current flow between W and B in this state to a maximum continuous current of 5 mA and a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contacts can occur. VDD2 = 5V RP A 03876-0-010 While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 35 shows one of the implementations. M1 and M2 can be any N channel signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low threshold FETs such as the FDV301N. Figure 35. Level Shifting for Operation at Different Potentials 100.00 ESD PROTECTION 5mA CURRENT LIMIT RAB = 5kΩ 1.00 RAB = 10kΩ RAB = 50kΩ 0.10 03876-0-057 LOGIC 10.00 IWB CURRENT (mA) 340Ω 03876-0-008 All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 36 and Figure 37. This applies to the digital input pins SDA and SCL. RAB = 100kΩ GND 0.01 Figure 36. ESD Protection of Digital Pins A,W 0 16 32 64 80 48 CODE (Decimal) 96 112 128 03876-0-009 Figure 39. Maximum Operating Current POWER-UP SEQUENCE GND Figure 37. ESD Protection of Resistor Terminals TERMINAL VOLTAGE OPERATING RANGE The AD5247 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 38). Since the ESD protection diodes limit the voltage compliance at terminals A and W (see Figure 38), it is important to power VDD/GND before applying any voltage to terminals A and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA/VW. The relative order of powering VA and VW and the digital inputs is not important as long as they are powered after VDD/GND. Rev. 0 | Page 15 of 20 AD5247 110% LAYOUT AND POWER SUPPLY BYPASSING AD5247 GND 03876-0-011 C1 C3 + 0.1µF 10µF 104% 102% 100% 98% 96% 94% 92% 90% 0 5 10 15 DAYS 20 25 30 Figure 41. Battery Operating Life Depletion This demonstrates that constantly biasing the pot is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5247 will be lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5247. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly. VDD VDD TA = 25°C 106% 03876-0-059 Similarly, it is a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 40). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. 108% BATTERY LIFE DEPLETED It is a good practice to employ a compact, minimum lead-length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Figure 40. Power Supply Bypassing EVALUATION BOARD For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5247 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5247 was designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. The graph in Figure 41 demonstrates the power consumption from a 3.4 V 450 mAhr Li-ion cell phone battery, which is connected to the AD5247. The measurement over time shows that the device draws approximately 1.3 µA and consumes negligible power. Over a course of 30 days, the battery was depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. An evaluation board, along with all necessary software, is available to program the AD5247 from any PC running Windows® 98, Windows 2000®, or Windows XP®. The graphical user interface, as shown in Figure 42, is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board. 03876-0-061 CONSTANT BIAS TO RETAIN RESISTANCE SETTING Figure 42. AD5247 Evaluation Board Software Rev. 0 | Page 16 of 20 AD5247 VDD 1 AD5247 6 A GND 2 TOP VIEW 5 W SCL 3 (Not to Scale) 4 SDA 03876-0-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 43. Pin Configuration (6-Lead SC70) Table 9. AD5247 Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VDD GND SCL SDA W A Description Positive Power Supply. Digital Ground and B Termination Voltage. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. W Terminal. A Terminal. Rev. 0 | Page 17 of 20 AD5247 OUTLINE DIMENSIONS 2.00 BSC 6 5 4 1 2 3 2.10 BSC 1.25 BSC PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 MAX 0.22 0.08 0.10 MAX 0.30 0.15 8° 4° 0° SEATING PLANE 0.46 0.36 0.26 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB Figure 44. 6-Lead Thin Shrink Small Outline Transistor [SC70] (KS-6) Dimensions shown in millimeters ORDERING GUIDE Model AD5247BKS5-R2 AD5247BKS5-RL7 AD5247BKS10-R2 AD5247BKS10-RL7 AD5247BKS50-R2 AD5247BKS50-RL7 AD5247BKS100-R2 AD5247BKS100-RL7 AD5247EVAL 1 RAB (kΩ) 5 5 10 10 50 50 100 100 See Note 1 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 Evaluation Board Package Option KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. Rev. 0 | Page 18 of 20 Branding D1E D1E D19 D19 D18 D18 D17 D17 AD5247 NOTES Rev. 0 | Page 19 of 20 AD5247 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03876–0–9/03(0) Rev. 0 | Page 20 of 20