a
FEATURES
256-Position
Replaces 1, 2, or 4 Potentiometers
1 k, 10 k, 50 k, 100 k
Power Shutdown—Less than 5 A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
2.7 V to 5.5 V Single-Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
1-/2-/4-Channel
Digital Potentiometers
AD8400/AD8402/AD8403
FUNCTIONAL BLOCK DIAGRAM
AD8403
VDD
8-BIT 8
LATCH
DAC
SELECT
DGND
10-BIT
SERIAL
LATCH
SDI
D
Each VR has its own VR latch that holds its programmed resistance
value. These VR latches are updated from an SPI compatible serialto-parallel shift register that is loaded from a standard 3-wire
serial-input digital interface. Ten data bits make up the data word
clocked into the serial input register. The data word is decoded where
the first two bits determine the address of the VR latch to be loaded,
the last eight bits are data. A serial data output pin at the opposite end
of the serial register allows simple daisy-chaining in multiple VR
applications without additional external decoding logic.
The reset (RS) pin forces the wiper to the midscale position by
loading 80H into the VR latch. The SHDN pin forces the resistor
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
SHDN
8
CK RS
2
8
8-BIT
LATCH
8
CK RS
CLK
8-BIT 8
LATCH
CS
RDAC2
SHDN
CK Q RS
RDAC3
SHDN
RDAC4
CK RS
SHDN
RS
SHDN
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When SHDN is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made that will produce
new wiper positions when the device is taken out of shutdown.
The AD8400 is available in both the SO-8 surface-mount and the
8-lead plastic DIP package.
The AD8402 is available in both surface mount (SO-14) and
14-lead plastic DIP packages, while the AD8403 is available in a
narrow body 24-lead plastic DIP and a 24-lead surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm thin
TSSOP-14/TSSOP-24 packages for PCMCIA applications. All
parts are guaranteed to operate over the extended industrial temperature range of –40°C to +125°C.
100
RWA(D), RWB(D) – % of Nominal RAB
The AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR) device.
These devices perform the same electronic adjustment function as
a potentiometer or variable resistor. The AD8400 contains a single
variable resistor in the compact SO-8 package. The AD8402 contains
two independent variable resistors in space-saving SO-14 surfacemount packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each part
contains a fixed resistor with a wiper contact that taps the fixed
resistor value at a point determined by a digital code loaded into the
controlling serial input register. The resistance between the wiper and
either endpoint of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. Each variable resistor
offers a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The fixed
A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal temperature
coefficient of 500 ppm/°C. A unique switching circuit minimizes the
high glitch inherent in traditional switched resistor designs avoiding
any make-before-break or break-before-make operation.
8-BIT
LATCH
3
A1, A0 4
SDO
GENERAL DESCRIPTION
CK RS
1
2
RDAC1
RWA
RWB
75
50
25
0
0
64
128
CODE – Decimal
192
255
Figure 1. RWA and RWB vs. Code
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
or 5 V 10%, V = V , V = 0 V,
AD8400/AD8402/AD8403–SPECIFICATIONS (V–40C= 3≤ VT ≤ 10%
+125C unless otherwise noted.)
DD
A
DD
B
A
ELECTRICAL CHARACTERISTICS–10 k VERSION
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2
R-DNL
RWB, VA = No Connect
Resistor Nonlinearity2
R-INL
RWB, VA = No Connect
RAB
TA = 25°C, Model: AD840XYY10
Nominal Resistance3
Resistance Tempco
∆RAB/∆T
VAB = VDD, Wiper = No Connect
IW = 1 V/R
Wiper Resistance
RW
Nominal Resistance Match
∆R/RAB
CH 1 to 2, 3, or 4, VAB = VDD, TA = 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
Integral Nonlinearity4
INL
Differential Nonlinearity4
DNL
VDD = 5 V
DNL
VDD = 3 V TA = 25°C
DNL
VDD = 3 V TA = –40°C, +85°C
Code = 80H
Voltage Divider Tempco
∆VW/∆T
Full-Scale Error
VWFSE
Code = FFH
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
Capacitance6 Wx
Shutdown Current7
Shutdown Wiper Resistance
VA, B, W
CA, B
CW
IA_SD
RW_SD
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk11
Min
Typ1
Max
Unit
–1
–2
8
± 1/4
± 1/2
10
500
50
0.2
+1
+2
12
LSB
LSB
kΩ
ppm/°C
Ω
%
± 1/2
± 1/4
± 1/4
± 1/2
15
–2.8
1.3
+2
+1
+1
+1.5
8
–2
–1
–1
–1.5
–4
0
0
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
RL = 2.2 kΩ to VDD
IOL = 1.6 mA, VDD = 5 V
VIN = 0 V or +5 V, VDD = 5 V
100
1
0
2
VDD
75
120
0.01
100
5
200
2.4
0.8
2.1
0.6
VDD – 0.1
0.4
±1
5
VDD Range
IDD
IDD
PDISS
PSS
PSS
VIH = VDD or VIL = 0 V
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
VIH = VDD or VIL = 0 V, VDD = 5.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
2.7
0.01
0.9
BW_10K
THDW
tS
eNWB
CT
R = 10 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ± 1% Error Band
RWB = 5 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
600
0.003
2
9
–65
0.0002
0.006
5.5
5
4
27.5
0.001
0.03
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
%
µs
nV/√Hz
dB
NOTES
11
Typicals represent average readings at 25°C and VDD = 5 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.
1
IW = 50 µA for VDD = 3 V and IW = 400 µA for VDD = 5 V for the 10 kΩ versions.
13
VAB = VDD, Wiper (VW) = No Connect.
14
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
1
DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
1
resistor terminals are left open circuit.
17
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I DD versus logic voltage.
19
PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V DD = 5 V.
11
Measured at a VW pin where an adjacent V W pin is making a full-scale voltage change.
Specifications subject to change without notice.
–2–
REV. C
AD8400/AD8402/AD8403
SPECIFICATIONS (V
DD
= 3 V 10% or 5 V 10%, VA = VDD, VB = 0 V, –40C ≤ TA ≤ +125C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS–50 k and 100 k VERSIONS
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2
R-DNL
RWB, VA = No Connect
Resistor Nonlinearity2
R-INL
RWB, VA = No Connect
RAB
TA = 25°C, Model: AD840XYY50
Nominal Resistance3
TA = 25°C, Model: AD840XYY100
RAB
Resistance Tempco
∆RAB/∆T
VAB = VDD, Wiper = No Connect
Wiper Resistance
RW
IW = 1 V/R
Nominal Resistance Match
∆R/RAB
CH 1 to 2, 3, or 4, VAB = VDD, TA = 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity4
INL
DNL
VDD = 5 V
Differential Nonlinearity4
DNL
VDD = 3 V TA = 25°C
DNL
VDD = 3 V TA = –40°C, +85°C
Voltage Divider Tempco
∆VW/∆T
Code = 80H
Full-Scale Error
VWFSE
Code = FFH
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
Capacitance6 Wx
Shutdown Current7
Shutdown Wiper Resistance
VA, B, W
CA, B
CW
IA_SD
RW_SD
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk11
Min
Typ1
Max
Unit
–1
–2
35
70
± 1/4
± 1/2
50
100
500
53
0.2
+1
+2
65
130
LSB
LSB
kΩ
kΩ
ppm/°C
Ω
%
±1
± 1/4
± 1/4
± 1/2
15
–0.25
+0.1
+4
+1
+1
+1.5
8
–4
–1
–1
–1.5
–1
0
0
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
RL = 2.2 kΩ to VDD
IOL = 1.6 mA, VDD = 5 V
VIN = 0 V or 5 V, VDD = 5 V
100
1
0
+1
VDD
15
80
0.01
100
5
200
2.4
0.8
2.1
0.6
VDD – 0.1
0.4
±1
5
VDD Range
IDD
IDD
PDISS
PSS
PSS
VIH = VDD or VIL = 0 V
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
VIH = VDD or VIL = 0 V, VDD = 5.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
2.7
0.01
0.9
BW_50K
BW_100K
THDW
tS _50K
tS _100K
eNWB_50K
eNWB _100K
CT
R = 50 kΩ
R = 100 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ± 1% Error Band
VA = VDD, VB = 0 V, ± 1% Error Band
RWB = 25 kΩ, f = 1 kHz, RS = 0
RWB = 50 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
125
71
0.003
9
18
20
29
–65
0.0002
0.006
5.5
5
4
27.5
0.001
0.03
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
kHz
%
µs
µs
nV/√Hz
nV/√Hz
dB
NOTES
11
Typicals represent average readings at 25°C and VDD = 5 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.
1
IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
13
VAB = VDD, Wiper (VW) = No Connect.
14
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
1
DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
1
resistor terminals are left open circuit.
17
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I DD versus logic voltage.
19
PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V DD = 5 V.
11
Measured at a VW pin where an adjacent V W pin is making a full-scale voltage change.
Specifications subject to change without notice.
REV. C
–3–
or 5 V 10%, V = V , V = 0 V,
AD8400/AD8402/AD8403–SPECIFICATIONS (V–40C= 3≤ VT ≤ 10%
+125C unless otherwise noted.)
DD
A
DD
B
A
ELECTRICAL CHARACTERISTICS–1 k VERSION
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
R-DNL
RWB, VA = No Connect
Resistor Nonlinearity2
R-INL
RWB, VA = No Connect
Nominal Resistance3
RAB
TA = 25°C, Model: AD840XYY1
VAB = VDD, Wiper = No Connect
Resistance Tempco
∆RAB/∆T
Wiper Resistance
RW
IW = 1 V/RAB
Nominal Resistance Match
∆R/RAB
CH 1 to 2, VAB = VDD, TA = 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
INL
Integral Nonlinearity4
Differential Nonlinearity4
DNL
VDD = 5 V
DNL
VDD = 3 V, TA = 25°C
Voltage Divider Temperature Coefficent
∆VW/∆T
Code = 80H
Code = FFH
Full-Scale Error
VWFSE
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
Capacitance6 Wx
Shutdown Supply Current7
Shutdown Wiper Resistance
VA, B, W
CA, B
CW
IA_SD
RW_SD
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk11
Min
Typ1
Max
Unit
–5
–4
0.8
–1
± 1.5
1.2
700
53
0.75
+3
+4
1.6
LSB
LSB
kΩ
ppm/°C
Ω
%
±2
–1.5
–2
25
–12
6
+6
+2
+5
8
–6
–4
–5
–20
0
0
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
RL = 2.2 kΩ to VDD
IOL = 1.6 mA, VDD = 5 V
VIN = 0 V or 5 V, VDD = 5 V
100
2
0
10
VDD
75
120
0.01
50
5
100
2.4
0.8
2.1
0.6
VDD – 0.1
0.4
±1
5
VDD Range
IDD
IDD
PDISS
PSS
PSS
VIH = VDD or VIL = 0 V
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
VIH = VDD or VIL = 0 V, VDD = 5.5 V
∆VDD = 5 V ± 10%
∆VDD = 3 V ± 10%
2.7
0.01
0.9
BW_1K
THDW
tS
eNWB
CT
R = 1 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ± 1% Error Band
RWB = 500 Ω, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
5,000
0.015
0.5
3
–65
0.0035
0.05
5.5
5
4
27.5
0.008
0.13
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
%
µs
nV/√Hz
dB
NOTES
11
Typicals represent average readings at 25°C and V DD = 5 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. See TPC 29 test circuit.
1
IW = 500 µA for V DD = 3 V and IW = 2.5 mA for V DD = 5 V for 1 kΩ version.
13
VAB = VDD, Wiper (VW) = No Connect.
14
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
17
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I DD versus logic voltage.
19
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V DD = 5 V.
11
Measured at a VW pin where an adjacent V W pin is making a full-scale voltage change.
Specifications subject to change without notice.
–4–
REV. C
AD8400/AD8402/AD8403
SPECIFICATIONS (V
DD
= 3 V 10% or 5 V 10%, VA = VDD, VB = 0 V, –40C ≤ TA ≤ +125C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS–ALL VERSIONS
Parameter
Symbol
Conditions
Min
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH
tCS1
Clock Level High or Low
10
5
5
1
10
10
50
0
10
Typ1
Max
Unit
2, 3
SWITCHING CHARACTERISTICS
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay4
CS Setup Time
CS High Pulsewidth
Reset Pulsewidth
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
RL = 1 kΩ to 5 V, CL ≤ 20 pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
NOTES
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
3
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using V DD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of 1 V/ µs should be maintained.
4
Propagation Delay depends on value of V DD, RL, and CL—see Applications section.
Specifications subject to change without notice.
SDI
(DATA IN)
1
Ax OR Dx
Ax OR Dx
0
tDS
1
A1
SDI
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
(DATA OUT)
0
1
1
A'x OR D'x
0
tPD_MIN
CLK
0
tPD_MAX
tCH
1
DAC REGISTER LOAD
1
tCS1
CLK
CS
0
0
VOUT
tDH
A'x OR D'x
tCSS
1
VDD
tCL
tCSH
CS
tCSW
0
0V
tS
VDD
1 %
VOUT
0V
Figure 2a. Timing Diagram
1% ERROR BAND
Figure 2b. Detail Timing Diagram
1
tRS
RS
0
VOUT
tS
VDD
VDD/2
1%
1% ERROR BAND
Figure 2c. Reset Timing Diagram
REV. C
–5–
AD8400/AD8402/AD8403
ABSOLUTE MAXIMUM RATINGS*
Table I. Serial Data Word Format
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Input and Output Voltage to GND . . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Resistance (θJA)
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . . 180°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
ADDR
B9
B8
B7
B6
B5
DATA
B4 B3
B2
B1
B0
A1
MSB
29
D7 D6
MSB
27
D5
D4
D2
D1
D0
LSB
20
A0
LSB
28
D3
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8400/AD8402/AD8403 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. C
AD8400/AD8402/AD8403
ORDERING GUIDE
Model
Number of
Channels
End-to-End
RAB (k)
Temperature
Range (C)
Package
Description
Package
Option*
Number of
Devices per
Container
Branding
Information
AD8400AN10
AD8400AR10
AD8402AN10
AD8402AR10
AD8402ARU10
AD8402ARU10-REEL
AD8403AN10
AD8403AR10
AD8403ARU10
AD8403ARU10-REEL
1
1
2
2
2
2
4
4
4
4
10
10
10
10
10
10
10
10
10
10
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
PDIP-8
SO-8
PDIP-14
SO-14
TSSOP-14
TSSOP-14
PDIP-24
SOIC-24
TSSOP-24
TSSOP-24
N-8
SO-8
N-14
SO-14
RU-14
RU-14
N-24
SOL-24
RU-24
RU-24
50
98
25
56
96
2,500
15
31
63
2,500
8400A10
8400A10
8400A10
8400A10
8400A10
8400A10
8400A10
8400A10
8400A10
8400A10
AD8400AN50
AD8400AR50
AD8402AN50
AD8402AR50
AD8402ARU50
AD8402ARU50-REEL
AD8403AN50
AD8403AR50
AD8403ARU50
AD8403ARU50-REEL
1
1
2
2
2
2
4
4
4
4
50
50
50
50
50
50
50
50
50
50
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
PDIP-8
SO-8
PDIP-14
SO-14
TSSOP-14
TSSOP-14
PDIP-24
SOIC-24
TSSOP-24
TSSOP-24
N-8
SO-8
N-14
SO-14
RU-14
RU-14
N-24
SOL-24
RU-24
RU-24
50
98
25
56
96
2,500
15
31
63
2,500
8400A50
8400A50
8400A50
8400A50
8400A50
8400A50
8400A50
8400A50
8400A50
8400A50
AD8400AN100
AD8400AR100
AD8402AN100
AD8402AR100
AD8402ARU100
AD8402ARU100-REEL
AD8403AN100
AD8403AR100
AD8403ARU100
AD8403ARU100-REEL
1
1
2
2
2
2
4
4
4
4
100
100
100
100
100
100
100
100
100
100
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
PDIP-8
SO-8
PDIP-14
SO-14
TSSOP-14
TSSOP-14
PDIP-24
SOIC-24
TSSOP-24
TSSOP-24
N-8
SO-8
N-14
SO-14
RU-14
RU-14
N-24
SOL-24
RU-24
RU-24
50
98
25
56
96
2,500
15
31
63
2,500
8400A100
8400A100
8400A100
8400A100
8400A100
8400A100
8400A100
8400A100
8400A100
8400A100
AD8400AN1
AD8400AR1
AD8402AN1
AD8402AR1
AD8402ARU1
AD8402ARU1-REEL
AD8403AN1
AD8403AR1
AD8403ARU1
AD8403ARU1-REEL
1
1
2
2
2
2
4
4
4
4
1
1
1
1
1
1
1
1
1
1
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
–40 to +125
PDIP-8
SO-8
PDIP-14
SO-14
TSSOP-14
TSSOP-14
PDIP-24
SOIC-24
TSSOP-24
TSSOP-24
N-8
SO-8
N-14
SO-14
RU-14
RU-14
N-24
SOL-24
RU-24
RU-24
50
98
25
56
96
2,500
15
31
63
2,500
8400A1
8400A1
8400A1
8400A1
8400A1
8400A1
8400A1
8400A1
8400A1
8400A1
*N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO.
The AD8400, AD8402, and AD8403 contain 720 transistors.
REV. C
–7–
AD8400/AD8402/AD8403
PIN CONFIGURATIONS
B1 1
GND 2
AD8400 PIN FUNCTION DESCRIPTIONS
8 A1
AD8400
7 W1
TOP VIEW
CS 3 (Not to Scale) 6 VDD
SDI 4
14 B1
B2 2
13 A1
A2 3
12 W1
AD8402
W2 4
TOP VIEW 11 VDD
(Not to Scale)
10 RS
DGND 5
SHDN 6
9 CLK
CS 7
24 B1
B2 2
23 A1
A2 3
22 W1
W2 4
21 AGND1
A4 7
Description
1
2
3
B1
GND
CS
4
5
6
SDI
CLK
VDD
7
8
W1
A1
Terminal B RDAC
Ground
Chip Select Input, Active Low. When CS
returns high, data in the serial input register
is loaded into the DAC register.
Serial Data Input
Serial Clock Input, Positive Edge Triggered.
Positive power supply, specified for operation
at both 3 V and 5 V.
Wiper RDAC, Addr = 002
Terminal A RDAC
8 SDI
AGND2 1
B4 6
Name
5 CLK
AGND 1
AGND4 5
Pin
AD8403
TOP VIEW
(Not to Scale)
W4 8
AD8403 PIN FUNCTION DESCRIPTIONS
20 B3
19 A3
18 W3
17 AGND3
DGND 9
16 VDD
SHDN 10
15 RS
CS 11
14 CLK
SDI 12
13 SDO
AD8402 PIN FUNCTION DESCRIPTIONS
Pin
Name
Description
1
2
3
4
5
6
AGND
B2
A2
W2
DGND
SHDN
7
CS
8
9
10
SDI
CLK
RS
11
V DD
12
13
14
W1
A1
B1
Analog Ground*
Terminal B RDAC #2
Terminal A RDAC #2
Wiper RDAC #2, Addr = 012.
Digital Ground*
Terminal A Open Circuit. Shutdown controls
Variable Resistors #1 and #2.
Chip Select Input, Active Low. When CS
returns high, data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register.
Serial Data Input
Serial Clock Input, Positive Edge Triggered.
Active low reset to midscale; sets RDAC
registers to 80H.
Positive power supply, specified for operation
at both 3 V and 5 V.
Wiper RDAC #1, Addr = 002.
Terminal A RDAC #1
Terminal B RDAC #1
*All AGNDs must be connected to DGND.
Pin
Name
Description
1
2
3
4
5
6
7
8
9
10
AGND2
B2
A2
W2
AGND4
B4
A4
W4
DGND
SHDN
11
CS
12
13
SDI
SDO
14
15
CLK
RS
16
V DD
17
18
19
20
21
22
23
24
AGND3
W3
A3
B3
AGND1
W1
A1
B1
Analog Ground #2*
Terminal B RDAC #2
Terminal A RDAC #2
Wiper RDAC #2, Addr = 012.
Analog Ground #4*
Terminal B RDAC #4
Terminal A RDAC #4
Wiper RDAC #4, Addr = 112.
Digital Ground*
Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors #1
through #4.
Chip Select Input, Active Low. When CS
returns high, data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
Serial Data Input
Serial Data Output, Open Drain transistor
requires pull-up resistor.
Serial Clock Input, Positive Edge Triggered
Active Low reset to midscale; sets RDAC
registers to 80H.
Positive power supply, specified for
operation at both 3 V and 5 V.
Analog Ground #3*
Wiper RDAC #3, Addr = 102
Terminal A RDAC #3
Terminal B RDAC #3
Analog Ground #1*
Wiper RDAC #1, Addr = 002
Terminal A RDAC #1
Terminal B RDAC #1
*All AGNDs must be connected to DGND.
–8–
REV. C
Typical Performance Characteristics–AD8400/AD8402/AD8403
5
10
VDD = 3V OR 5V
RAB = 10k
4
4
40H
CODE = 10H
2
1
RWB
0
32
64
0
0
96 128 160 192 224 256
CODE – Decimal
TA = 25C
VDD = 5V
2
3
4
5
IWB CURRENT – mA
6
–1
7
60
FREQUENCY
0
–0.5
–1
0
TA = +85C
NOMINAL RESISTANCE – k
RAB (END-TO-END)
12
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0
WIPER RESISTANCE – TPC 7. 100 kΩ Wiper-ContactResistance Histogram
REV. C
8
6
RWB (WIPER-TO-END)
CODE = 80H
4
2
RAB = 10k
0
–75 –50 –25 0
25 50 75
TEMPERATURE – C
100 125
TPC 8. Nominal Resistance vs.
Temperature
–9–
24
0
32 64 96 128 160 192 224 256
DIGITAL INPUT CODE – Decimal
10
SS = 184 UNITS
VDD = 4.5V
TA = 25C
36
12
35 37 39 41 43 45 47 49 51 53 55
WIPER RESISTANCE – TPC 6. 50 k⍀ Wiper-ContactResistance Histogram
TPC 5. Potentiometer Divider
Nonlinearity Error vs. Code
60
24
SS = 184 UNITS
VDD = 4.5V
TA = 25C
48
TA = +25C
TA = –40C
TPC 4. 10 kΩ Wiper-ContactResistance Histogram
32 64 96 128 160 192 224 256
DIGITAL INPUT CODE – Decimal
TPC 3. Resistance Step Position
Nonlinearity Error vs. Code
0.5
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0
36
0
VDD = 5V
WIPER RESISTANCE – FREQUENCY
TA = +25C
–0.5
POTENTIOMETER MODE TEMPCO – ppm/C
12
INL NONLINEARITY ERROR – LSB
FREQUENCY
24
48
TA = –40C
1
SS = 1205 UNITS
VDD = 4.5V
TA = 25C
36
0
1
TA = +85C
0
TPC 2. Resistance Linearity vs.
Conduction Current
60
48
05H
RWA
TPC 1. Wiper to End Terminal
Resistance vs. Code
0
20H
3
0.5
R-INL ERROR – LSB
VWB VOLTAGE – V
RESISTANCE – k
6
2
VDD = 5V
FFH
8
0
1
80H
70
VDD = 5V
TA = –40C/+85C
VA = 2.00V
VB = 0V
60
50
40
30
20
10
0
–10
0
32
64
96 128 160 192 224 256
CODE – Decimal
TPC 9. DVWB/DT Potentiometer
Mode Tempco
AD8400/AD8402/AD8403
6
VDD = 5V
TA = –40C/+85C
VA = NO CONNECT
RWB MEASURED
600
500
400
TPC 10. ∆RWB /∆T Rheostat Mode
Tempco
04
02
TPC 11. One Position Step Change at
Half-Scale (Code 7FH to 80H)
TA = +25C
SEE TEST CIRCUIT 7
–54
10
TIME 500ns/DIV
100
6
CODE = 80H
VDD = 5V
SS = 158 UNITS
0.50
1k
10k
100k
FREQUENCY – Hz
–6
GAIN – dB
0
80H
–12
OUTPUT
AVG
–0.25
40H
–18
20H
–24
10H
–30
08H
–36
AVG – 2 SIGMA
04H
–42
–0.50
INPUT
02H
–48
–0.75
0
200
500
600
100
300
400
HOURS OF OPERATION AT 150C
TPC 13. Long-Term Drift
Accelerated by Burn-In
TPC 14. Large Signal Settling Time
6
–6
–12
VOUT
(50mV/DIV)
SEE TEST CIRCUIT 5
–18
–24
–30
–36
0.01
–42
SEE TEST CIRCUIT 6
100
1k
10k
FREQUENCY – Hz
–48
100k
TPC 16. Total Harmonic Distortion
Plus Noise vs. Frequency
TIME 200ns/DIV
TPC 17. Digital Feedthrough vs. Time
–10–
1M
CODE = FFH
0
GAIN – dB
THD + NOISE – %
100k
10k
FREQUENCY – Hz
TPC 15. 50 kΩ Gain vs. Frequency
vs. Code
FILTER = 22kHz
VDD = 5V
TA = 25C
0.1
0.001
10
01H
–54
1k
TIME 500s/DIV
10
1
1M
CODE = FFH
0
AVG + 2 SIGMA
0.25
01
TPC 12. 10 kΩ Gain vs. Frequency
0.75
RWB RESISTANCE – %
08
–30
–48
96 128 160 192 224 256
CODE – Decimal
10
–24
–42
0
64
20
–18
–36
CS
(5V/DIV)
32
40
–12
RW
(20mV/DIV)
200
–100
0
80
–6
300
100
CODE = FF
0
GAIN – dB
RHEOSTAT MODE TEMPCO – ppm/C
700
–54
1k
80H
40H
20H
10H
08H
04H
02H
01H
10k
100k
FREQUENCY – Hz
1M
TPC 18. 100 kΩ Gain vs. Frequency
vs. Code
REV. C
10
SEE TEST CIRCUIT 7
CODE = 80H
VDD = 5V
TA = 25C
R = 50k
60
VDD = 5V
0.1
1k
100k
10k
FREQUENCY – Hz
20
0.01
0
1M
SEE TEST CIRCUIT 4
0
100
5
1
2
3
4
DIGITAL INPUT VOLTAGE – V
TPC 20. Supply Current vs.
Digital Input Voltage
12
0
–6
f–3dB = 71kHz, R = 100k
–12
–18
f–3dB = 125kHz, R = 50k
–24
–30
VIN = 100mV rms
VDD = 5V
RL = 1M
–36
–42
1k
10k
100k
FREQUENCY – Hz
1000
800
600
400
TA = 25C
TA = 25C
VDD = 2.7V
B – VDD = 3.3V
CODE = 55H
120
100
C – VDD = 5.5V
CODE = FFH
D – VDD = 3.3V
CODE = FFH
0
1k
0
10M
–90 VDD = 5V
TA = 25C
WIPER SET AT
HALF-SCALE 80H
IDD – SUPPLY CURRENT – A
–45
IA SHUTDOWN CURRENT – nA
GAIN – dB
PHASE – Degrees
0
10
2
3
4
VBIAS – V
5
6
LOGIC INPUT
VOLTAGE = 0, VDD
0.1
VDD = 5.5V
0.01
VDD = 3.3V
1M
100k 200k 400k
2M
4M 6M 10M
FREQUENCY – Hz
1
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE – C
TPC 25. 1 kΩ Gain and Phase
vs. Frequency
TPC 26. Shutdown Current vs.
Temperature
REV. C
1
1
VDD = 5V
–20
0
TPC 24. AD8403 Incremental Wiper
ON Resistance vs. VDD
100
–10
SEE TEST CIRCUIT 3
20
D
100k
1M
FREQUENCY – Hz
TPC 23. Supply Current vs.
Clock Frequency
0
VDD = 5.5V
60
40
C
10k
80
B
200
TPC 22. –3 dB Bandwidths
1M
140
A
1M
10k
100k
FREQUENCY – Hz
160
A – VDD = 5.5V
CODE = 55H
RON – IDD – SUPPLY CURRENT – µA
f–3dB = 700kHz, R = 10k
1k
TPC 21. Power Supply Rejection
vs. Frequency
1200
6
40
VDD = 3V
R = 100k
100
PSRR – dB
R = 10k
10
VDD = +5V DC 1V p-p AC
TA = 25C
CODE = 80H
CL = 10pF
VA = 4V, VB = 0V
1
TPC 19. Normalized Gain Flatness vs.
Frequency
GAIN – dB
80
TA = 25C
IDD – SUPPLY CURRENT – mA
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
AD8400/AD8402/AD8403
–11–
0.001
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE – C
TPC 27. Supply Current vs.
Temperature
AD8400/AD8402/AD8403
TEST CIRCUITS
A
DUT
A
V+
V+ = VDD
1LSB = V+/256
VOUT
OP279
OFFSET
GND
VMS
5V
W
~ VIN
W
B
B
DUT
2.5V DC
Test Circuit 1. Potentiometer Divider Nonlinearity
Error (INL, DNL)
Test Circuit 5. Inverting Programmable Gain
5V
VOUT
NO CONNECT
VIN
IW
DUT
A
W
OP279
~
OFFSET
GND
B
W
A
B
DUT
2.5V
VMS
Test Circuit 6. Noninverting Programmable Gain
Test Circuit 2. Resistor Position Nonlinearity
Error (Rheostat Operation; R-INL, R-DNL)
+15V
A
IMS
VIN
DUT
A
V+
W
IW = 1V/RNOMINAL
V+
VMS
WHERE VW1 = VMS WHEN IW = 0
AND VW2 = VMS WHEN IW = 1/R
VW
B
VDD
VW2 – [VW1 + IW (RAW II RBW)]
RW = ––––––––––––––––––––––––––
IW
~
2.5V
–15V
Test Circuit 7. Gain vs. Frequency
RSW = 0.1V
ISW
DUT
VA
V+
~
B
W
V+ = VDD 10%
W
VMS
PSRR (dB) = 20LOG
VOUT
OP42
B
OFFSET
GND
Test Circuit 3. Wiper Resistance
VDD A
W
DUT
B
∆V
MS
( –––––
)
∆V
∆VMS%
PSS (%/%) = –––––––
∆VDD%
CODE = ØØH
+
ISW
–
0.1V
DD
VBIAS
Test Circuit 4. Power Supply Sensitivity (PSS, PSRR)
A = NC
Test Circuit 8. Incremental ON Resistance
–12–
REV. C
AD8400/AD8402/AD8403
OPERATION
The AD8400/AD8402/AD8403 provide a single, dual, and quad
channel, 256-position digitally controlled variable resistor (VR)
device. Changing the programmed VR settings is accomplished by
clocking in a 10-bit serial data word into the SDI (Serial Data Input)
pin. The format of this data word is two address bits, MSB first,
followed by eight data bits, MSB first. Table I provides the serial
register data word format. The AD8400/AD8402/AD8403 has the
following address assignments for the ADDR decode, which
determines the location of VR latch receiving the serial register
data in Bits B7 through B0:
VR# = A1 × 2 + A0 + 1
(1)
The single-channel AD8400 requires A1 = A0 = 0. The dualchannel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. The serial clock running at
10 MHz makes it possible to load all four VRs in under 4 µs
(10 × 4 × 100 ns) for the AD8403. The exact timing requirements
are shown in Figures 2a, 2b, and 2c.
The AD8402/AD8403 resets to midscale by asserting the RS
pin, simplifying initial conditions at power up. Both parts have a
power shutdown SHDN pin that places the VR in a zero power
consumption state where terminals Ax are open circuited and the
wiper Wx is connected to Bx resulting in only leakage currents
being consumed in the VR structure. In shutdown mode the VR
latch settings are maintained so that returning to operational mode
from power shutdown, the VR settings return to their previous
resistance values. The digital interface is still active in shutdown,
except that SDO is deactivated. Code changes in the registers can
be made that will produce new wiper positions when the device is
taken out of shutdown.
RS
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
Ax
RS
RS
Wx
RS
Bx
RS = RNOMINAL/256
Figure 3. AD8402/AD8403 Equivalent VR (RDAC) Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the VR (RDAC) between terminals A and
B is available with values of 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
final digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance
(RAB) of the VR has 256 contact points accessed by the wiper
terminal, plus the B terminal contact. The 8-bit data word in the
RDAC latch is decoded to select one of the 256 possible settings.
The wiper’s first connection starts at the B terminal for data 00H.
This B terminal connection has a wiper contact resistance of 50 Ω.
The second connection (10 kΩ part) is the first tap point located
at 89 Ω [= RAB (nominal resistance)/256 + RW = 39 Ω + 50 Ω] for
data 01H. The third connection is the next tap point representing
78 + 50 = 128 Ω for data 02H. Each LSB data value increase
moves the wiper up the resistor ladder until the last tap point is
reached at 10,011 Ω. The wiper does not directly connect to the
B terminal. See Figure 3 for a simplified diagram of the equivalent RDAC circuit.
The AD8400 contains one RDAC, the AD8402 contains two
independent RDACs, and the AD8403 contains four independent
RDACs. The general transfer equation that determines the digitally programmed output resistance between Wx and Bx is:
RWB ( Dx ) = ( Dx ) / 256 × RAB + RW
where Dx is the data contained in the 8-bit RDAC# latch, and
RAB is the nominal end-to-end resistance.
For example, when VB = 0 V and when the A terminal is open
circuit, the following output resistance values will be set for the
following RDAC latch codes (applies to 10 kΩ potentiometers):
D
(Dec)
RWB
()
Output State
255
128
1
0
10,011
5,050
89
50
Full Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale (Wiper Contact Resistance)
Note in the zero-scale condition a finite wiper resistance of 50 Ω
is present. Care should be taken to limit the current flow between
W and B in this state to a maximum value of 5 mA to avoid
degradation or possible destruction of the internal switch contact.
Like the mechanical potentiometer the RDAC replaces, it is totally
symmetrical. The resistance between the wiper W and terminal
A also produces a digitally controlled complementary resistance
RWA. When these terminals are used, the B terminal can be tied
to the wiper or left floating. Setting the resistance value for RWA
starts at a maximum value of resistance and decreases as the data
loaded in the RDAC latch is increased in value. The general transfer
equation for this operation is:
RWA ( DX ) = (256 − DX ) 256 × RAB + RW
REV. C
(2)
–13–
(3)
AD8400/AD8402/AD8403
where Dx is the data contained in the 8-bit RDAC# latch, and
RAB is the nominal end-to-end resistance. For example, when
VA = 0 V and B terminal is open circuit, the following output
resistance values will be set for the following RDAC latch codes
(applies to 10 kΩ potentiometers):
D
(Dec)
RWA
()
Output State
255
128
1
0
89
5,050
10,011
10,050
Full Scale
Midscale (RS = 0 Condition)
1 LSB
Zero Scale
VDD
CS
CLK
A1
D7
EN
ADDR
DEC
A1
A0
W1
RDAC
LATCH
#1
D0
B1
D7
10-BIT
SER
REG
SDI
8
GND
a.
The typical distribution of RAB from channel to channel matches
within ± 1%. However, device-to-device matching is process lotdependent, having a ± 20% variation. The change in RAB with
temperature has a positive 500 ppm/°C temperature coefficient.
CS
The wiper-to-end-terminal resistance temperature coefficient has
the best performance over the 10% to 100% of adjustment range
where the internal wiper contact switches do not contribute any
significant temperature related errors. The graph in TPC 10 shows
the performance of RWB tempco versus code: using the trimmer with
codes below 32 results in the larger temperature coefficients plotted.
AD8402
CLK
EN
ADDR
DEC
A1
A0
SDI
D7
A1
RDAC
LATCH
#1
R
D0
W1
B1
RDAC
LATCH
#2
R
D0
D0
DI
A4
D7
8
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to 5 V and B terminal to
ground produces an output voltage at the wiper starting at zero
volts up to 1 LSB less than 5 V. Each LSB of voltage is equal to
the voltage applied across terminal AB divided by the 256
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
VDD
D7
10-BIT
SER
REG
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
VW ( DX ) = DX 256 × VAB + VB
AD8400
DI D0
W4
B4
SHDN
RS
DGND
AGND
b.
VDD
CS
CLK
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors, not
the absolute value; therefore, the temperature drift improves to
15 ppm/°C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases due to the contributions of the
CMOS switch wiper resistance becoming an appreciable portion of
the total resistance from Terminal B to the wiper. See TPC 9 for
a plot of potentiometer tempco performance versus code setting.
EN
SDO
DO
ADDR
DEC
A1
A0
D7
D0
SER
REG
SDI
A1
D7
(4)
DI
RDAC
LATCH
#1
R
W1
B1
AD8403
A4
D7
D0
8
D0
W4
RDAC
LATCH
#4
R
B4
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contain a standard SPI compatible three-wire serial input control interface. The three inputs
are clock (CLK), CS and serial data input (SDI). The positiveedge sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. For best
results use logic transitions faster than 1 V/µs. Standard logic
families work well. If mechanical switches are used for product
evaluation, they should be debounced by a flip-flop or other
suitable means. The Figure 4 block diagrams show more detail
of the internal digital circuitry. When CS is taken active low, the
clock loads data into the 10-bit serial register on each positive
clock edge (see Table II).
–14–
SHDN
DGND
RS
AGND
c.
Figure 4. Block Diagrams
REV. C
AD8400/AD8402/AD8403
Table II. Input Logic Control Truth Table
CLK CS
RS
SHDN Register Activity
L
P
H
H
H
H
L
L
X
P
H
H
X
X
H
X
H
L
H
H
X
X
H
H
P
H
H
L
AD8403
CS
RDAC 1
RDAC 2
ADDR
DECODE
RDAC 4
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin.
The tenth previously entered bit is
shifted out of the SDO pin.
Load SR data into RDAC latch
based on A1, A0 decode (Table III).
No Operation
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared.
Latches all RDAC latches to 80H.
Open circuits all resistor
A-terminals, connects W to B,
turns off SDO output transistor.
CLK
SERIAL
REGISTER
SDI
Figure 5. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. In the case of the
AD8403 four separate 10-bit data words must be clocked in to
change all four VR settings.
SHDN
CS
SDI
SDO
SERIAL
REGISTER
D
Q
CK RS
CLK
RS
NOTE: P = positive edge, X = don’t care, SR = shift register.
The serial data-output (SDO) pin contains an open drain n-channel
FET. This output requires a pull-up resistor in order to transfer data
to the next package’s SDI pin. The pull-up resistor termination
voltage may be larger than the VDD supply (but less than max
VDD of 8 V) of the AD8403 SDO output device, e.g., the AD8403
could operate at VDD = 3.3 V and the pull-up for interface to the
next device could be set at 5 V. This allows for daisy-chaining
several RDACs from a single processor serial data line. The
clock period needs to be increased when using a pull-up resistor
to the SDI pin of the following device in the series. Capacitive
loading at the daisy-chain node SDO–SDI between devices must
be accounted for to successfully transfer data. When daisy chaining
is used, the CS should be kept low until all the bits of every package
are clocked into their respective serial registers ensuring that the
address bits and data bits are in the proper decoding location.
This would require 20 bits of address and data complying to the
word format provided in Table I if two AD8403 four-channel
RDACs are daisy-chained. Note, only the AD8403 has a SDO
pin. During shutdown SHDN the SDO output pin is forced to
the off (logic high) state to disable power dissipation in the pull-up
resistor. See Figure 6 for equivalent SDO output circuit schematic.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 10 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four (AD8403)
positive edge triggered RDAC latches. See Figure 5 detail and
Table III Address Decode Table.
Figure 6. Detail SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 7a. This structure
applies to digital pins CS, SDI, SDO, RS, SHDN, CLK. The
digital input ESD protection allows for mixed power supply
applications where 5 V CMOS logic can be used to drive an
AD8400/AD8402 or AD8403 operating from a 3 V power supply.
The analog pins A, B, and W are protected with a 20 Ω series
resistor and parallel Zener. (see Figure 7b).
DIGITAL
PINS
A0
Latch Decoded
0
0
1
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3 AD8403 Only
RDAC#4 AD8403 Only
REV. C
LOGIC
Figure 7a. Equivalent ESD Protection Circuits
20
A, B, W
Figure 7b. Equivalent ESD Protection Circuit
(Analog Pins)
RDAC
10k
A
B
CA
CW
120pF
CA = 90.4pF ( DW ) + 30pF
256
Table III. Address Decode Table
A1
1k
CB
CB = 90.4pF (1 – DW ) + 30pF
256
W
Figure 8. RDAC Circuit Simulation Model for
RDAC =10 kΩ
–15–
AD8400/AD8402/AD8403
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA
A 0 {DW/256*90.4E-12+30E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW
W 0 120E-12
RBW W B {DW/256*RDAC+50}
CB
B 0 {(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
The total harmonic distortion plus noise (THD+N) is measured
at 0.003% in an inverting op amp circuit using an offset ground
and a rail-to-rail OP279 amplifier, Test Circuit 5. Thermal noise is
primarily Johnson noise, typically 9 nV/√Hz for the 10 kΩ version
at f = 1 kHz. For the 100 kΩ device, thermal noise becomes
29 nV/√Hz. Channel-to-channel crosstalk measures less than
–65 dB at f = 100 kHz. To achieve this isolation, the extra ground
pins provided on the package to segregate the individual RDACs
must be connected to circuit ground. AGND and DGND pins
should be at the same voltage potential. Any unused potentiometers in a package should be connected to ground. Power
supply rejection is typically –35 dB at 10 kHz (care is needed to
minimize power supply ripple in high accuracy applications).
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and the
rheostat (2-terminal configuration) connections shown in Test
Circuits 1 and 2 (see page 11).
Certain boundary conditions must be satisfied for proper AD8400/
AD8402/AD8403 operation. First, all analog signals must remain
within the 0 to VDD range used to operate the single-supply
AD8400/AD8402/AD8403 products. For standard potentiometer
divider applications, the wiper output can be used directly. For
low resistance loads, buffer the wiper with a suitable rail-to-rail
op amp such as the OP291 or the OP279. Second, for ac signals
and bipolar dc adjustment applications, a virtual ground will
generally be needed. Whatever method is used to create the
virtual ground, the result must provide the necessary sink and
source current for all connected loads, including adequate bypass
capacitance. Test Circuit 5 (see page 11) shows one channel of
the AD8402 connected in an inverting programmable gain
amplifier circuit. The virtual ground is set at 2.5 V, which allows
the circuit output to span a ± 2.5 volt range with respect to virtual
ground. The rail-to-rail amplifier capability is necessary for the
widest output swing. As the wiper is adjusted from its midscale
reset position (80H) toward the A terminal (code FFH), the voltage
gain of the circuit is increased in successfully larger increments.
Alternatively, as the wiper is adjusted toward the B terminal
(code 00H), the signal becomes attenuated. The plot in Figure 9
shows the wiper settings for a 100:1 range of voltage gain (V/V).
Note the ± 10 dB of pseudo-logarithmic gain around 0 dB (1 V/V).
This circuit is mainly useful for gain adjustments in the range of
0.14 V/V to 4 V/V; beyond this range the step sizes become very
large and the resistance of the driving circuit can become a
significant term in the gain equation.
APPLICATIONS
The digital potentiometer (RDAC) allows many of the applications
of trimming potentiometers to be replaced by a solid-state solution offering compact size and freedom from vibration, shock and
open contact problems encountered in hostile environments. A
major advantage of the digital potentiometer is its programmability. Any settings can be saved for later recall in system memory.
256
224
DIGITAL CODE – Decimal
The ac characteristics of the RDACs are dominated by the internal
parasitic capacitances and the external capacitive loads. The –3 dB
bandwidth of the AD8403AN10 (10 kΩ resistor) measures 600 kHz
at half scale as a potentiometer divider. TPC 22 provides the large
signal BODE plot characteristics of the three available resistor
versions 10 kΩ, 50 kΩ, and 100 kΩ. The gain flatness versus
frequency graph, TPC 25, predicts filter applications performance.
A parasitic simulation model has been developed, and is shown
in Figure 8. Listing I provides a macro model net list for the
10 kΩ RDAC:
192
160
128
96
64
32
0
0.1
1.0
10
INVERTING GAIN – V/V
Figure 9. Inverting Programmable Gain Plot
–16–
REV. C
AD8400/AD8402/AD8403
ACTIVE FILTER
40
–0.16
0
–20
–40
–80
20
100
1k
10k
FREQUENCY – Hz
100k 200k
Figure 11. Programmed Center Frequency Band-Pass
Response
40
–19.01
10k
B
A
–60
10k
RDAC4
20.0000 k
20
AMPLITUDE – dB
One of the standard circuits used to generate a low-pass, highpass, or band-pass filter is the state variable active filter. The
digital potentiometer allows full programmability of the frequency,
gain and Q of the filter outputs. Figure 10 shows the filter circuit
using a 2.5 V virtual ground, which allows a ± 2.5 VP input and
output swing. RDAC2 and 3 set the LP, HP, and BP cutoff and
center frequencies, respectively. These variable resistors should
be programmed with the same data (as with ganged potentiometers) to maintain the best circuit Q. Figure 11 shows the measured
filter response at the band-pass output as a function of the RDAC2
and RDAC3 settings which produce a range of center frequencies
from 2 kHz to 20 kHz. The filter gain response at the band-pass
output is shown in Figure 12. At a center frequency of 2 kHz, the
gain is adjusted over a –20 dB to +20 dB range determined by
RDAC1. Circuit Q is adjusted by RDAC4. For more detailed
reading on the state variable active filter, see Analog Devices’
application note, AN-318.
0.01F
2.00000 k
A
20
0.01F
VIN
B RDAC1 A1
B
RDAC2
A3
OP279 2
LOWPASS
B
RDAC3
AMPLITUDE – dB
A2
A4
BANDPASS
HIGHPASS
0
–20
–40
–60
Figure 10. Programmable State Variable Active Filter
–80
20
100
1k
10k
FREQUENCY – Hz
100k 200k
Figure 12. Programmed Amplitude Band-Pass Response
REV. C
–17–
AD8400/AD8402/AD8403
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.210
(5.33)
MAX
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
0.015 (0.381)
0.008 (0.204)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead SOIC
(R-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
0.1574 (4.00)
0.1497 (3.80) 1
4
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
SEATING (1.27)
0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0° 0.0500 (1.27)
0.0160 (0.41)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
14-Lead Plastic DIP Package
(N-14)
0.795 (20.19)
0.725 (18.42)
14
8
7
1
PIN 1
0.100 (2.54)
BSC
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
PLANE
0.014 (0.356) 0.045 (1.15)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–18–
REV. C
AD8400/AD8402/AD8403
14-Lead Narrow Body SOIC Package
(SO-14)
0.3444 (8.75)
0.3367 (8.55)
0.1574 (4.00)
0.1497 (3.80)
14
8
1
7
0.050 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
0.0196 (0.50)
45
0.0099 (0.25)
8
0.0192 (0.49) SEATING 0.0099 (0.25) 0 0.0500 (1.27)
PLANE
0.0138 (0.35)
0.0160 (0.41)
0.0075 (0.19)
0.0098 (0.25)
0.0040 (0.10)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
14-Lead TSSOP
(RU-14)
0.201 (5.10)
0.193 (4.90)
14
8
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
7
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
0.0256
(0.65)
BSC
SEATING
PLANE
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8
0
0.028 (0.70)
0.020 (0.50)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
24-Lead Narrow Body Plastic DIP Package
(N-24)
1.275 (32.30)
1.125 (28.60)
24
13
1
12
0.280 (7.11)
0.240 (6.10)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.150
(3.81)
MIN
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.070 (1.77) SEATING
0.045 (1.15) PLANE
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. C
–19–
AD8400/AD8402/AD8403
OUTLINE DIMENSIONS (continued)
Dimensions shown in inches and (mm).
C01092–0–2/02(C)
24-Lead SOIC Package
(SOL-24)
0.6141 (15.60)
0.5985 (15.20)
24
13
0.2992 (7.60)
0.2914 (7.40)
1
0.4193 (10.65)
0.3937 (10.00)
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0118 (0.30) 0.0500
0.0040 (0.10) (1.27)
BSC
0.0291 (0.74)
45
0.0098 (0.25)
8
0
0.0192 (0.49) SEATING
0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
24-Lead Thin Surface-Mount TSSOP Package
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8
0
0.028 (0.70)
0.020 (0.50)
Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Addition of new Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to TPCs 1, 8, 12, 16, 20, 24, 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to PROGRAMMING THE VARIABLE RESISTOR section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–20–
REV. C
PRINTED IN U.S.A.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS, INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN