12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter AD9233 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AD9233 VIN+ VIN– GENERAL DESCRIPTION 8-STAGE 1 1/2-BIT PIPELINE MDAC1 SHA 8 4 3 REFB CORRECTION LOGIC OR 13 OUTPUT BUFFERS DCO D11 (MSB) VREF D0 (LSB) SENSE 0.5V REF SELECT AGND CLOCK DUTY CYCLE STABILIZER CLK+ CLK– SCLK/DFS MODE SELECT PDWN SDIO/DCS CSB DRGND Figure 1. The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. The AD9233 is available in a 48-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and onchip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. PRODUCT HIGHLIGHTS The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9233 is suitable for applications in communications, imaging, and medical ultrasound. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. A/D A/D REFT APPLICATIONS Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes DRVDD 05492-001 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.15 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock duty cycle stabilizer Data output clock Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment 1. The AD9233 operates from a single 1.8 V power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 2. The patented SHA input maintains excellent performance for input frequencies up to 225 MHz. 3. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 4. A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS, power-down, and voltage reference mode. 5. The AD9233 is pin compatible with the AD9246, allowing a simple migration from 12 bits to 14 bits. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD9233 TABLE OF CONTENTS Features .............................................................................................. 1 Timing ......................................................................................... 22 Applications....................................................................................... 1 Serial Port Interface (SPI).............................................................. 23 General Description ......................................................................... 1 Configuration Using the SPI..................................................... 23 Functional Block Diagram .............................................................. 1 Hardware Interface..................................................................... 23 Product Highlights ........................................................................... 1 Configuration Without the SPI ................................................ 23 Revision History ............................................................................... 3 Memory Map .................................................................................. 24 Specifications..................................................................................... 4 Reading the Memory Map Table.............................................. 24 DC Specifications ......................................................................... 4 Layout Considerations................................................................... 27 AC Specifications.......................................................................... 5 Power and Ground Recommendations ................................... 27 Digital Specifications ................................................................... 6 CML ............................................................................................. 27 Switching Specifications .............................................................. 7 RBIAS........................................................................................... 27 Timing Diagram ........................................................................... 7 Reference Decoupling................................................................ 27 Absolute Maximum Ratings............................................................ 8 Evaluation Board ............................................................................ 28 Thermal Resistance ...................................................................... 8 Power Supplies............................................................................ 28 ESD Caution.................................................................................. 8 Input Signals................................................................................ 28 Pin Configuration and Function Descriptions............................. 9 Output Signals ............................................................................ 28 Equivalent Circuits ......................................................................... 10 Default Operation and Jumper Selection Settings................. 29 Typical Performance Characteristics ........................................... 11 Alternative Clock Configurations............................................ 29 Theory of Operation ...................................................................... 15 Alternative Analog Input Drive Configuration...................... 30 Analog Input Considerations.................................................... 15 Schematics ....................................................................................... 31 Voltage Reference ....................................................................... 17 Evaluation Board Layouts ......................................................... 36 Clock Input Considerations ...................................................... 18 Bill of Materials (BOM)............................................................. 39 Jitter Considerations .................................................................. 19 Outline Dimensions ....................................................................... 42 Power Dissipation and Standby Mode..................................... 20 Ordering Guide .......................................................................... 42 Digital Outputs ........................................................................... 21 Rev. A | Page 2 of 44 AD9233 REVISION HISTORY 8/06—Rev. 0 to Rev. A Updated Format.................................................................. Universal Added 80 MSPS .................................................................. Universal Deleted Figure 19, Figure 20, Figure 22, and Figure 23; Renumbered Sequentially ..............................................................11 Deleted Figure 24, Figure 25, and Figure 27 to Figure 29; Renumbered Sequentially ..............................................................12 Deleted Figure 31 and Figure 34; Renumbered Sequentially ....13 Deleted Figure 37, Figure 38, Figure 40, and Figure 41; Renumbered Sequentially ..............................................................14 Deleted Figure 46; Renumbered Sequentially .............................15 Deleted Figure 52; Renumbered Sequentially .............................16 Changes to Figure 40 ......................................................................16 Changes to Figure 46 ......................................................................18 Inserted Figure 54; Renumbered Sequentially ............................20 Changes to Digital Outputs Section .............................................21 Changes to Timing Section............................................................22 Added Data Clock Output (DCO) Section..................................22 Changes to Configuration Using the SPI Section and Configuration Without the SPI Section .......................................23 Changes to Table 15 ........................................................................25 Changes to Table 16 ........................................................................39 Changes to Ordering Guide...........................................................42 4/06—Revision 0: Initial Version Rev. A | Page 3 of 44 AD9233 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 2 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 (DRVDD = 1.8 V) IDRVDD1 (DRVDD = 3.3 V) POWER CONSUMPTION DC Input Sine Wave Input1 (DRVDD = 1.8 V) Sine Wave Input1 (DRVDD = 3.3 V) Standby 3 Power-Down Temp Full AD9233BCPZ-80 Min Typ Max 12 AD9233BCPZ-105 Min Typ Max 12 AD9233BCPZ-125 Min Typ Max 12 Guaranteed ±0.3 ±0.5 ±0.2 ±4.7 ±0.3 ±0.2 ±1.2 ±0.5 Guaranteed ±0.3 ±0.8 ±0.2 ±4.9 ±0.5 ±0.2 ±1.2 ±0.5 Guaranteed ±0.3 ±0.8 ±0.2 ±3.9 ±0.5 ±0.2 ±1.2 ±0.5 Full Full Full Full 25°C Full 25°C ±15 ±95 Full Full ±5 7 25°C 0.34 0.34 0.34 LSB rms Full Full Full 2 8 6 2 8 6 2 8 6 V p-p pF kΩ 1.7 1.7 ±20 1.8 3.3 1.9 3.6 Full Full Full 138 7 12 Full Full Full Full Full 248 261 288 40 1.8 ±5 7 ±35 1.8 3.3 1.9 3.6 155 178 8 14 279 320 335 365 40 1.8 1 1.7 1.7 ±15 ±95 % FSR % FSR LSB LSB LSB LSB Full Full Full Full ±15 ±95 Unit Bits ±5 7 1.7 1.7 ppm/°C ppm/°C ±35 mV mV 1.8 3.3 1.9 3.6 V V 194 220 10 17 236 mA mA mA 350 395 415 452 40 1.8 425 mW mW mW mW mW Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND). 2 Rev. A | Page 4 of 44 AD9233 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz TWO-TONE SFDR fIN = 30 MHz (−7 dBFS), 31 MHz (−7 dBFS) fIN = 170 MHz (−7 dBFS), 171 MHz (−7 dBFS) ANALOG INPUT BANDWIDTH 1 Temp 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C AD9233BCPZ-80 Min Typ Max AD9233BCPZ-105 Min Typ Max 69.5 69.5 AD9233BCPZ-125 Min Typ Max 69.5 69.5 68.9 69.5 69.5 68.3 dBc dBc dBc dBc dBc 68.3 69.4 68.9 69.4 68.9 69.4 68.9 69.2 69.2 69.2 69.2 69.2 69.2 Unit 69.1 68.6 69.1 68.6 69.1 68.6 dBc dBc dBc dBc dBc 25°C 25°C 25°C 25°C 11.4 11.4 11.4 11.3 11.4 11.4 11.4 11.3 11.4 11.4 11.4 11.3 Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C −90.0 −85.0 −90.0 −85.0 −90.0 −85.0 −85.0 −83.5 −85.0 −83.5 −85.0 −83.5 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 90.0 85.0 90.0 85.0 90.0 85.0 68.5 67.3 67.3 −76.0 76.0 −73.0 73.0 −73.0 dBc dBc dBc dBc dBc 73.0 85.0 83.5 85.0 83.5 85.0 83.5 25°C 25°C Full 25°C 25°C −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 −90.0 dBc dBc dBc dBc dBc 25°C 25°C 25°C 87 83 650 87 83 650 85 84 650 dBFS dBFS MHz −85.0 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. A | Page 5 of 44 −81.0 −81.0 AD9233 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, OE, PWDN) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (CSB) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (VOH, IOH = 50 μA) High Level Output Voltage (VOH, IOH = 0.5 mA) Low Level Output Voltage (VOL, IOL = 1.6 mA) Low Level Output Voltage (VOL, IOL = 50 μA) DRVDD = 1.8 V High Level Output Voltage (VOH, IOH = 50 μA) High Level Output Voltage (VOH, IOH = 0.5 mA) Low Level Output Voltage (VOL, IOL = 1.6 mA) Low Level Output Voltage (VOL, IOL = 50 μA) AD9233BCPZ-80/105/125 Typ Max Temp Min Full Full Full Full Full Full Full Full Full Full CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 8 10 12 4 Full Full Full Full Full Full 1.2 0 −50 −10 Full Full Full Full Full Full 1.2 0 −10 +40 Full Full Full Full Full Full 1.2 0 −10 +40 Full Full Full Full 3.29 3.25 Full Full Full Full 1.79 1.75 Rev. A | Page 6 of 44 Unit V V p-p V V V V μA μA kΩ pF 3.6 0.8 −75 +10 V V μA μA kΩ pF 3.6 0.8 +10 +135 V V μA μA kΩ pF DRVDD + 0.3 0.8 +10 +130 V V μA μA kΩ pF 30 2 26 2 26 5 0.2 0.05 V V V V 0.2 0.05 V V V V AD9233 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted. Table 4. Parameter 1 CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Conversion Rate, DCS Disabled CLK Period CLK Pulse Width High, DCS Enabled CLK Pulse Width High, DCS Disabled DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 3 OUT-OF-RANGE RECOVERY TIME SERIAL PORT INTERFACE 4 SCLK Period (tCLK) SCLK Pulse Width High Time (tHI) SCLK Pulse Width Low Time (tLO) SDIO to SCLK Setup Time (tDS) SDIO to SCLK Hold Time (tDH) CSB to SCLK Setup Time (tS) CSB to SCLK Hold Time (tH) Temp AD9233BCPZ-80 Min Typ Max AD9233BCPZ-105 Min Typ Max AD9233BCPZ-125 Min Typ Max Unit Full Full Full Full Full 20 10 12.5 3.75 5.63 MSPS MSPS ns ns ns Full Full Full Full Full Full Full Full Full 3.1 80 80 4.9 5.9 Full Full Full Full Full Full Full 6.25 6.25 8.75 6.88 20 10 9.5 2.85 4.28 3.9 4.4 5.7 6.8 12 0.8 0.1 350 2 4.8 3.1 3.4 4.4 40 16 16 5 2 5 2 105 105 4.75 4.75 6.65 5.23 20 10 8 2.4 3.6 3.9 4.4 4.3 5.3 12 0.8 0.1 350 2 4.8 3.1 125 125 2.6 3.7 40 16 16 5 2 5 2 40 16 16 5 2 5 2 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependant on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 57 and the Serial Port Interface (SPI) section. 2 TIMING DIAGRAM N+2 N+3 N N+4 tA N+8 N+5 N+6 N+7 N–7 N–6 tCLK CLK+ CLK– tPD N – 13 tS N – 12 N – 11 tH N – 10 N–9 N–8 tDCO DCO Figure 2. Timing Diagram Rev. A | Page 7 of 44 tCLK N–5 N–4 05492-083 DATA 5.6 4.4 3.9 4.4 3.5 4.5 12 0.8 0.1 350 3 4.8 ns ns ns ns cycles ns ps rms ms cycles ns ns ns ns ns ns ns 1 N+1 4 4 AD9233 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0 through D11 to DRGND DCO to DRGND OR to DRGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND VREF to AGND SENSE to AGND REFT to AGND REFB to AGND SDIO/DCS to DRGND PDWN to AGND CSB to AGND SCLK/DFS to AGND OEB to AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 Sec) Junction Temperature Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +0.3 V −3.9 V to +2.0 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to AVDD + 1.3 V −0.3 V to AVDD + 1.3 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Package Type 48-lead LFCSP (CP-48-3) θJA 26.4 θJC 2.4 Unit °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes, reduces the θJA. –65°C to +125°C –40°C to +85°C 300°C 150°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 44 AD9233 48 47 46 45 44 43 42 41 40 39 38 37 DRVDD DRGND NC NC DCO OEB AVDD AGND AVDD CLK– CLK+ AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS (LSB) D0 D1 1 2 AD9233 TOP VIEW (Not to Scale) PIN 0 (EXPOSED PADDLE): AGND 36 35 34 33 32 31 30 29 28 27 26 25 PDWN RBIAS CML AVDD AGND VIN– VIN+ AGND REFT REFB VREF SENSE 05492-003 D10 (MSB) D11 OR DRGND DRVDD SDIO/DCS SCLK/DFS CSB AGND AVDD AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 D2 3 D3 4 D4 5 D5 6 DRGND 7 DRVDD 8 D6 9 D7 10 D8 11 D9 12 PIN 1 INDICATOR NC = NO CONNECT Figure 3. Pin Configuration Table 7. Pin Function Description Pin No. 0, 21, 23, 29, 32, 37, 41 1 to 6, 9 to 14 7, 16, 47 8, 17, 48 15 18 Mnemonic AGND Description Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.) D0 (LSB) to D11 (MSB) DRGND DRVDD OR SDIO/DCS 19 20 22, 24, 33, 40, 42 25 26 27 28 30 31 34 35 SCLK/DFS CSB AVDD SENSE VREF REFB REFT VIN+ VIN– CML RBIAS 36 38 39 43 44 45, 46 PDWN CLK+ CLK– OEB DCO NC Data Output Bits. Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Out-of-Range Indicator. Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). See Table 10. SPI Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). See Table 10. SPI Chip Select (Active Low). Analog Power Supply. Reference Mode Selection. See Table 9. Voltage Reference Input/Output. Differential Reference (−). Differential Reference (+). Analog Input Pin (+). Analog Input Pin (−). Common-Mode Level Bias Output. External Bias Resister Connection. A 10 kΩ resister must be connected between this pin and analog ground (AGND). Power-Down Function Select. Clock Input (+). Clock Input (−). Output Enable (Active Low). Data Clock Output. No Connection. Rev. A | Page 9 of 44 AD9233 EQUIVALENT CIRCUITS 1kΩ SCLK/DFS OEB PDWN 30kΩ 05492-004 05492-008 VIN Figure 4. Equivalent Analog Input Circuit Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit AVDD AVDD 26kΩ 1.2V 1kΩ CLK– 05492-005 CLK+ CSB 10kΩ 05492-010 10kΩ Figure 9. Equivalent CSB Input Circuit Figure 5. Equivalent Clock Input Circuit DRVDD SENSE 1kΩ 1kΩ 05492-006 05492-011 SDIO/DCS Figure 10. Equivalent SENSE Circuit Figure 6. Equivalent SDIO/DCS Input Circuit DRVDD AVDD 05492-007 DRGND 6kΩ 05492-012 VREF Figure 11. Equivalent VREF Circuit Figure 7. Equivalent Digital Output Circuit Rev. A | Page 10 of 44 AD9233 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS; 64k sample; TA = 25°C, unless otherwise noted. All figures show typical performance for all speed grades. 0 0 125MSPS 2.3MHz @ –1dBFS SNR = 69.5dBc (70.5dBFS) ENOB = 11.2 BITS SFDR = 90.0dBc –60 –80 –80 –100 –120 –120 0 15.625 31.250 FREQUENCY (MHz) 46.875 –140 62.500 15.625 31.250 FREQUENCY (MHz) 0 125MSPS 30.3MHz @ –1dBFS SNR = 69.5dBc (70.5dBFS) ENOB = 11.2 BITS SFDR = 88.8dBc –80 –40 –60 –80 –100 –120 –120 05492-014 –100 31.250 FREQUENCY (MHz) 46.875 –140 62.500 0 125MSPS 70.3MHz @ –1dBFS SNR = 69.5dBc (70.5dBFS) ENOB = 11.2 BITS SFDR = 85.0dBc –20 AMPLITUDE (dBFS) –60 –80 05492-015 –120 46.875 62.500 –80 –120 31.250 FREQUENCY (MHz) 46.875 –60 –100 15.625 31.250 FREQUENCY (MHz) –40 –100 –140 15.625 125MSPS 170.3MHz @ –1dBFS SNR = 68.9dBc (69.9dBFS) ENOB = 11.1 BITS SFDR = 83.5dBc –20 –40 0 0 Figure 16. AD9233-125 Single-Tone FFT with FIN = 140.3 MHz Figure 13. AD9233-125 Single-Tone FFT with FIN = 30.3 MHz 0 05492-017 AMPLITUDE (dBFS) –60 15.625 62.500 125MSPS 140.3MHz @ –1dBFS SNR = 69.0dBc (70.0dBFS) ENOB = 11.1 BITS SFDR = 85.0dBc –20 –40 0 46.875 62.500 Figure 14. AD9233-125 Single-Tone FFT with FIN = 70.3 MHz –140 05492-018 –20 –140 0 Figure 15. AD9233-125 Single-Tone FFT with FIN = 100.3 MHz 0 AMPLITUDE (dBFS) –60 –100 Figure 12. AD9233-125 Single-Tone FFT with FIN = 2.3 MHz AMPLITUDE (dBFS) –40 05492-016 AMPLITUDE (dBFS) –40 –140 125MSPS 100.3MHz @ –1dBFS SNR = 69.4dBc (70.4dBFS) ENOB = 11.2 BITS SFDR = 85.0dBc –20 05492-013 AMPLITUDE (dBFS) –20 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 Figure 17. AD9233-125 Single-Tone FFT with FIN = 170.3 MHz Rev. A | Page 11 of 44 AD9233 0 –20 95 SFDR = –40°C 90 –40 SNR/SFDR (dBc) –60 –80 –100 75 SNR = +25°C SNR = –40°C 15.625 31.250 FREQUENCY (MHz) 46.875 SNR = +85°C 60 62.500 0 05492-021 05492-019 0 50 100 200 250 Figure 21. AD9233 Single-Tone SNR/SFDR vs. Input Frequency (FIN) and Temperature with 2 V p-p Full Scale 100 125MSPS 300.3MHz @ –1dBFS SNR = 67.8dBc (68.8dBFS) ENOB = 10.8 BITS SFDR = 77.4dBc –20 95 SNR/SFDR (dBc) –60 –80 75 65 05492-029 –120 31.250 46.875 SFDR = –40°C 80 70 15.625 SFDR = +25°C 85 –100 0 SFDR = +85°C 90 –40 SNR = +25°C SNR = –40°C SNR = +85°C 60 62.500 0 50 100 150 200 250 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. AD9233 Single-Tone SNR/SFDR vs. Input Frequency (FIN) and Temperature with 1 V p-p Full Scale Figure 19. AD9233-125 Single-Tone FFT with FIN = 300.3 MHz 1.0 120 SFDR (dBFS) 0.8 80 GAIN/OFFSET ERROR (%FSR) 100 SNR (dBFS) 60 40 SFDR (dBc) 85dB REFERENCE LINE 20 OFFSET ERROR 0.5 0.3 0 GAIN ERROR –0.3 –0.5 05492-031 –0.8 SNR (dBc) 0 –90 –80 –70 –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 0 05492-091 SNR/SFDR (dBc and dBFS) 150 INPUT FREQUENCY (MHz) 0 –140 SFDR = +85°C 65 Figure 18. AD9233-125 Single-Tone FFT with FIN = 225.3 MHz AMPLITUDE (dBFS) 80 70 –120 –140 SFDR = +25°C 85 05492-022 AMPLITUDE (dBFS) 100 125MSPS 225.3MHz @ –1dBFS SNR = 68.5dBc (69.5dBFS) ENOB = 11.0 BITS SFDR = 80.4dBc –1.0 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 23. AD9233 Gain and Offset vs. Temperature Figure 20. AD9233 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with FIN = 2.4 MHz Rev. A | Page 12 of 44 80 AD9233 0 0 125MSPS 29.1MHz @ –7dBFS 32.1MHz @ –7dBFS SFDR = 85dBc (92dBFS) –20 SFDR/IMD3 (dBc and dBFS) –40 –60 –80 –100 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) 05492-024 –140 0 15.625 31.250 46.875 IMD3 (dBFS) –120 –90 62.500 –78 –66 FREQUENCY (MHz) –30 –18 –6 0 125MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS SFDR = 84dBc (91dBFS) –20 SFDR/IMD3 (dBc and dBFS) –20 AMPLITUDE (dBFS) –42 Figure 27. AD9233 Two-Tone SFDR/IMD vs. Input Amplitude (AIN) with FIN1 = 29.1 MHz, FIN2 = 32.1 MHz 0 –40 –60 –80 –100 SFDR (dBc) –40 IMD3 (dBFS) –60 –80 SFDR (dBFS) –100 05492-025 –120 0 15.625 31.250 46.875 –120 –90 62.500 FREQUENCY (MHz) –66 –54 –42 –30 –18 –6 Figure 28. AD9233 Two-Tone SFDR/IMD vs. Input Amplitude (AIN) with FIN1 = 169.1 MHz, FIN2 = 172.1 MHz 0 –20 –20 AMPLITUDE (dBFS) 0 –40 –60 –80 NPR = 61.9dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz –40 –60 –80 05492-086 0 15.36 30.72 46.08 61.44 –120 05492-090 –100 –100 –120 IMD3 (dBFS) –78 INPUT AMPLITUDE (dBFS) Figure 25. AD9233-125 Two-Tone FFT with FIN1 = 169.1 MHz, FIN2 = 172.1 MHz AMPLITUDE (dBFS) –54 ANALOG INPUT LEVEL (dBFS) Figure 24. AD9233-125 Two-Tone FFT with FIN1 = 29.1 MHz, FIN2 = 32.1 MHz –140 05492-035 –100 –120 05492-080 AMPLITUDE (dBFS) –20 0 15.625 31.250 46.875 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. AD9233-125 Noise Power Ratio Figure 26. AD9233-125 Two 64k WCDMA Carriers with FIN = 215.04 MHz, FS = 122.88 MSPS Rev. A | Page 13 of 44 62.500 AD9233 10 100 0.34 LSB rms SFDR 8 NUMBER OF HITS (1M) SNR/SFDR (dBc) 90 85 80 75 SNR 05492-027 5 4 2 70 65 6 25 45 65 85 105 05492-085 95 0 125 N–1 N Figure 33. AD9233 Grounded Input Histogram Figure 30. AD9233 Single-Tone SNR/SFDR vs. Clock Frequency (FS) with FIN = 2.4 MHz 0.35 100 SFDR DCS = ON 0.25 90 INL ERROR (LSB) SNR DCS = ON 70 60 0.05 –0.05 –0.15 50 05492-026 –0.25 SNR DCS = OFF 20 40 60 –0.35 80 05492-023 SNR/SFDR (dBc) 0.15 SFDR DCS = OFF 80 40 0 1024 DUTY CYCLE (%) Figure 31. AD9233 SNR/SFDR vs. Duty Cycle with FIN = 10.3 MHz 2048 OUTPUT CODE 3072 4096 Figure 34. AD9233 INL with FIN = 10.3 MHz 90 0.15 SFDR 0.10 DNL ERROR (LSB) 85 80 75 0.05 0 –0.05 70 65 0.5 0.7 0.9 1.1 1.3 INPUT COMMON-MODE VOLTAGE (V) Figure 32. AD9233 SNR/SFDR vs. Input Common Mode (VCM) with FIN = 30 MHz –0.10 –0.15 05492-020 SNR 05492-028 SNR/SFDR (dBc) N+1 OUTPUT CODE CLOCK FREQUENCY (MSPS) 0 1024 2048 OUTPUT CODE 3072 Figure 35. AD9233 DNL with FIN = 10.3 MHz Rev. A | Page 14 of 44 4096 AD9233 THEORY OF OPERATION S The AD9233 architecture consists of a front-end SHA followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers proceed into a high impedance state. ANALOG INPUT CONSIDERATIONS The analog input to the AD9233 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. CS VIN+ CPIN, PAR S H CS VIN– CPIN, PAR CH S 05492-037 Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. CH S Figure 36. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN− should match such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates two reference voltages used to define the input span of the ADC core. The span of the ADC core is set by the buffer to be 2 × VREF. The reference voltages are not available to the user. Two bypass points, REFT and REFB, are brought out for decoupling to reduce the noise contributed by the internal reference buffer. It is recommended that REFT be decoupled to REFB by a 0.1 μF capacitor, as described in the Layout Considerations section. Input Common Mode The clock signal alternately switches the SHA between sample mode and hold mode (see Figure 36). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a lowpass filter at the ADC input; therefore, the precise values are dependant upon the application. In IF undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, these capacitors limit the input bandwidth. See Application Notes AN-742, Frequency Domain Response of SwitchedCapacitor ADCs, and AN-827, A Resonant Approach To Interfacing Amplifiers to Switched-Capacitor ADCs, and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters”, for more information. The analog inputs of the AD9233 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that VCM = 0.55 × AVDD is recommended for optimum performance; however, the device functions over a wider range with reasonable performance (see Figure 32). An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 × AVDD). The CML pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Layout Considerations section. Differential Input Configurations Optimum performance is achieved by driving the AD9233 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9233 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Rev. A | Page 15 of 44 AD9233 49.9Ω R VIN+ AVDD 499Ω AD9233 C 523Ω R CML VIN– 05492-038 AD8138 0.1µF At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9233. For applications where SNR is a key parameter, transformer coupling is the recommended input. For applications where SFDR is a key parameter, differential double balun coupling is the recommended input configuration. An example is shown in Figure 39. 499Ω 499Ω Figure 37. Differential Input Configuration Using the AD8138 As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver can be used. An example is shown in Figure 40. For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 38. The CML voltage can be connected to the center tap of the secondary winding of the transformer to bias the analog input. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 8 displays recommended values to set the RC network. However, these values are dependant on the input signal and should only be used as a starting guide. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can cause core saturation, which leads to distortion. R 49.9Ω Frequency Range (MHz) 0 to 70 70 to 200 200 to 300 >300 VIN+ AD9233 C R CML VIN– R Series (Ω) 33 33 15 15 05492-039 0.1µF Figure 38. Differential Transformer-Coupled Configuration 0.1µF 0.1µF R VIN+ 2V p-p 25Ω PA S P S 25Ω 0.1µF AD9233 C 0.1µF R VIN– CML 05492-089 2V p-p Table 8. RC Network Recommended Values Figure 39. Differential Double Balun Input Configuration VCC 0.1µF 0.1µF 0Ω ANALOG INPUT 16 1 8, 13 11 0.1µF R 2 VIN+ 200Ω RD CD AD8352 RG 3 10 0.1µF 200Ω C R 4 5 ANALOG INPUT 0.1µF 0Ω AD9233 VIN– CML 14 0.1µF 0.1µF Figure 40. Differential Input Configuration Using the AD8352 Rev. A | Page 16 of 44 05492-088 1V p-p C Differential (pF) 15 5 5 Open AD9233 Single-Ended Input Configuration Although not recommended, it is possible to operate the AD9233 in a single-ended input configuration, as long as the input voltage swing is within the AVDD supply. Single-ended operation can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 41 details a typical single-ended input configuration. AVDD 10µF This puts the reference amplifier in a noninverting mode with the VREF output defined as R2 ⎞ VREF = 0.5 × ⎛⎜1 + ⎟ ⎝ R1 ⎠ If the SENSE pin is connected to the AVDD pin, the reference amplifier is disabled, and an external reference voltage can be applied to the VREF pin (see the External Reference Operation section). The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. AVDD 1kΩ 10µF 0.1µF C R ADC AD9233 VIN– 1kΩ ADC CORE VIN– – 1kΩ REFT 0.1µF REFB VREF Figure 41. Single-Ended Input Configuration 0.1µF 0.1µF VOLTAGE REFERENCE SELECT LOGIC SENSE A stable and accurate voltage reference is built into the AD9233. The input range is adjustable by varying the reference voltage applied to the AD9233, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the following sections. The Reference Decoupling section describes the best practices and requirements for PCB layout of the reference. 05492-043 0.5V AD9233 VIN– ADC CORE – VIN+ – Figure 42. Internal Reference Configuration REFT Internal Reference Connection A comparator within the AD9233 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 42), setting VREF to 1 V. 0.1µF REFB VREF 0.1µF 0.1µF R2 SENSE Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected external to the chip, as shown in Figure 43, the switch again sets to the SENSE pin. R1 SELECT LOGIC 0.5V AD9233 05492-044 1V p-p 49.9Ω VIN+ VIN+ 05492-042 R 0.1µF – 1kΩ Figure 43. Programmable Reference Configuration If the internal reference of the AD9233 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 depicts how the internal reference voltage is affected by loading. Rev. A | Page 17 of 44 AD9233 Table 9. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 0.5 × (1 + R2/R1) (See Figure 43) 1.0 0 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9233 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ pin and the CLK− pin via a transformer or capacitors. These pins are biased internally (see Figure 5) and require no external bias. –0.25 VREF = 1V –0.50 Clock Input Options –0.75 –1.00 05492-032 REFERENCE VOLTAGE ERROR (%) VREF = 0.5V –1.25 Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF 2.0 0 0.5 1.0 2.0 1.5 The AD9233 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal used, the jitter of the clock source is of the most concern, as described in the Jitter Considerations section. LOAD CURRENT (mA) Figure 44. VREF Accuracy vs. Load External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 45 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. VREF = 0.5V 8 MIN-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 0.1µF VREF = 1V 6 CLOCK INPUT 50Ω ADC AD9233 0.1µF CLK– 2 SCHOTTKY DIODES: HSMS2812 05492-048 0.1µF Figure 46. Transformer Coupled Differential Clock –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 45. Typical VREF Drift When the SENSE pin is tied to the AVDD pin, the internal reference is disabled, allowing the use of an external reference. An internal resistor divider loads the external reference with an equivalent 6 kΩ load (see Figure 11). In addition, an internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V. If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to the sample clock input pins, as shown in Figure 47. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. 0.1µF CLOCK INPUT CLOCK INPUT 0.1µF CLK+ CLK 0.1µF AD951x PECL DRIVER 100Ω 0.1µF CLK 50Ω* 50Ω* 240Ω 240Ω *50Ω RESISTORS ARE OPTIONAL Figure 47. Differential PECL Sample Clock Rev. A | Page 18 of 44 ADC AD9233 CLK– 05492-049 0 –40 CLK+ 100Ω 4 05492-033 REFERENCE VOLTAGE ERROR (mV) 10 Figure 46 shows one preferred method for clocking the AD9233. A low jitter clock source is converted from singleended to a differential signal using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9233 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9233 while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance. AD9233 A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 48. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. 0.1µF CLOCK INPUT CLK+ AD951x LVDS DRIVER 100Ω 0.1µF CLK 50Ω* ADC AD9233 CLK– 05492-050 CLOCK INPUT 0.1µF CLK 0.1µF and distortion performance are nearly flat for a wide range of duty cycles when the DCS is on, as shown in Figure 31. 50Ω* *50Ω RESISTORS ARE OPTIONAL Figure 48. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, directly drive CLK+ from a CMOS gate, while bypassing the CLK− pin to ground with a 0.1 μF capacitor. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.6 V, making the selection of the drive logic voltage very flexible. When driving CLK+ with a 1.8 V CMOS signal, it is required to bias the CLK− pin with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 49). The 39 kΩ resistor is not required when driving CLK+ with a 3.3 V CMOS signal (see Figure 50). VCC 0.1µF CLOCK INPUT 50Ω* 1kΩ OPTIONAL 0.1µF 100Ω AD951x CMOS DRIVER VCC 50Ω* 1kΩ 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω 0.1µF SCLK/DFS Binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) SNR = −20 log (2π × FIN × tJ) In the equation, the rms aperture jitter (tJ) represents the rootmean-square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 51. Figure 49. Single-Ended 1.8 V CMOS Sample Clock CLOCK INPUT Voltage at Pin AGND AVDD 05492-051 39kΩ *50Ω RESISTOR IS OPTIONAL 0.1µF Table 10. Mode Selection (External Pin Mode) High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (FIN) due to jitter (tJ) is calculated as CLK– 0.1µF The DCS can be enabled or disabled by setting the SDIO/DCS pin when operating in the external pin mode (see Table 10), or via the SPI, as described in the Table 15. JITTER CONSIDERATIONS CLK+ ADC AD9233 1kΩ Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, which requires a wait time of 1.5 μs to 5 μs after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the time the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependant on the duty cycle of the input clock signal. In such an application, it can be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. CLK+ ADC AD9233 70 0.05ps 05492-052 CLK– *50Ω RESISTOR IS OPTIONAL MEASURED PERFORMANCE 65 Figure 50. Single-Ended 3.3 V CMOS Sample Clock 0.20ps Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9233 contains a DCS that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9233. Noise Rev. A | Page 19 of 44 0.5ps 55 1.0ps 50 1.50ps 2.00ps 45 40 2.50ps 3.00ps 1 10 100 INPUT FREQUENCY (MHz) Figure 51. SNR vs. Input Frequency and Jitter 05492-046 Clock Duty Cycle SNR (dBc) 60 1000 AD9233 150 400 TOTAL POWER 100 375 50 350 0 25 50 75 100 0 125 05492-034 IDRVDD 325 CLOCK FREQUENCY (MSPS) Figure 52. AD9233-125 Power and Current vs. Clock Frequency, FIN = 30 MHz 410 200 180 IAVDD 160 370 POWER (mW) 140 ×N 350 120 330 100 TOTAL POWER 80 310 60 290 40 250 30 55 80 0 105 CLOCK FREQUENCY (MSPS) 290 150 IAVDD 275 120 260 90 TOTAL POWER 245 60 230 CURRENT (mA) The data used for Figure 52 and Figure 53 is based on the same operating conditions as used in the plots in the Typical Performance Characteristics section with a 5 pF load on each output driver. 5 Figure 53. AD9233-105 Power and Current vs. Clock Frequency, FIN = 30 MHz POWER (mW) This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. 20 IDRVDD 05492-082 270 where N is the number of output bits (12 in the case of the AD9233). 30 IDRVDD 215 0 20 40 CLOCK FREQUENCY (MSPS) 60 0 80 05492-093 2 200 425 390 As shown in Figure 52 and Figure 53, the power dissipated by the AD9233 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as I DRVDD = V DRVDD × C LOAD × IAVDD CURRENT (mA) 450 POWER DISSIPATION AND STANDBY MODE f CLK 250 CURRENT (mA) Refer to Application Notes AN-501, Aperture Uncertainty and ADC System Performance, and AN-756, Sampled Systems and the Effects of Clock Phase Noise and Jitter for more in-depth information about jitter performance as it relates to ADCs. 475 POWER (mW) Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9233. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. The power supplies should also not be shared with analog input circuits such as buffers to avoid the clock modulating onto the input signal or vice versa. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Figure 54. AD9233-80 Power and Current vs. Clock Frequency, FIN = 30 MHz Rev. A | Page 20 of 44 AD9233 Power-Down Mode Out-of-Range (OR) Condition By asserting the PDWN pin high, the AD9233 is placed in power-down mode. In this state, the ADC typically dissipates 1.8 mW. During power-down, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9233 to its normal operational mode. This pin is both 1.8 V and 3.3 V tolerant. An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OR has the same pipeline latency as the digital data. Standby Mode When using the SPI port interface, the user can place the ADC in power-down or standby modes. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details. +FS – 1 LSB OR –FS + 1/2 LSB 0000 0000 0001 0000 0000 0000 0000 0000 0000 –FS –FS – 1/2 LSB +FS +FS – 1/2 LSB 05492-041 0 0 1 Figure 55. OR Relation to Input Voltage and Output Data OR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in Figure 55. OR remains high until the analog input returns to within the input range and another conversion is completed. By logically AND’ing the OR bit with the MSB and its complement, overrange high or underrange low conditions can be detected. Table 11 is a truth table for the overrange/underrange circuit in Figure 56, which uses NAND gates. MSB DIGITAL OUTPUTS OVER = 1 OR The AD9233 output drivers can be configured to interface with 1.8 V to 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts can require external buffers or latches. Table 11. Overrange/Underrange Truth Table The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 10). As detailed in the Interfacing to High Speed ADCs via SPI User Manual, the data format can be selected for either offset binary, twos complement, or Gray code when using the SPI control. Digital Output Enable Function (OEB) UNDER = 1 MSB 05492-045 Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in power-down mode; shorter power-down cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF decoupling capacitor on REFT and REFB, it takes approximately 0.25 ms to fully discharge the reference buffer decoupling capacitor and 0.35 ms to restore full operation. OR DATA OUTPUTS 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 Figure 56. Overrange/Underrange Logic OR 0 0 1 1 MSB 0 1 0 1 Analog Input Is: Within Range Within Range Underrange Overrange The AD9233 has three-state ability. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. This is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage. Table 12. Output Data Format Condition (V) VIN+ − VIN− < –VREF – 0.5 LSB VIN+ − VIN− = –VREF VIN+ − VIN− = 0 VIN+ − VIN− = +VREF – 1.0 LSB VIN+ − VIN− > +VREF – 0.5 LSB Binary Output Mode 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111 Twos Complement Mode 1000 0000 0000 1000 0000 0000 0000 0000 0000 0111 1111 1111 0111 1111 1111 Rev. A | Page 21 of 44 Gray Code Mode (SPI Accessible) 1100 0000 0000 1100 0000 0000 0000 0000 0000 1000 0000 0000 1000 0000 0000 OR 1 0 0 0 1 AD9233 TIMING Data Clock Output (DCO) The lowest typical conversion rate of the AD9233 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. The AD9233 provides a data clock output (DCO) intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 for a graphical timing description. The AD9233 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9233. These transients can degrade the dynamic performance of the converter. Rev. A | Page 22 of 44 AD9233 SERIAL PORT INTERFACE (SPI) The AD9233 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that are further divided into fields, as documented in the Memory Map section. For detailed operational information, see the Interfacing to High Speed ADCs via SPI User Manual. CONFIGURATION USING THE SPI As summarized in Table 13, three pins define the SPI of this ADC. The SCLK/DFS pin synchronizes the read and write data presented to the ADC. The SDIO/DCS dual-purpose pin allows data to be sent and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Table 13. Serial Port Interface Pins Mnemonic SCLK/DFS SDIO/DCS CSB Description SCLK (Serial Clock) is the serial shift clock in. SCLK synchronizes serial interface reads and writes. SDIO (Serial Data Input/Output) is a dual-purpose pin. The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. CSB (Chip Select Bar) is an active low control that gates the read and write cycles. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing. Figure 57 and Table 14 provide an example of the serial timing and its definitions. Other modes involving the CSB are available. The CSB can be held low indefinitely, permanently enabling the device (this is called streaming). The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high during power up, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. If CSB is high at power up and then brought low to activate the SPI, the SPI pin secondary functions are no longer available, unless the device power is cycled. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase and the length is determined by the W0 bit and the W1 bit. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip as well as read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first or in LSB first mode. MSB first is the default on power up and can be changed via the configuration register. For more information, see the Interfacing to High Speed ADCs via SPI User Manual. Table 14. SPI Timing Diagram Specifications Name tDS tDH tCLK tS tH tHI tLO Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state HARDWARE INTERFACE The pins described in Table 13 comprise the physical interface between the user’s programming device and the serial port of the AD9233. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either PROM or PIC microcontrollers. This provides the user with the ability to use an alternate method to program the ADC. One method is described in detail in the Application Note AN-812. When the SPI interface is not used, some pins serve a dual function. When strapped to AVDD or ground during device power on, the pins are associated with a specific function. CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS and SCLK/DFS pins serve as standalone CMOScompatible control pins. When the device is powered up with the CSB chip select connected to AVDD, the serial port interface is disabled. In this mode, it is assumed that the user intends to use the pins as static control lines for the output data format and duty cycle stabilizer (see Table 10). For more information, see the Interfacing to High Speed ADCs via SPI User Manual. Rev. A | Page 23 of 44 AD9233 MEMORY MAP READING THE MEMORY MAP TABLE Logic Levels Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration registers map (Address 0x00 to Address 0x02), device index and transfer registers map (Address 0xFF), and ADC functions map (Address 0x08 to Address 0x18). An explanation of two registers follows: The memory map register in Table 15 displays the register address number in hexadecimal in the first column. The last column displays the default value for each hexadecimal address. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x14, output_phase has a hexadecimal default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in binary. This setting is the default output clock or DCO phase adjust option. The default value adjusts the DCO phase 90° relative to the nominal DCO edge and 180° relative to the data edge. For more information on this function, consult the Interfacing to High Speed ADCs via SPI User Manual. • Bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit. • Clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit. SPI-Accessible Features A list of features accessible via the SPI and a brief description of what the user can do with these features follows. These features are described in detail in the Interfacing to High Speed ADCs via SPI User Manual. • Modes: Set either power-down or standby mode. • Clock: Access the DCS via the SPI. • Offset: Digitally adjust the converter offset. Open Locations • Test I/O: Set test modes to have known data on output bits. Locations marked as open are currently not supported for this device. When required, these locations should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x14). If the entire address location is open (Address 0x13), then the address location does not need to be written. • Output Mode: Setup outputs, vary the strength of the output drivers. • Output Phase: Set the output clock polarity. • VREF: Set the reference voltage. Default Values Coming out of reset, critical registers are loaded with default values. The default values for the registers are provided in Table 15. tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 05492-053 SDIO DON’T CARE DON’T CARE Figure 57. Serial Port Interface Timing Diagram Rev. A | Page 24 of 44 AD9233 Table 15. Memory Map Register Addr Parameter Bit 7 (Hex) Name (MSB) Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB First 0 = Off (Default) 1 = On Soft Reset 0 = Off (Default) 1 = On 1 1 Soft Reset 0 = Off (Default) 1 = On LSB First 0 = Off (Default) 1 = On Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0 0x18 The nibbles should be mirrored. See Interfacing to High Speed ADCs via SPI User Manual. Default is unique chip ID, different for each device. Child ID used to differentiate speed grades. 8-Bit Chip ID Bits 7:0 (AD9233 = 0x00), (Default) ReadOnly Open Open Open Child ID 0= 125 MSPS, 1= 105 MSPS Open Open Open ReadOnly Device Index and Transfer Registers FF device_update Open Open Open Open Open Open Open SW Transfer 0x00 Synchronously transfers data from the master shift register to the slave. Global ADC Functions 08 modes Open Open PDWN 0—Full 1— Standby Open Open Internal Power-Down Mode 000—Normal (Power-Up) 001—Full Power-Down 010—Standby 011—Normal (Power-Up) Note: External PDWN pin overrides this setting. 0x00 09 Open Open Open Open Open Open 0x01 Determines various generic modes of chip operation. See Power Dissipation and Standby Mode and SPI-Accessible Features sections. See Clock Duty Cycle and SPI-Accessible Features sections. clock Flexible ADC Functions 10 offset Open Digital Offset Adjust <5:0> 011111 011110 011101 … 000010 000001 000000 111111 111110 111101 ... 100001 100000 Rev. A | Page 25 of 44 Open Offset in LSBs +7 3/4 +7 1/2 +7 1/4 +1/2 +1/4 0 −1/4 −1/2 −3/4 −7 3/4 −8 Duty Cycle Stabilizer 0— Disabled 1—Enabled 0x00 Adjustable for offset inherent in the converter. See SPIAccessible Features section. AD9233 Addr (Hex) 0D Parameter Name test_io Bit 7 (MSB) 14 output_mode 16 output_phase 18 VREF 1 Bit 6 Bit 0 (LSB) Bit 2 Bit 1 Global Output Test Options 000—Off 001—Midscale Short 010— +FS Short 011— −FS Short 100—Checker Board Output 101—PN 23 Sequence 110—PN 9 111—One/Zero Word Toggle Data Format Select Output 00—Offset Binary Data (Default) Invert 01—Twos 1= Complement Invert 10—Gray Code Default Value (Hex) 0x00 Default Notes/ Comments See the Interfacing to High Speed ADCs via SPI User Manual. 0x00 Configures the outputs and the format of the data and the output driver strength. See SPIAccessible Features section. See SPIAccessible Features section. Bit 5 PN23 0= Normal 1= Reset Bit 4 PN9 0= Normal 1= Reset Bit 3 Output Driver Configuration 00 for DRVDD = 3.3 V 10 for DRVDD = 1.8 V Open Output Disable 1— Disabled 0— Enabled 1 Open Open DCO Polarity 1 = Inverted 0 = Normal Internal Reference Resistor Divider 00—VREF = 1.25 V 01—VREF = 1.5 V 10—VREF = 1.75 V 11—VREF = 2.00 V Open Open Open Open Open Open 0x00 Open Open Open Open Open Open 0xC0 External Output Enable (OEB) pin must be high. Rev. A | Page 26 of 44 AD9233 LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS A single PC board ground plane should be sufficient when using the AD9233. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the board, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9233. An exposed, continuous copper plane on the PCB should mate to the AD9233 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the ADC and PCB. See Figure 58 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). SILKSCREEN PARTITION PIN 1 INDICATOR 05492-054 When connecting power to the AD9233, it is recommended that two separate supplies be used: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal). If only a single 1.8 V supply is available, then it should be routed to AVDD first, then tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors preceding its connection to DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. Figure 58. Typical PCB Layout CML The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. RBIAS The AD9233 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resister sets the master current reference of the ADC core and should have at least a 1% tolerance. REFERENCE DECOUPLING The VREF pin should be externally decoupled to ground with a low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low ESR capacitor. In all reference configurations, REFT and REFB are bypass points provided for reducing the noise contributed by the internal reference buffer. It is recommended to place an external 0.1 μF ceramic capacitor across REFT/REFB. While it is not required to place this 0.1 μF capacitor, the SNR performance will degrade by approximately 0.1 dB without it. All reference decoupling capacitors should be placed as close to the ADC as possible with minimal trace lengths. Rev. A | Page 27 of 44 AD9233 EVALUATION BOARD The AD9233 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry. Each input configuration can be selected by proper connection of various components. Figure 59 shows the typical bench characterization setup used to evaluate the ac performance of the AD9233. Although at least one 1.8 V supply is needed with a 1 A current capability for AVDD_DUT and DRVDD_DUT, it is recommended that separate supplies be used for analog and digital. To operate the evaluation board using the AD8352 option, a separate 5.0 V analog supply is needed. The 5.0 V supply, or AMP_VDD, should have a 1 A current capability. To operate the evaluation board using the alternate SPI options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply (AVDD_3.3V) should have a 1 A current capability as well. Solder Jumpers J501, J502, and J505 allow the user to combine these supplies. See Figure 64 for more details. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or Agilent HP8644 signal generators or the equivalent. Use one meter long, shielded, RG-58, 50 Ω coaxial cables for making connections to the evaluation board. Enter the desired frequency and amplitude for the ADC. Typically, most ADI evaluation boards can accept a ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Analog Devices uses TTE®, Allen Avionics, and K&L® types of band-pass filters. Connect the filter directly to the evaluation board, if possible. See Figure 60 to Figure 70 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P500. Once on the PC board, the 6 V supply is fused and conditioned before connecting to five low dropout linear regulators that supply the proper bias to each of the various sections on the board. When operating the evaluation board in a nondefault condition, L501, L503, L504, L508, and L509 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board independently. Use P501 to connect a different supply for each section. OUTPUT SIGNALS The parallel CMOS outputs interface directly with Analog Devices’ standard single-channel FIFO data capture board (HSC-ADC-EVALB-SC). For more information on the FIFO boards and their optional settings, visit www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz AIN 3.3V + – + – + VDL GND AVDD_3.3V GND VCC 3.3V – GND 3.3V + DRVDD_DUT GND 2.5V – GND – AD9233 EVALUATION BOARD CLK 12-BIT PARALLEL CMOS SPI Figure 59. Evaluation Board Connection Rev. A | Page 28 of 44 HSC-ADC-EVALB-SC FIFO DATA CAPTURE BOARD USB CONNECTION SPI PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE SPI 05492-084 ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER + AMP_VDD ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER 1.8V + – GND 5.0V SWITCHING POWER SUPPLY AVDD_DUT 6V DC 2A MAX AD9233 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS SCLK/DFS Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500. If the SPI port is in external pin mode, the SCLK/DFS pin sets the data format of the outputs. If the pin is left floating, the pin is internally pulled down, setting the default condition to binary. Connecting JP2 Pin 2 and Pin 3 sets the format to twos complement. If the SPI port is in serial pin mode, connecting JP2 Pin 1 and Pin 2 connects the SCLK pin to the on board SPI circuitry. See the Serial Port Interface (SPI) section for more details. VIN SDIO/DCS The evaluation board is set up for a double balun configuration analog input with optimum 50 Ω impedance matching out to 70 MHz. For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed (see Table 8). The common mode of the analog inputs is developed from the center tap of the transformer via the CML pin of the ADC. See the Analog Input Considerations section for more information. If the SPI port is in external pin mode, the SDIO/DCS pin acts to set the duty cycle stabilizer. If the pin is left floating, the pin is internally pulled up, setting the default condition to DCS enabled. To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the SDIO pin to the on-board SPI circuitry. See the Serial Port Interface (SPI) section for more details. VREF ALTERNATIVE CLOCK CONFIGURATIONS VREF is set to 1.0 V by tying the SENSE pin to ground via JP507 (Pin 1 and Pin 2). This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option is also included on the evaluation board. Simply connect JP507 between Pin 2 and Pin 3, connect JP501, and provide an external reference at E500. Proper use of the VREF options is detailed in the Voltage Reference section. A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U500). When using this drive option, the components listed in Table 16 need to be populated. Consult the AD9515 data sheet for further information. The following is a list of the default and optional settings or modes allowed on the AD9233 Rev. A evaluation board. POWER RBIAS RBIAS requires a 10 kΩ (R503) to ground and is used to set the ADC core bias current. CLOCK The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T503) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. PDWN To configure the analog input to drive the AD9515 instead of the default transformer option, the following components need to be added, removed, and/or changed. • Remove R507, R508, C532, and C533 in the default clock path. • Populate R505 with a 0 Ω resistor and C531 in the default clock path. • Populate R511, R512, R513, R515 to R524, U500, R580, R582, R583, R584, C536, C537, and R586. If using an oscillator, two oscillator footprint options are also available (OSC500) to check the performance of the ADC. JP508 provides the user flexibility in using the enable pin, which is common on most oscillators. Populate OSC500, R575, R587, and R588 to use this option. To enable the power-down feature, connect JP506, shorting the PDWN pin to AVDD. CSB The CSB pin is internally pulled-up, setting the chip into external pin mode, to ignore the SDIO and SCLK information. To connect the control of the CSB pin to the SPI circuitry on the evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip into serial pin mode and to enable the SPI information on the SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in the always enabled mode. Rev. A | Page 29 of 44 AD9233 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352 . When using this particular drive option, some components need to be populated as listed in Table 16. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet. To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed and/or changed: • Remove C1 and C2 in the default analog input path. • Populate R3 and R4 with 200 Ω resistors in the analog input path. • Populate the optional amplifier input path with all components, except R594, R595, and C502. Note that to terminate the input path, only one of these components, (R9, R592, or R590 and R591) should be populated. • Populate C529 with a 5 pF capacitor in the analog input path. Currently, R561 and R562 are populated with 0 Ω resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary. Rev. A | Page 30 of 44 S504 Rev. A | Page 31 of 44 Figure 60. Evaluation Board Schematic, DUT Analog Inputs DNI Ampin/ S505 DNI R8 DNI R502 50 DNI GND;3,4,5 SMA200UP R7 DNI R560 0 2 RC0603 2 RC0603 C528 0.1UF C3 DNI CML RC0402 R6 DNI RC0402 R2 0 R11 0 DNI R9 DNI 1 1 RC0603 2 R12 0 DNI RC0603 2 R10 0 DNI C4 0 C5 0 C509 .1UF 4 5 T500 S 4 5 T1 DNI S 4 5 2 3 6 1 P T502 DNI ETC1-1-13 P 3 2 1 3 2 1 CML RC0402 For amplifier (AD8352): Install all optional Amp input components. R590/R591,R9,R592 Only one should be installed at a time. Remove C1, C2. Set R3=R4=200 OHM. DNI DNI When using T502, remove T500, T501. Repalce C1, C2 with 0 ohm resistors. Remove R3, R4. Place R6, R502,. 1 1 GND;3,4,5 SMA200UP GND;3,4,5 SMAEDGE GND;3,4,5 RC060 3 Ampin Ain/ S503 Ain SMAEDGE CC0402 CC0402 S500 RC060 3 CC0402 R590 25 DNI R591 25 DNI R1 DNI RC0402 R592 DNI S T501 P 5 C503 .1UF DNI C500 .1UF DNI R5 0 C2 .1UF AMPOUT- R565 DNI AMPOUT+ RC0402 R597 4.3K DNI R596 0 DNI DNI 2 1 4 RDP VIN RDN 5 16 VIP 2 15 U511 VCM 14 6 7 GND AMPVDD GND VON VCC 8 GND VOP VCC 13 AMPVDD AD8352 DNI SIGNAL=GND;17 ENB 3 disable R594 10K DNI J500 enable 1 RGP R598 100 RGN DNI 3 AMPVDD C501 0.3PF R593 0 DNI R4 25 R3 25 C510 .1UF 9 10 11 12 RC0402 R571 0 R595 10K DNI OPTIONAL AMP INPUT When using R1, remove R3, R4,R6. Replace R5 with 0.1UF cap Replace C1, C2 with 0 ohm resistors. 3 ETC1-1-13 4 2 1 C1 .1UF RC040 2 CC0402 RC0402 RC0402 RC0402 R53 6 R535 C502 .1UF DNI R562 0 CML R561 0 0 0 RC0402 DNI RC0402 DNI 1 D500 DNI R567 33 R566 33 3 VIN+ R574 DNI HSMS281 2 RC040 2 RC0402 C505 .1UF DNI C504 .1UF DNI DUTAVDD 2 RC0402 RC0402 R563 DNI HSMS281 2 AMPOUT- 2 VIN- DUTAVDD C529 20PF D501 DNI AMPOUT+ 1 3 VIN- CC0402 VIN+ 05492-058 DOUBLE BALUN / XFMR INPUT AD9233 SCHEMATICS RC060 3 RC060 3 C556 0.1UF CML R503 10K TP500 TP504 D1 Figure 61. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface Rev. A | Page 32 of 44 E500 48 47 CC0402 E X T_ V R E F 45 D0 46 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DCO JP502 DNI CLK CLK JP506 DNI VIN- VIN+ CC0402 C554 0.1UF VREF SENSE DUTDRVDD DUTAVDD CC0603 RC060 3 chip corners AVDD AGND AVDD AGND CSB SCLK/DFS SDIO/DCS DRVDD DRGND OR (MSB) D11 D10 C555 0.1UF DNI JP501 CC0805 DNI JP500 3 C553 1.0UF DUTAVDD 2 JP507 1 R0402 DNI R501 VREF R0402 DNI R500 SENS E AD9233LFCSP AGND D9 CLK+ D8 EPAD D7 CLKD6 AVDD AGND DRVDD AVDD DRGND OEB D5 DCO D4 D3 NC U510 NC D2 DRGND D1 DRVDD (LSB) D0 SENSE VREF REFB REFT AGND VIN+ VIN– AGND AVDD CML RBIAS PDWN 1 2 3 4 5 6 7 8 9 10 11 12 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 13 DOR 14 TP502 TP501 TP503 DUTDRVDD DUTAVDD 15 16 17 18 19 20 21 22 23 24 8 10 9 9 RP500 22 RP501 22 RP501 22 RP502 22 1 7 8 8 DCO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 DOR 7 6 5 16 15 14 13 12 11 16 15 14 13 12 11 10 RP500 22 RP500 22 RP500 22 RP501 22 RP501 22 RP501 22 RP501 22 RP501 22 RP501 22 RP502 22 RP502 22 RP502 22 RP502 22 RP502 22 RP502 22 RP502 22 CSB_DUT 2 3 4 1 2 3 4 5 6 1 2 3 4 5 6 7 1 JP1 VDL 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3 2 JP2 O10 O7 O6 I7 I6 O0 OUTPUT BUFFER OE1 I0 OE2 O1 I1 GND1 O2 GND8 O3 I2 VCC1 O4 O5 I3 VCC4 I4 I5 GND2 O8 I8 GND7 O9 I9 GND3 I10 GND6 O11 I11 VCC2 O12 I12 VCC3 O13 GND4 I13 GND5 O14 OE4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDIO_ODM O15 3 DUTAVDD I14 U509 74VCX16224 1 I15 OE3 SCLK_DTP 1 JP3 3 FDOR FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FIFOCLK FIFOCLK FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FDOR 2 J503 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 SCLK_CHA SDO_CHA CSB1_CHA SDI_CHA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 J503 OUTPUT CONNECTOR J503 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 05492-059 DUT AD9233 GND;3,4,5 CLK/ SMAEDGE S502 GND;3,4,5 CLK SMAEDGE S501 R505 49.9 DNI C530 0.1UF C531 0.1UF DNI CC0402 RC0402 1 1 OPT_CLK OPT_CLK R575 0 DNI OPT_CLK R504 49.9 CC0402 VCC R511 DNI 2 RC0603 2 RC0603 R579 DNI R510 DNI R512 0 RC0603 RC0603 R576 DNI R507 0 DNI 0 OE OE GND GND CB3LV-3C OUT R508 8 10 OUT 12 VCC 14 DNI C511 .1UF R578 DNI R577 DNI R509 0 R506 0 RC0603 RC0603 D502 HSMS2812 2 1 3 C533 0.1UF C532 0.1UF CLK CLK E501 5 3 2 AD9515 RC0402 DNI OUT0B OUT0 NC=27,28 OUT1B OUT1 AVDD_3P3V;1,4,17,20,21,24,26,29,30 SYNCB CLKB CLK DNI U500 R586 4.12K 18 19 22 23 R584 240 DNI R585 100 DNI R583 240 DNI R582 100 DNI C536 0.1UF DNI C537 0.1UF DNI S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 RC060 3 C534 0.1UF DNI C535 0.1UF DNI E503 E502 CLK CLK To use AD9515 (OPT _CLK), remove R507, R508, C533, C532. Place C531,R505=0. 4 6 3 R580 10K DNI T503 R588 10K DNI 5 1 2 1 AVDD_3P3V R581 DNI 7 5 3 1 RC0402 OSC500 RC0402 RC0402 DISABLE RC0402 2 S7 ENABLE S8 DNI JP508 VREF 6 S0 7 S1 8 S2 9 S3 10 S4 11 S5 12 S6 13 S9 Figure 62. Evaluation Board Schematic, DUT Clock Inputs S10 RC060 3 14 RC060 3 15 3 RSET 16 RC0402 RC0402 CC0402 CC0402 RC0402 10K DNI RC0402 R587 GN D 25 CC0402 RC0402 GND_PAD RC0402 32 CC0402 31 CC0402 AVDD_3P3V RC0402 RC0402 Rev. A | Page 33 of 44 33 CC0402 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 R526 DNI R527 DNI R525 DNI R532 DNI R533 DNI R534 DNI R529 DNI R528 DNI R530 DNI R531 DNI 0 0 0 0 0 0 0 0 0 0 0 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 R522 R523 R524 R519 R518 R520 R521 R516 R517 R515 R513 0 0 0 0 0 0 0 0 0 0 0 RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI RC0603 DNI AD9515 LOGIC SETUP AVDD_3P3V R514 DNI OPT_CLK XFMR/AD9515 Clock Circuitry AD9233 05492-057 2 1 S1 DNI 4 3 1 1 SOIC8 DNI GP1 GP0 VSS RC0603 2 2 1 GP1 3 GP0 5 MCLR-GP3 7 9 Rev. A | Page 34 of 44 HEADER UP MALE DNI J504 E504 5 6 7 8 DNI GP2 MCLR PIC12F629 GP4 GP5 VDD U506 AMPVDD R559 D505 261 Optional DNI 4 3 2 1 DNI 3 PICVCC 1 4 2 6 8 10 PICVCC GP1 GP0 MC LR-GP3 Figure 63. Evaluation Board Schematic, SPI Circuitry R547 4.7K DNI When using PICSPI controlled port, populate R545, R546, R547. When using PICSPI controlled port, remove R555, R556, R557. For FIFO controlled port, populate R555, R556, R557. PIC-HEADER DNI CC0603 2 JP509 C557 0.1UF DNI R558 4.7K A V D D _3 P3 V +5V=PROGRAMMING ONLY=AMPVDD +3.3V=NORMAL OPERATION=AVDD_3P3V RC060 3 SPI CIRCUITRY R545 4.7K RC0603 DNI R546 4.7K RC0603 DNI RC0603 R555 0 R557 0 R556 0 R549 10K AVDD_3P3V R554 0 RC0603 RC0603 RC0603 RC0603 SCLK_CH A RC0603 SDI_CHA R548 10K R550 10K RC0603 RC0603 CSB1_CHA U508 6 Y1 5 VCC 4 Y2 6 Y1 5 VCC 4 Y2 NC7WZ16 1 A1 2 GND 3 A2 U507 NC7WZ07 1 A1 2 GND 3 A2 R552 1K R551 1K R553 1K DUTAVDD AVDD_3P3V RC0603 SDO_CH A RC0603 REMOVE WHEN USING OR PROGRAMMING PIC (U506) CSB_DUT SCLK_DTP SDIO_ODM AD9233 RC0603 05492-056 Figure 64. Evaluation Board Schematic, Power Supply Inputs Rev. A | Page 35 of 44 DUTDRVDDIN GND 5 P5 6 P6 J502 J501 J505 LC1210 L500 10UH LC1210 L506 10UH LC1210 L502 10UH LC1210 L507 10UH LC1210 L505 10UH D504 S2A_RECT 2A DO-214AA ACASE ACASE ACASE ACASE ACASE Remove L501,L503,L504,L508,L509. To use optional power connection GND GND AVDD_3P3VIN 9 P9 10 P10 8 P8 VDLIN GND AMPVDDIN DUTAVDDIN 7 P7 C527 10UF SMDC110F 3 C548 1OUF 6.3V C552 1OUF 6.3V C551 1OUF 6.3V C550 1OUF 6.3V C549 1OUF 6.3V C512 0.1UF AVDD_3P3V C517 0.1UF DUTDRVDD C516 0.1UF DUTAVDD C515 0.1UF VDL C514 0.1UF AMPVDD OPTIONAL POWER CONNECTION 4 P4 2 3 P3 3 GND 1 2 P2 P501 1 P1 7.5V POWER CON005 2.5MM JACK P500 4 FER500 CHOKE_COIL DUTDRVDD DUTAVDD VDL AMPVDD PWR_IN CC0603 CC0603 CC0603 CC0603 C573 0.1UF C569 0.1UF C564 0.1UF C567 0.1UF R589 261 C572 0.1UF C575 0.1UF C565 0.1UF CC0603 CC0603 CC0603 CC0603 C524 1UF PWR_IN C521 1UF PWR_IN C519 1UF PWR_IN CC0603 C599 0.1UF CC0603 0.1UF C570 0.1UF 4 4 4 CC0603 2 O UTP U T1 OUTPUT4 CC0603 C559 CC0603 C566 0.1UF IN P U T C558 CC0603 2 O UTP U T1 OUTPUT4 U504 ADP3339AKC-3.3 IN P U T U503 ADP3339AKC-2.5 2 O UTP U T1 OUTPUT4 U502 ADP3339AKC-1.8 IN P U T 0.1UF C568 0.1UF 3 3 3 GND 1 GND 1 GND 1 C574 0.1UF CC0402 C540 0.1UF CC0402 C545 0.1UF VDLIN CC0402 CC0402 C513 1UF PWR_IN C523 1UF PWR_IN DUTDRVDDIN DUTAVDDIN TP508 TP505 AVDD_3P3V LC1210 L508 10UH LC1210 L503 10UH AVDD_3P3V C526 1UF C520 1UF C518 1UF L504 10UH LC1210 TP506 C539 0.1UF C544 0.1UF 3 3 O UTP U T1 OUTPUT4 CC0402 CC0402 INP UT C542 0.1UF C546 0.1UF CC0402 CC0402 C538 0.1UF C543 0.1UF O U TP UT 1 OUTPUT4 U505 ADP3339AKC-3.3 INP UT U501 ADP3339AKC-5 DUTAVDD=1.8V DUTDRVDD=2.5V VDL=3.3V AMPVDD=5V AVDD_3.3V=3.3V GND 1 GND 1 F500 D503 3A SHOT_RECT DO-214AB 2 2 LC1210 L509 10UH LC1210 L501 10UH C525 1UF C522 1UF TEST POINTS GROUND 4 4 TP510 2 TP512 CR500 TP511 1 TP509 Power Supply Input 6V, 2A max H503 H502 Connected to Ground Mounting Holes H500 H501 AVDD_3P3V AMPVDDIN TP513 TP507 AD9233 05492-055 AD9233 05492-063 EVALUATION BOARD LAYOUTS 05492-062 Figure 65. Evaluation Board Layout, Primary Side Figure 66. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. A | Page 36 of 44 05492-065 AD9233 05492-064 Figure 67. Evaluation Board Layout, Ground Plane Figure 68. Evaluation Board Layout, Power Plane Rev. A | Page 37 of 44 05492-061 AD9233 05492-060 Figure 69. Evaluation Board Layout, Silkscreen Primary Side Figure 70. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image) Rev. A | Page 38 of 44 AD9233 BILL OF MATERIALS (BOM) Table 16. Evaluation Board BOM Item 1 2 Qty. 1 24 Omit (DNI) 3 4 5 10 6 7 8 9 10 1 1 5 1 15 11 1 Reference Designator AD9246CE_REVA C1, C2, C509, C510, C511, C512, C514, C515, C516, C517, C528, C530, C532, C533, C538, C539, C540, C542, C543, C544, C545, C546, C554, C555 C3, C500, C502, C503, C504, C505, C531, C534, C535, C536, C537, C557 C501 C4, C5 C513, C518, C519, C520, C521, C522, C523, C524, C525, C526 C527 C529 C548, C549, C550, C551, C552 C553 C556, C558, C559, C564, C565, C566, C567, C568, C569, C570, C572, C573, C574, C575, C599 CR500 12 1 D502 Diode SOT-23 30 V, 20 mA, dual Schottky 13 1 D500, D501 D503 Diodes Diode DO-214AB 3 A, 30 V, SMC 14 1 D504 Diode DO-214AA 2 A, 50 V, SMC 15 16 1 D505 F500 LED Fuse LN1461C 1210 AMB 6.0 V, 2.2 A trip current resettable fuse 17 1 FER500 Choke 2020 J500 J501, J502, J505 J503 Jumper Jumpers Connector 120 Pin Solder jumper Solder jumper Male header Connector Jumpers 10 Pin 3 Pin Male, 2 × 5 Male, straight 12 1 2 2 18 19 20 1 1 3 1 1 Device PCB Capacitors Package 0402 Description PCB 0.1 μF Capacitor Resistors Capacitors 0402 0402 0402 0.3 pF 0Ω 1.0 μF Capacitor Capacitor Capacitors Capacitor Capacitors 1206 0402 ACASE 0805 0603 10 μF 20 pF 10 μF 1.0 μF 0.1 μF LED 0603 Green 3 J504 JP1, JP2, JP3 23 4 JP500, JP501, JP502, JP506 Jumpers 2 Pin Male, straight 24 1 JP507 Jumpers 3 Pin Male, straight 25 10 JP508, JP509 L500, L501, L502, L503, L504, L505, L506, L507, L508, L509 Ferrite Beads 1 OSC500 Oscillator 3.2 mm × 2.5 mm × 1.6 mm SMT 1 P500 P501 Connector Connector PJ-102A 10 Pin 26 27 28 1 Rev. A | Page 39 of 44 Panasonic LNJ314G8TRA HSMS2812 Micro Commercial Group SK33-TPMSCT-ND Micro Commercial Group S2A-TPMSTR-ND Amber LED Tyco, Raychem NANO SMDC110F-2 Murata DLW5BSN191SQ2 21 22 2 Supplier/Part No. Analog Devices, Inc. Samtec TSW-140-08-G-T-RA Samtec Samtec TSW-103-07-G-S Samtec TSW-102-07-G-S Samtec TSW-103-07-G-S Digi-Key P9811CT-ND 125 MHz or 105 MHz DC power jack Male, straight CTS Reeves CB3LV-3C Digi-Key CP-102A-ND PTMICRO10 AD9233 Item 29 30 Qty. Omit (DNI) 6 Package 0402 0402 Description DNI 0Ω 0402 0603 0402 0603 0603 25 Ω DNI DNI 10 kΩ 49.9 Ω 0603 0Ω Resistors Resistors Resistors 0603 0603 0603 4.7 kΩ 1 kΩ 261 Ω Resistors Resistors Resistors Resistor Resistors Resistors Resistor Resistors Resistors Resistor Resistor Resistors Switch 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 RCA74204 RCA74208 S500, S501 Connectors SMAEDGE 33 Ω 100 Ω 240 Ω 4.12 kΩ 10 kΩ 25 Ω DNI 0Ω 10 kΩ 4.3 kΩ 22 Ω 22 Ω Momentary (normally open) SMA edge right angle 2 2 S502, S503 S504, S505 Connectors SMA200UP T500, T501 T1 T503 Transformers SM-22 M/A-Com ETC1-1-13 1 Transformer CD542 Mini-Circuits ADT1-1WT T502 U500 IC 32-Lead LFCSP Clock distribution Analog Devices, Inc. AD9515BCPZ Analog Devices, Inc. ADP3339AKCZ-5 Analog Devices, Inc. ADP3339AKCZ-1.8 Analog Devices, Inc. ADP3339AKCZ-2.5 Analog Devices, Inc. ADP3339AKCZ-3.3 5 6 31 32 33 34 35 2 6 6 4 1 1 36 9 23 37 38 39 4 3 1 1 40 41 42 43 44 45 46 47 48 49 50 51 52 2 53 2 3 2 1 3 2 1 2 2 1 1 2 1 54 55 56 2 1 1 1 57 Reference Designator R1, R6, R563, R565, R574, R577 R2, R5, R561, R562, R571 R10, R11, R12, R535, R536, R575 R3, R4 R7, R8, R9, R502, R510, R511 R500, R501, R576, R578, R579, R581 R503, R548, R549, R550 R504 R505 R506, R508, R509, R512, R554, R555, R556, R557, R560 R507, R514, R513, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534 R545, R546, R547, R558 R551, R552, R553 R589 R559 R566, R567 R582, R585, R598 R583, R584 R586 R580, R587, R588 R590, R591 R592 R593, R596 R594, R595 R597 RP500 RP501, RP502 S1 Device Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistor Resistor Resistors Panasonic EVQ-PLDA15 SMA RF 5-pin upright 58 1 U501 IC SOT-223 Voltage regulator 59 1 U502 IC SOT-223 Voltage regulator 60 1 U503 IC SOT-223 Voltage regulator 61 2 U504, U505 ICs SOT-223 Voltage regulator Rev. A | Page 40 of 44 Supplier/Part No. AD9233 Item 62 Qty. 63 64 65 66 Reference Designator U506 Device IC Package 8-pin SOIC 1 1 1 U507 U508 U509 IC IC IC 1 U510 DUT (AD9233) IC SC70 SC70 48-Lead TSSOP 48-Lead LFCSP 16-Lead LFCSP 67 Total Omit (DNI) 1 1 128 U511 (or Z500) 107 Rev. A | Page 41 of 44 Description 8-bit microcontroller Dual buffer Dual buffer Buffer/line driver Supplier/Part No. Microchip PIC12F629 ADC Analog Devices, Inc. AD9233BCPZ Analog Devices, Inc. AD8352ACPZ Differential amplifier Fairchild NC7WZ16 Fairchild NC7WZ07 Fairchild 74VCX162244 AD9233 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX 48 PIN 1 INDICATOR 1 EXPOSED PAD 6.75 BSC SQ 4.25 4.10 SQ 3.95 (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 71. 48-Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters ORDERING GUIDE Model AD9233BCPZ-125 2 AD9233BCPZRL7–1252 AD9233BCPZ-1052 AD9233BCPZRL7–1052 AD9233BCPZ-802 AD9233BCPZRL7–802 AD9233-125EB AD9233-105EB AD9233-80EB 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFSCP_VQ] 48-Lead Lead Frame Chip Scale Package [LFSCP_VQ] 48-Lead Lead Frame Chip Scale Package [LFSCP_VQ] 48-Lead Lead Frame Chip Scale Package [LFSCP_VQ] 48-Lead Lead Frame Chip Scale Package [LFSCP_VQ] 48-Lead Lead Frame Chip Scale Package [LFSCP_VQ] Evaluation Board Evaluation Board Evaluation Board It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance . Z = Pb-free part. Rev. A | Page 42 of 44 Package Option 1 CP-48-3 CP-48-3 CP-48-3 CP-48-3 CP-48-3 CP-48-3 AD9233 NOTES Rev. A | Page 43 of 44 AD9233 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05492-0-8/06(A) Rev. A | Page 44 of 44