Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp ADA4857-1/ADA4857-2 APPLICATIONS Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers CONNECTION DIAGRAMS ADA4857-1 TOP VIEW (Not to Scale) PD 1 8 +VS FB 2 7 OUT –IN 3 6 NC +IN 4 5 –VS 07040-001 High speed 850 MHz, −3 dB bandwidth (G = +1, RL = 1 kΩ, LFSCP) 750 MHz, −3 dB bandwidth (G = +1, RL = 1 kΩ, SOIC) 2800 V/μs slew rate Low distortion: −88 dBc @ 10 MHz (G = +1, RL = 1 kΩ) Low power: 5 mA/amplifier @ 10 V Low noise: 4.4 nV/√Hz Wide supply voltage range: 5 V to 10 V Power-down feature Available in 3 mm × 3 mm 8-lead LFCSP (single), 8-lead SOIC (single), and 4 mm × 4 mm 16-lead LFCSP (dual) NC = NO CONNECT Figure 1. 8-Lead LFCSP (CP) ADA4857-1 TOP VIEW (Not to Scale) FB 1 8 PD –IN 2 7 +VS +IN 3 6 OUT –VS 4 5 NC NC = NO CONNECT 07040-002 FEATURES Figure 2. 8-Lead SOIC (R) ADA4857-2 +IN1 2 12 –VS1 11 NC NC 3 10 +IN2 –VS2 4 9 –IN2 FB2 8 PD2 7 +VS2 6 OUT2 5 –IN1 1 NC = NO CONNECT 07040-003 14 +VS1 13 OUT1 16 FB1 15 PD1 TOP VIEW (Not to Scale) Figure 3. 16-Lead LFCSP (CP) GENERAL DESCRIPTION The ADA4857 is a unity gain stable, high speed, voltage feedback amplifier with low distortion, low noise, and high slew rate. With a spurious-free dynamic range (SFDR) of −88 dBc @ 10 MHz, the ADA4857 is an ideal solution in a variety of applications including ultrasounds, ATE, active filters, and ADC drivers. The Analog Devices, Inc., proprietary next-generation XFCB process and innovative architecture enables such high performance amplifiers. The ADA4857 has 850 MHz bandwidth, 2800 V/μs slew rate, and settles to 0.1% in 15 ns. With a wide supply voltage range (5 V to 10 V), the ADA4857 is an ideal candidate for systems that require high dynamic range, precision, and speed. The ADA4857-1 amplifier is available in a 3 mm × 3 mm, 8-lead LFCSP and a standard 8-lead SOIC. The ADA4857-2 is available in a 4 mm × 4 mm, 16-lead LFSCP. The LFCSP features an exposed paddle that provides a low thermal resistance path to the PCB. This path enables more efficient heat transfer and increases reliability. The ADA4857 works over the extended industrial temperature range (−40°C to +125°C). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADA4857-1/ADA4857-2 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications....................................................................................... 1 Test Circuits..................................................................................... 15 Connection Diagrams...................................................................... 1 Applications Information .............................................................. 16 General Description ......................................................................... 1 PD Pin Operation....................................................................... 16 Revision History ............................................................................... 2 Capacitive Load Considerations .............................................. 16 Specifications..................................................................................... 3 Recommended Values for Various Gains................................ 16 ±5 V Supply ................................................................................... 3 Noise ............................................................................................ 17 +5 V Supply ................................................................................... 4 Circuit Considerations .............................................................. 17 Absolute Maximum Ratings............................................................ 6 PCB Layout ................................................................................. 17 Thermal Resistance ...................................................................... 6 Power Supply Bypassing ............................................................ 17 Maximum Power Dissipation ..................................................... 6 Grounding ................................................................................... 17 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 18 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 19 REVISION HISTORY 5/08—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADA4857-1/ADA4857-2 SPECIFICATIONS ±5 V SUPPLY TA = 25°C, G = +2, RG = RF = 499 Ω, RL = 1 kΩ to ground, PD = no connect, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth (LFCSP/SOIC) Full Power Bandwidth Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) Slew Rate (10% to 90%) Settling Time to 0.1% NOISE/Harmonic PERFORMANCE Harmonic Distortion Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain PD (Power-Down) Pin PD Input Voltage Turn-Off Time Turn-On Time PD Pin Leakage Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive Conditions Min Typ G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p, THD < −40 dBc G = +2, VOUT = 2 V p-p, RL = 150 Ω G = +1, VOUT = 4 V step G = +2, VOUT = 2 V step 650 850/750 600/550 400/350 110 75/90 2800 15 MHz MHz MHz MHz MHz V/μs ns f = 1 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 1 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 100 kHz f = 100 kHz −108 −108 −88 −93 −65 −62 4.4 1.5 dBc dBc dBc dBc dBc dBc nV/√Hz pA/√Hz VOUT = −2.5 V to +2.5 V ±2 2.3 −2 24.5 50 57 Chip powered down Chip enabled 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 Chip enabled Chip powered down ≥(VCC − 2) ≤(VCC − 4.2) 55 33 58 80 V V μs ns μA μA Common mode Differential mode Common mode 8 4 2 ±4 −86 MΩ MΩ pF V dB 10 ±4 ±3.7 50 125 10 ns V V mA mA pF VCM = ±1 V −78 VIN = ±2.5 V, G = +2 RL = 1 kΩ RL = 100 Ω Sinking and sourcing 30% overshoot, G = +2 Rev. 0 | Page 3 of 20 Max ±4.5 −3.3 Unit mV μV/°C μA nA/°C nA dB ADA4857-1/ADA4857-2 Parameter POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Power Down) Positive Power Supply Rejection Negative Power Supply Rejection Conditions Min Typ 4.5 PD ≥ VCC − 2 V +VS = 4.5 V to 5.5 V, −VS = −5 V +VS = 5 V, −VS = −4.5 V to −5.5 V −59 −65 5 350 −62 −68 Max Unit 10.5 5.5 450 V mA μA dB dB Max Unit +5 V SUPPLY TA = 25°C, G = +2, RF = RG = 499 Ω, RL = 1 kΩ to midsupply, PD = no connect, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth (LFCSP/SOIC) Full Power Bandwidth Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) Slew Rate (10% to 90%) Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain PD (Power-Down) Pin PD Input Voltage Turn-Off Time Turn-On Time PD Pin Leakage Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Conditions Min Typ G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p, THD < −40 dBc G = +2, VOUT = 2 V p-p, RL = 150 Ω G = +1, VOUT = 2 V step G = +2, VOUT = 2 V step 595 800/750 500/400 360/300 95 50/40 1500 15 MHz MHz MHz MHz MHz V/μs ns f = 1 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 1 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 100 kHz f = 100 kHz −92 −90 −81 −71 −69 −55 4.4 1.5 dBc dBc dBc dBc dBc dBc nV/√Hz pA/√Hz VOUT = 1.25 V to 3.75 V ±1 4.6 −1.7 24.5 50 57 Chip powered down Chip enabled 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 Chip enable Chip powered down ≥(VCC − 2) ≤(VCC − 4.2) 38 30 8 30 V V μs ns μA μA Common mode Differential mode Common mode 8 4 2 1 to 4 −84 MΩ MΩ pF V dB VCM = 2 V to 3 V Rev. 0 | Page 4 of 20 −76 ±4.2 −3.3 mV μV/°C μA nA/°C nA dB ADA4857-1/ADA4857-2 Parameter OUTPUT CHARACTERISTICS Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Power Down) Positive Power Supply Rejection Negative Power Supply Rejection Conditions Min G = +2 RL = 1 kΩ RL = 100 Ω Typ 15 1 to 4 1.1 to 3.9 50 75 10 Sinking and sourcing 30% overshoot, G = +2 4.5 PD ≥ VCC − 2 V +VS = 4.5 V to 5.5 V, −VS = 0 V +VS = 5 V, −VS = −0.5 V to +0.5 V Rev. 0 | Page 5 of 20 Max −58 −65 4.5 250 −62 −68 Unit ns V V mA mA pF 10.5 5 350 V mA μA dB dB ADA4857-1/ADA4857-2 ABSOLUTE MAXIMUM RATINGS Table 3. Rating 11 V See Figure 4 −VS + 0.7 V to +VS − 0.7 V ±VS −VS −65°C to +125°C −40°C to +125°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. θJC 15 34.8 19 ⎞ VOUT 2 ⎟– ⎟ RL ⎠ RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS × I S ) + (VS /4 )2 RL In single-supply operation with RL referenced to −VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduce θJA. Unit °C/W °C/W °C/W 3.0 MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4857 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4857. Exceeding a junction temperature of 175°C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. 2.5 2.0 ADA4857-2 (LFCSP) 1.5 1.0 ADA4857-1 (LFCSP) 0.5 ADA4857-1 (SOIC) 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) 07040-004 θJA 115 94.5 68.2 ⎛V V PD = (VS × I S ) + ⎜⎜ S × OUT RL ⎝ 2 Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC and LFCSP packages on a JEDEC standard 4-layer board. θJA values are approximations. Table 4. Package Type 8-Lead SOIC 8-Lead LFCSP 16-Lead LFSCP PD = Quiescent Power + (Total Drive Power − Load Power) MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Exposed Paddle Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4857 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION Rev. 0 | Page 6 of 20 ADA4857-1/ADA4857-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS –IN 3 TOP VIEW (Not to Scale) FB 1 8 +VS 7 OUT –IN 2 NC = NO CONNECT PD +VS TOP VIEW +IN 3 (Not to Scale) 6 OUT –VS 4 5 NC 6 NC 5 –VS +IN 4 8 ADA4857-1 7 NC = NO CONNECT 07040-006 FB 2 ADA4857-1 07040-005 PD 1 Figure 6. 8-Lead SOIC Pin Configuration Figure 5. 8-Lead LFCSP Pin Configuration Table 5. 8-Lead LFCSP Pin Function Descriptions Table 6. 8-Lead SOIC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Pin No. 1 2 3 4 5 6 7 8 Mnemonic PD FB −IN +IN −VS NC OUT +VS Description Power Down Feedback Inverting Input Noninverting Input Negative Supply No Connect Output Positive Supply Rev. 0 | Page 7 of 20 Mnemonic FB −IN +IN −VS NC OUT +VS PD Description Feedback Inverting Input Noninverting Input Negative Supply No Connect Output Positive Supply Power Down 14 +VS1 13 OUT1 16 FB1 15 PD1 ADA4857-1/ADA4857-2 –IN1 1 NC 3 ADA4857-2 TOP VIEW (Not to Scale) –VS2 4 12 –VS1 11 NC 10 +IN2 FB2 8 PD2 7 +VS2 6 OUT2 5 9 –IN2 NC = NO CONNECT 07040-007 +IN1 2 Figure 7. 16-Lead LFCSP Pin Configuration Table 7. 16-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3, 11 4 5 6 7 8 9 10 12 13 14 15 16 Mnemonic −IN1 +IN1 NC −VS2 OUT2 +VS2 PD2 FB2 −IN2 +IN2 −VS1 OUT1 +VS1 PD1 FB1 Description Inverting Input 1 Noninverting Input 1 No Connect Negative Supply 2 Output 2 Positive Supply 2 Power Down 2 Feedback 2 Inverting Input 2 Noninverting Input 2 Negative Supply 1 Output 1 Positive Supply 1 Power Down 1 Feedback 1 Rev. 0 | Page 8 of 20 ADA4857-1/ADA4857-2 TYPICAL PERFORMANCE CHARACTERISTICS 3 2 2 G = +2 –2 –3 –4 G = +10 –5 –6 G = +5 –7 –8 VS = ±5V RL = 1kΩ VOUT = 0.2V p-p –9 –10 1 10 100 1000 FREQUENCY (MHz) –3 –4 G = +10 –5 G = +5 –6 –7 –8 VS = ±5V RL = 1kΩ VOUT = 2V p-p –9 1 10 100 3 9 2 8 7 10pF 5pF 6 CLOSED-LOOP GAIN (dB) 0 –1 –2 ±5V –3 –4 –5 –6 +5V –7 5 4 NO CAP LOAD 3 2 1 0 –1 –2 –3 –4 –8 G = +1 RL = 1kΩ VOUT = 0.2V p-p –9 1 G = +2 VS = ±5V RL = 1kΩ VOUT = 0.2V p-p –5 –6 10 100 1000 FREQUENCY (MHz) –7 2 1 1 0 0 CLOSED-LOOP GAIN (dB) 3 2 –40°C –2 –3 –4 –5 +25°C –7 +125°C FREQUENCY (MHz) 1000 1000 –1 –2 –3 4V p-p –4 –5 –6 –7 G = +1 VS = ±5V RL = 100Ω –9 100 100 1V p-p –8 –10 07040-010 –8 G = +1 VS = ±5V –9 RL = 1kΩ VOUT = 0.2V p-p –10 1 10 10 Figure 12. Small Signal Frequency Response for Various Capacitive Loads (LFCSP) 3 –6 1 FREQUENCY (MHz) Figure 9. Small Signal Frequency Response for Various Supply Voltages (LFCSP) –1 1000 Figure 11. Large Signal Frequency Responses for Various Gains (LFCSP) 07040-009 CLOSED-LOOP GAIN (dB) G = +2 –2 FREQUENCY (MHz) 1 CLOSED-LOOP GAIN (dB) –1 –10 Figure 8. Small Signal Frequency Responses for Various Gains (LFCSP) –10 G = +1 0 07040-012 –1 1 07040-011 G = +1 0 1 10 100 1000 FREQUENCY (MHz) Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP) Rev. 0 | Page 9 of 20 Figure 13. Large Signal Frequency Response vs. VOUT (LFCSP) 07040-013 1 NORMALIZED CLOSED-LOOP GAIN (dB) 3 07040-008 NORMALIZED CLOSED-LOOP GAIN (dB) T = 25°C, (G = +1, RF = 0 Ω, RG open and G = +2, RF = RG = 499 Ω), unless otherwise noted. ADA4857-1/ADA4857-2 3 9 8 2 RL = 1kΩ 1 5 CLOSED-LOOP GAIN (dB) 4 3 2 RL = 100Ω 1 0 –1 –2 –3 –4 1 10 100 1000 FREQUENCY (MHz) –6 –7 G = +1 VS = ±5V VOUT = 2V p-p 1 10 100 1000 Figure 17. Large Signal Frequency Response for Various Resistive Loads (LFCSP) 3 1 NORMALIZED CLOSED-LOOP GAIN (dB) 2 G = +1 0 –1 G = +2 –2 –3 –4 G = +10 –5 –6 G = +5 –7 –8 VS = 5V RL = 1kΩ VOUT = 0.2V p-p –9 1 10 100 1000 FREQUENCY (MHz) –50 G = +1 1 0 G = +2 –1 –2 –3 –4 G = +10 –5 –6 G = +5 –7 –8 VS = ±5V RL = 1kΩ VOUT = 0.2V p-p –9 1 10 1000 Figure 18. Small Signal Frequency Response for Various Gains (SOIC) –40 VS = ±5V VOUT = 2V p-p RL= 1kΩ –50 G = +1 VS = ±5V VOUT = 2V p-p –60 DISTORTION (dBc) –60 G = +1, HD2 –70 –80 G = +2, HD2 G = +1, HD3 –90 RL = 100Ω, HD3 –70 –80 RL = 100Ω, HD2 –90 RL = 1kΩ, HD2 –100 –100 –110 –110 RL = 1kΩ, HD3 1 10 100 FREQUENCY (MHz) 07040-016 G = +2, HD3 –120 0.2 100 FREQUENCY (MHz) Figure 15. Small Signal Frequency Response for Various Gains (LFCSP) –40 2 –10 07040-015 NORMALIZED CLOSED-LOOP GAIN (dB) –5 FREQUENCY (MHz) 3 DISTORTION (dBc) RL = 100Ω –4 –10 Figure 14. Small Signal Frequency Response for Various Resistive Loads (LFCSP) –10 –3 07040-018 –7 –2 –9 07040-014 –6 RL = 1kΩ –8 G = +2 VS = ±5V VOUT = 0.2V p-p –5 0 –1 Figure 16. Harmonic Distortion vs. Frequency and Gain (LFCSP) –120 0.2 1 10 100 FREQUENCY (MHz) Figure 19. Harmonic Distortion vs. Frequency and Load (LFCSP) Rev. 0 | Page 10 of 20 07040-019 CLOSED-LOOP GAIN (dB) 6 07040-017 7 ADA4857-1/ADA4857-2 –40 0.5 G = +2 VS = ±5V RL= 1kΩ –50 VOUT = 2V p-p G = +2 VS = ±5 0.4 HD3, f = 10MHz 0.3 HD2, f = 10MHz SETTLING TIME (%) –70 –80 –90 HD3, f = 1MHz HD2, f = 1MHz 0.1 OUTPUT 0 –0.1 –0.2 –0.3 –110 INPUT 07040-023 –100 0.2 –0.4 2 3 4 5 6 7 OUTPUT VOLTAGE (V p-p) 8 –0.5 TIME (5ns/DIV) Figure 20. Harmonic Distortion vs. Output Voltage 6.3 6.3 VS = ±5V G = +2 RL= 150Ω 6.1 VOUT = 2V p-p 6.0 5.9 VOUT = 0.2V p-p 1 10 100 FREQUENCY (MHz) Figure 21. 0.1 dB Flatness vs. Frequency for Various Output Voltages (SOIC) 2.0 6.0 VOUT = 2V p-p 5.9 VOUT = 0.2V p-p 5.7 2.5 VS = ±5V RL = 1kΩ G = +2 4V p-p 2.0 100 VS = ±5V RL = 1kΩ G = +1 1.5 OUTPUT VOLTAGE (V) 2V p-p OUTPUT VOLTAGE (V) 10 Figure 24. 0.1 dB Flatness vs. Frequency for Various Output Voltages (LFCSP) 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 2V p-p 1.0 0.5 0 –0.5 –1.0 07040-022 –1.5 –2.0 –2.5 1 FREQUENCY (MHz) 2.5 4V p-p 6.1 5.8 07040-021 5.8 5.7 VS = ±5V G = +2 RL= 150Ω 6.2 CLOSED-LOOP GAIN (dB) 6.2 CLOSED-LOOP GAIN (dB) Figure 23. Short-Term Settling Time (LFCSP) 07040-024 1 07040-020 –120 –2.0 –2.5 TIME (10ns/DIV) Figure 22. Large Signal Transient Response for Various Output Voltages (SOIC) 07040-025 DISTORTION (dBc) –60 TIME (10ns/DIV) Figure 25. Large Signal Transient Response for Various Output Voltages (LFCSP) Rev. 0 | Page 11 of 20 ADA4857-1/ADA4857-2 0.25 2.0 VS = ±5V RL = 1kΩ G = +1 0.20 OUTPUT VOLTAGE (V) 1.2 0.10 CL = 1.5pF 0 –0.05 –0.10 –0.15 CL = 10pF –0.20 –0.25 0 –0.4 –0.8 RL = 100Ω –1.6 –2.0 TIME (10ns/DIV) TIME (10ns/DIV) Figure 29. Large Signal Transient Response for Various Load Resistances (SOIC) 2.0 0.25 RL = 1kΩ G = +1 0.20 0.15 1.6 0.10 0.05 VS = ±5V G = +1 RL = 1kΩ 1.2 VS = ±5V OUTPUT VOLTAGE (V) VS = ±2.5V 0 –0.05 –0.10 0.8 0.4 0 –0.4 –0.8 –1.2 –0.20 –0.25 –2.0 TIME (10ns/DIV) Figure 27. Small Signal Transient Response for Various Supply Voltages (LFCSP) TIME (10ns/DIV) Figure 30. Large Signal Transient Response for Various Load Resistances (LFCSP) 100 CLOSED-LOOP INPUT IMPEDANCE (kΩ) VS = ±5V 100 10 G = +5 1 G = +2 10 100 1000 FREQUENCY (MHz) 07040-028 1 0.1 0.1 RL = 100Ω –1.6 07040-030 07040-027 –0.15 Figure 28. Output Impedance vs. Frequency for Various Gains VS = ±5V G = +2 10 1 0.1 0.01 1 10 100 FREQUENCY (MHz) Figure 31. Closed-Loop Input Impedance vs. Frequency Rev. 0 | Page 12 of 20 1000 07040-031 OUTPUT VOLTAGE (V) RL = 1kΩ 0.4 –1.2 Figure 26. Small Signal Transient Response for Various Capacitive Loads (LFCSP) CLOSED-LOOP OUTPUT IMPEDANCE (Ω) 0.8 07040-029 0.05 07040-026 OUTPUT VOLTAGE (V) 0.15 1000 VS = ±5V G = +2 1.6 ADA4857-1/ADA4857-2 GAIN 40 –20 –10 –40 –20 –60 –80 30 –100 20 –120 10 –140 0 0 –40 –50 LFCSP –60 –70 –80 10 –90 –180 1000 100 –100 0.1 07040-032 1 FREQUENCY (MHz) 1 8 OUTPUT RL = 100Ω –2 –4 OUTPUT RL = 1kΩ –6 INPUT –8 2 0 –2 –4 OUTPUT RL = 1kΩ 2 × INPUT –6 OUTPUT RL = 100Ω 07040-036 OUTPUT VOLTAGE (V) 0 07040-033 OUTPUT VOLTAGE (V) 4 2 –8 TIME (40ns/DIV) TIME (200ns/DIV) Figure 33. Input Overdrive Recovery for Various Resistive Loads 0 1000 VS = ±5V G = +2 6 4 10 100 Figure 35. PD Isolation vs. Frequency VS = ±5V G = +1 6 10 FREQUENCY (MHz) Figure 32. Open-Loop Gain and Phase vs. Frequency 8 SOIC –30 –160 –10 0.1 G = +2 VS = ±5V RL = 1kΩ PD = 3V 07040-035 50 0 PD ISOLATION (dB) 60 Figure 36. Output Overdrive Recovery for Various Resistive Loads –30 VS = ±5V RL= 1kΩ VS = ±5V RL= 1kΩ –40 –10 –20 CMRR (dB) –50 –30 –40 –50 –60 –70 +PSRR –60 –80 –80 0.1 –PSRR 1 10 100 1000 FREQUENCY (MHz) –90 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 37. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. 0 | Page 13 of 20 07040-037 –70 07040-034 PSRR (dB) OPEN-LOOP GAIN (dB) VS = ±5V RL = 1kΩ PHASE OPEN-LOOP PHASE (Degrees) 70 ADA4857-1/ADA4857-2 1000 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 100 10 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 40. Input Voltage Noise vs. Frequency Figure 38. Input Current Noise vs. Frequency 3.5 50 N = 238 MEAN: 5.00 SD: 0.02 3.0 40 VOLTAGE (V) 2.5 30 20 PD INPUT 2.0 1.5 1.0 0.5 OUTPUT 10 0 4.85 4.90 4.95 5.00 5.05 SUPPLY CURRENT (mA) 5.10 5.15 Figure 39. Supply Current 07040-043 0 07040-042 COUNT VS = ±5V 07040-041 VOLTAGE NOISE (nV/√Hz) VS = ±5V 07040-050 CURRENT NOISE (pA/√Hz) 100 –0.5 TIME (20µs/DIV) Figure 41. Disable/Enable Switching Speed Rev. 0 | Page 14 of 20 ADA4857-1/ADA4857-2 TEST CIRCUITS +VS +VS 10µF 10µF + + 0.1µF 0.1µF RG RF 0.1µF VOUT VIN RL 49.9Ω CL 49.9Ω 0.1µF 07040-049 –VS RL 10µF 07040-047 0.1µF + + VOUT RSNUB VIN 10µF 0.1µF 40Ω –VS Figure 42. Noninverting Load Configuration Figure 45. Typical Capacitive Load Configuration +VS AC +VS 10µF + 49.9Ω 0.1µF VOUT VOUT RL RL 49.9Ω AC 07040-045 0.1µF –VS –VS Figure 43. Positive Power Supply Rejection Figure 46. Negative Power Supply Rejection +VS 10µF + 1kΩ 0.1µF 1kΩ 0.1µF VOUT 1kΩ 53.6Ω RL 1kΩ 0.1µF –VS 07040-046 10µF + VIN 07040-048 + 10µF Figure 44. Common-Mode Rejection Rev. 0 | Page 15 of 20 ADA4857-1/ADA4857-2 APPLICATIONS INFORMATION PD PIN OPERATION CAPACITIVE LOAD CONSIDERATIONS The PD pin is used to power down the chip, which reduces the quiescent current and the overall power consumption. It is low enabled which means that the chip is on with full power when the PD pin input voltage is low (see Table 8). Note that PD does not put the output in a high-Z state, which means that the ADA4857 should not be used as a multiplexer. When driving a capacitive load, RSNUB is used to reduce the peaking (see Figure 45). An optimum resistor value of 40 Ω is found to maintain the peaking within 1 dB for any capacitive load up to 40 pF. Table 8. PD Operation Table Guide PD Pin Voltage ≤+0.8 V ≥+3 V ≤−1.7 V ≥+0.5 V ≤+0.8 V ≥+3 V No connect Supply Voltage ±5 V ±5 V ±2.5 V ±2.5 V +5 V +5 V All Chip Enabled Powered down Enabled Powered down Enabled Powered down Enabled B RECOMMENDED VALUES FOR VARIOUS GAINS Table 9 provides a useful reference for determining various gains and associated performance. Resistors RF and RG are kept low to minimize their contribution to the overall noise performance of the amplifier. Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω Gain +1 +2 +5 +10 RF (Ω) 0 499 499 499 RG (Ω) N/A 499 124 56.2 −3 dB SS BW (MHz), VOUT = 200 mV p-p 850 360 90 43 Slew Rate (V/μs), VOUT = 2 V Step 2350 1680 516 213 Rev. 0 | Page 16 of 20 ADA4857 Voltage Noise (nV/√Hz), RTO 4.4 8.8 22.11 43.47 Total System Noise (nV/√Hz), RTO 4.49 9.89 23.49 45.31 ADA4857-1/ADA4857-2 NOISE CIRCUIT CONSIDERATIONS To analyze the noise performance of an amplifier circuit, identify the noise sources and then determine if the source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nV/√Hz, is equivalent to the noise in a 1 Hz bandwidth). Careful and deliberate attention to detail when laying out the ADA4857 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. The noise model shown in Figure 47 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally referred to input (RTI), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise. VN, R2 R2 GAIN FROM = A TO OUTPUT 4kTR2 A VN, R1 4kTR1 VN, R3 R1 NOISE GAIN = R2 NG = 1 + R1 IN– VN VOUT R3 IN+ 4kTR3 VN2 + 4kTR3 + 4kTR1 RTI NOISE = R2 R1 + R2 + IN+2R32 + IN–2 R1 × R2 R1 + R2 2 2 + 4kTR2 R1 R1 + R2 RTO NOISE = NG × RTI NOISE Because the ADA4857 can operate up to 850 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4857 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on the SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads. The low distortion pinout of the ADA4857 increases the separation distance between the inputs and the supply pins, which improves the second harmonics. In addition, the feedback pin reduces the distance between the output and the inverting input of the amplifier, which helps minimize the parasitic inductance and capacitance of the feedback path, reducing ringing and peaking. POWER SUPPLY BYPASSING GAIN FROM = – R2 B TO OUTPUT R1 2 07040-073 B PCB LAYOUT Figure 47. Op Amp Noise Analysis Model All resistors have a Johnson noise that is calculated by (4kBTR) . where: k is Boltzmann’s Constant (1.38 × 10–23 J/K). B is the bandwidth in Hertz. T is the absolute temperature in Kelvin. R is the resistance in ohms. Power supply bypassing for the ADA4857 was optimized for frequency response and distortion performance. Figure 42 shows the recommended values and location of the bypass capacitors. The 0.1 μF bypassing capacitors should be placed as close as possible to the supply pins. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The capacitor between the two supplies helps improve PSR and distortion performance. The 10 μF electrolytic capacitors should be close to the 0.1 μF capacitors but it is not as critical. In some cases, additional paralleled capacitors can help improve frequency and transient response. GROUNDING A simple relationship that is easy to remember is that a 50 Ω resistor generates a Johnson noise of 1 nV/√Hz at 25°C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 9. Ground and power planes should be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input, output terminations, bypass capacitors, and RG should all be kept as close to the ADA4857 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, overshoot and to improve distortion performance. The ADA4857 LFSCP packages feature an exposed paddle. For optimum electrical and thermal performance, solder this paddle to ground. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-Circuit-Board Layout at www.analog.com. Rev. 0 | Page 17 of 20 ADA4857-1/ADA4857-2 OUTLINE DIMENSIONS 3.25 3.00 SQ 2.75 0.60 MAX 0.50 BSC 0.60 MAX 5 2.95 2.75 SQ 2.55 TOP VIEW PIN 1 INDICATOR 8 4 12° MAX 1 0.50 0.40 0.30 0.70 MAX 0.65 TYP 1.89 1.74 1.59 PIN 1 INDICATOR 0.05 MAX 0.01 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF 061507-B 0.90 MAX 0.85 NOM 1.60 1.45 1.30 EXPOSED PAD (BOTTOM VIEW) Figure 48. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 49. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) 4.00 BSC SQ PIN 1 INDICATOR 0.65 BSC TOP VIEW 12° MAX 3.75 BSC SQ 0.75 0.60 0.50 (BOTTOM VIEW) 13 12 9 8 16 PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 5 4 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.35 0.30 0.25 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters Rev. 0 | Page 18 of 20 021207-A 1.00 0.85 0.80 0.60 MAX 0.60 MAX ADA4857-1/ADA4857-2 ORDERING GUIDE Model ADA4857-1YCPZ-R2 1 ADA4857-1YCPZ-RL1 ADA4857-1YCPZ-R71 ADA4857-1YRZ1 ADA4857-1YRZ-R71 ADA4857-1YRZ-RL1 ADA4857-2YCPZ-R21 ADA4857-2YCPZ-RL1 ADA4857-2YCPZ-R71 1 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-lead SOIC_N 8-lead SOIC_N 8-lead SOIC_N 16-Lead LFSCP_VQ 16-Lead LFSCP_VQ 16-Lead LFSCP_VQ Z = RoHS Compliant Part. Rev. 0 | Page 19 of 20 Package Option CP-8-2 CP-8-2 CP-8-2 R-8 R-8 R-8 CP-16-4 CP-16-4 CP-16-4 Ordering Quantity 250 5,000 1,500 250 5,000 1,500 250 5,000 1,500 Branding H15 H15 H15 ADA4857-1/ADA4857-2 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07040-0-5/08(0) Rev. 0 | Page 20 of 20