ADC1206S040/055/070 Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Rev. 02 — 12 August 2008 Product data sheet 1. General description The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features n n n n n n n n n n n n n n n n 12-bit resolution Sampling rate up to 70 MHz −3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or twos complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible static digital inputs TTL and CMOS compatible digital outputs Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible Power dissipation 550 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample and hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included −40 °C to +85 °C ambient temperature 3. Applications High-speed analog-to-digital conversion for: n Cellular infrastructure n Professional telecommunication n Digital radio n Radar n Medical imaging n Fixed network n Cable modem ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz n Barcode scanner n Cable Modem Termination System (CMTS)/ Data Over Cable Service Interface Specification (DOCSIS) 4. Quick reference data Table 1. Quick reference data VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 3.6 V ICCA analog supply current - 78 87 mA ICCD digital supply current - 27 30 mA ICCO output supply current fclk = 20 MHz fi = 400 kHz - 3 4 mA INL integral non-linearity fclk = 20 MHz fi = 400 kHz - ±2.6 ±4.5 LSB DNL differential non-linearity fclk = 20 MHz fi = 400 kHz (no missing code guaranteed) - ±0.5 +1.1 − 0.95 LSB fclk(max) maximum clock frequency ADC1206S040H 40 - - MHz ADC1206S055H 55 - - MHz ADC1206S070H 70 - - MHz fclk = 55 MHz fi = 20 MHz - 550 660 mW Ptot total power dissipation 5. Ordering information Table 2. Ordering information Type number Package Sampling frequency (MHz) Name Description Version ADC1206S040H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 40 ADC1206S055H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 55 ADC1206S070H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 70 ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 2 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 6. Block diagram VCCA1 VCCA3 VCCA4 CLKN CLK VCCD1 VCCD2 OTC CE 2 3 41 36 37 15 18 19 35 6 to 10,13,14,16 n.c. FSREF Vref 12 Vref REFERENCE ADC1206S040/055/070 CLOCK DRIVER 11 21 D11 MSB 22 D10 23 D9 24 D8 AMP 25 D7 INN IN 43 42 sample and - hold LATCHES ANALOG - TO DIGITAL CONVERTER CMOS OUTPUTS 26 D6 data outputs 27 D5 28 D4 29 D3 SH 39 30 D2 31 D1 32 D0 33 CMADC 1 CMADC REFERENCE OVERFLOW/UNDERFLOW LATCH CMOS OUTPUT 20 LSB VCCO IR 5 DEC 44 AGND1 4 AGND3 40 AGND4 38 DGND1 17 DGND2 34 OGND 014aaa385 Fig 1. Block diagram. ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 3 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 7. Pinning information 34 OGND 35 CLKN 36 CLK 37 VCCD1 38 DGND1 39 SH 40 AGND4 41 VCCA4 42 IN CMADC 1 33 VCCO VCCA1 2 32 D0 VCCA3 3 31 D1 AGND3 4 30 D2 DEC 5 n.c. 6 n.c. 7 27 D5 n.c. 8 26 D6 n.c. 9 25 D7 n.c. 10 24 D8 Vref 11 23 D9 29 D3 D10 22 D11 21 28 D4 IR 20 CE 19 OTC 18 DGND2 17 n.c. 16 VCCD2 15 n.c. 14 n.c. 13 ADC1206S070H FSREF 12 Fig 2. 43 INN 44 AGND1 7.1 Pinning 014aaa383 Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description CMADC 1 regulator output common mode ADC input VCCA1 2 analog supply voltage 1 (5 V) VCCA3 3 analog supply voltage 3 (5 V) AGND3 4 analog ground 3 DEC 5 decoupling node n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected Vref 11 reference voltage input FSREF 12 full-scale reference output n.c. 13 not connected n.c. 14 not connected VCCD2 15 digital supply voltage 2 (5 V) n.c. 16 not connected ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 4 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 3. Pin description …continued Symbol Pin Description DGND2 17 digital ground 2 OTC 18 control input twos complement output; active HIGH CE 19 chip enable input (CMOS level; active LOW) IR 20 in-range output D11 21 data output; bit 11 (Most Significant Bit (MSB)) D10 22 data output; bit 10 D9 23 data output; bit 9 D8 24 data output; bit 8 D7 25 data output; bit 7 D6 26 data output; bit 6 D5 27 data output; bit 5 D4 28 data output; bit 4 D3 29 data output; bit 3 D2 30 data output; bit 2 D1 31 data output; bit 1 D0 32 data output; bit 0 (Least Significant Bit (LSB)) VCCO 33 output supply voltage (3.3 V) OGND 34 output ground CLKN 35 complementary clock input CLK 36 clock input VCCD1 37 digital supply voltage 1 (5 V) DGND1 38 digital ground 1 SH 39 sample-and-hold enable input (CMOS level; active HIGH) AGND4 40 analog ground 4 VCCA4 41 analog supply voltage 4 (5 V) IN 42 analog input voltage INN 43 complementary analog input voltage AGND1 44 analog ground 1 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit analog supply voltage [1] −0.3 +7.0 V VCCD digital supply voltage [1] −0.3 +7.0 V VCCO output supply voltage [1] −0.3 +7.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCD − VCCO −1.0 +4.0 V VCCA − VCCO −1.0 +4.0 V VCCA Parameter Conditions ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 5 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Vi(IN) input voltage on pin IN referenced to AGND 0.3 VCCA V Vi(INN) input voltage on pin INN 0.3 VCCA V Vi(clk)(p-p) peak-to-peak clock input voltage - VCCD V IO output current - 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C [1] differential clock drive at pins 35 and 36 The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. 9. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 75 K/W 10. Characteristics Table 6. Characteristics VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 3.6 V ICCA analog supply current I - 78 87 mA ICCD digital supply current I - 27 30 mA ICCO output supply current I - 3 4 mA fclk = 40 MHz; fi = 4.43 MHz C - 6.2 9 mA fclk = 55 MHz; fi = 20 MHz - 9.5 12 mA - 550 660 mW Ptot total power dissipation fclk = 20 MHz; fi = 400 kHz fclk = 55 MHz fi = 20 MHz I ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 6 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Inputs CLK and CLKN referenced to DGND[2] VIL VIH LOW-level input voltage HIGH-level input voltage PECL mode; VCCD = 5 V I 3.19 - 3.52 V TTL mode C 0 - 0.8 V PECL mode; VCCD = 5 V I 3.83 - 4.12 V TTL mode C 2.0 - VCCD V IIL LOW-level input current VCLK or VCLKN = 3.19 V C −10 - - µA IIH HIGH-level input current VCLK or VCLKN = 3.83 V C - - 10 µA Vi(dif)(p-p) peak-to-peak differential input voltage AC driving mode; DC voltage level = 2.5 V C 1 1.5 2.0 V Ri input resistance fclk = 55 MHz D 2 - - kΩ Ci input capacitance fclk = 55 MHz D - - 2 pF OTC, SH and CE (referenced to DGND); see Table 8 and 9 VIL LOW-level input voltage I 0 - 0.8 V VIH HIGH-level input voltage I 2.0 - VCCD V IIL LOW-level input current VIL = 0.8 V I −20 - - µA IIH HIGH-level input current VIH = 2.0 V I - - 20 µA IN and INN (referenced to AGND); see Table 7, Vref = VCCA3 − 1.75 V IIL LOW-level input current SH = HIGH C - 10 - µA IIH HIGH-level input current SH = HIGH C - 10 - µA Ri input resistance fi = 20 MHz D - 14 - MΩ Ci input capacitance fi = 20 MHz D - 450 - pF VI(cm) common-mode VI(IN) = VI(INN) input voltage output code 2047 C VCCA3 − 1.7 VCCA3 − 1.6 VCCA3 − 1.2 V Voltage controlled regulator output CMADC VO(cm) common-mode output voltage I - VCCA3 − 1.6 - V Iload load current I - 1 2 mA ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 7 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Voltage input Vref[3] Vref reference voltage Iref reference current Vi(dif)(p-p) peak-to-peak differential input voltage full-scale fixed voltage; fi = 20 MHz; fclk = 55 MHz VI(IN)(p-p) − VI(INN)(p-p); Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V C - VCCA3 − 1.75 - V C - 0.3 10 µA C - 1.9 - V - VCCA3 − 1.75 - V - 0.5 V Voltage controlled regulator output FSREF VO(ref) reference output voltage VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V I Digital outputs D11 to D0 and IR (referenced to OGND) VOL LOW-level output voltage IOL = 2 mA I 0 VOH HIGH-level output voltage IOH = − 0.4 mA I VCCCO − 0.5 - VCCO V Io output current 3-state output level between 0.5 V and VCCO I −20 - +20 µA C - - 7 MHz Switching characteristics; Clock frequency fclk; see Figure 3 fclk(min) minimum clock frequency SH = HIGH fclk(max) maximum clock ADC1206S040H frequency ADC1206S055H C 40 - - MHz I 55 - - MHz ADC1206S070H C 70 - - MHz tw(clk)H HIGH clock pulse width fi = 20 MHz C 6.8 - - ns tw(clk)L LOW clock pulse width fi = 20 MHz C 6.8 - - ns Analog signal processing; 50 % clock duty factor; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; see Table 7 Linearity INL integral non-linearity fclk = 20 MHz; fi = 400 kHz I - ±2.6 ±4.5 DNL differential non-linearity fclk = 20 MHz; fi = 400 kHz (no missing code guaranteed) I - ±0.5 +1.1 − 0.95 LSB Eoffset offset error VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C; output code = 2047 C −25 +5 +25 mV EG gain error spread from device to device; VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C C −7 - +7 %FS ADC1206S040_055_070_2 Product data sheet LSB © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 8 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit 220 245 - MHz [1] Bandwidth (fclk = 55 MHz)[4] B bandwidth −3 dB; full-scale input second harmonic level ADC1206S040H; (fclk = 40 MHz) C Harmonics α2H fi = 4.43 MHz C - −78 - dBFS fi = 10 MHz C - −77 - dBFS fi = 15 MHz C - −74 - dBFS fi = 20 MHz C - −71 - dBFS ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C - −77 - dBFS fi = 10 MHz C - −77 - dBFS fi = 15 MHz C - −76 - dBFS fi = 20 MHz I - −73 - dBFS ADC1206S070H; (fclk = 70 MHz) α3H third harmonic level fi = 4.43 MHz C - −76 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −70 - dBFS ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz C - −74 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −74 - dBFS fi = 20 MHz C - −73 - dBFS ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C - −74 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −74 - dBFS fi = 20 MHz I - −72 - dBFS ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C - −74 - dBFS fi = 10 MHz C - −74 - dBFS fi = 15 MHz C - −73 - dBFS ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 9 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Total harmonic distortion[5] THD total harmonic distortion ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz C - −68 - dBFS fi = 10 MHz C - −68 - dBFS fi = 15 MHz C - −68 - dBFS fi = 20 MHz C - −68 - dBFS ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C - −68 - dBFS fi = 10 MHz C - −68 - dBFS fi = 15 MHz C - −68 - dBFS fi = 20 MHz I - −68 - dBFS ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C - −68 - dBFS fi = 10 MHz C - −67 - dBFS fi = 15 MHz C - −67 - dBFS shorted input; SH = HIGH; fclk = 55 MHz C - 0.45 - LSB Thermal noise (fclk = 55 MHz) Nth(RMS) RMS thermal noise Signal-to-noise ratio[6] S/N signal-to-noise ratio ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz C - 64 - dBFS fi = 10 MHz C - 64 - dBFS fi = 15 MHz C - 64 - dBFS fi = 20 MHz C - 64 - dBFS ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C - 64 - dBFS fi = 10 MHz C - 64 - dBFS fi = 15 MHz C - 64 - dBFS fi = 20 MHz I - 64 - dBFS ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C - 64 - dBFS fi = 10 MHz C - 64 - dBFS fi = 15 MHz C - 63 - dBFS ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 10 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Spurious free dynamic range; see Figure 7, 13 and 14 SFDR spurious free dynamic range ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz C - 72 - dBFS fi = 10 MHz C - 71 - dBFS fi = 15 MHz C - 71 - dBFS fi = 20 MHz C - 69 - dBFS ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C - 72 - dBFS fi = 10 MHz C - 71 - dBFS fi = 15 MHz C - 71 - dBFS fi = 20 MHz I - 69 - dBFS ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C - 70 - dBFS fi = 10 MHz C - 69 - dBFS fi = 15 MHz C - 69 - dBFS Effective number of bits[7] ENOB effective number of bits ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz C - 10.1 - bits fi = 10 MHz C - 10.1 - bits fi = 15 MHz C - 10.1 - bits fi = 20 MHz C - 10 - bits ADC1206S055H; (fclk = 55 MHz) fi = 4.43 MHz C - 10.1 - bits fi = 10 MHz C - 10.1 - bits fi = 15 MHz C - 10 - bits fi = 20 MHz I - 10 - bits ADC1206S070H; (fclk = 70 MHz) fi = 4.43 MHz C - 10 - bits fi = 10 MHz C - 10 - bits C - 10 - bits fi = 15 MHz Two-tone Intermodulation; (fclk = 55 MHz; fi = 20 MHz)[8] αIM intermodulation suppression C - −68 - dB IMD3 third-order intermodulation distortion C - −70 - dB ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 11 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to 85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min Typ Max Unit [1] Bit error rate (fclk = 55 MHz) BER bit error rate fi = 20 MHz; VI = ±16 LSB at C code 2047 - 10−14 - times/sample Timing (CL = 10 pF)[9] td(s) sampling delay time C - 0.25 1 ns th(o) output hold time C 4 6.4 - ns td(o) output delay time C - 9.0 13 ns 3-state output delay times; see Figure 4 tdZH float to active HIGH delay time C - 5.1 9.0 ns tdZL float to active LOW delay time C - 7.0 11 ns tdHZ active HIGH to float delay time C - 9.7 14 ns tdLZ active LOW to float delay time C - 9.5 13 ns [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p - p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case the CLKN pin has to be connected to the ground. [3] The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA; see Figure 12. [4] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. [5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics: 2 2 2 2 2 ( α 2H ) + ( α 3H ) + ( α 4H ) + ( α 5H ) + ( α 6H ) THD = 20 log -----------------------------------------------------------------------------------------------------------------------------------------------2 ( α 1H ) where α1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. [6] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8. ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 12 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz [7] Effective number of bits are obtained via a fast Fourier transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to Single-to-noise-and-distortion-ratio (SINAD) is given by SINAD = ENOB × 6.02 + 1.76 dB; see Figure 5. [8] Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full-scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. [9] Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3. 11. Additional information relating to Table 6 Table 7. Output coding with differential inputs (typical values to AGND); VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V, Vref = VCCA3 − 1.75 V Code VI(IN)(p-p) VI(INN)(p-p) IR (V) Binary outputs D11 to D0 Twos complement outputs D11 to D0 Underflow < 3.125 0000 0000 0000 10 0000 0000 00 0 3.125 4.075 1 0000 0000 0000 10 0000 0000 00 1 - - 1 0000 0000 0001 10 0000 0000 01 ↓ - - ↓ ↓ ↓ 2047 3.6 3.6 ↓ 01 1111 1111 11 11 1111 1111 11 ↓ - - ↓ ↓ ↓ 4094 - - 1 1111 1111 1110 0111 1111 1110 4095 4.075 3.125 1 1111 1111 1111 0111 1111 1111 Overflow > 4.075 < 3.125 0 1111 1111 1111 0111 1111 1111 Table 8. < 4.075 0 Mode selection OTC CE D0 to D11 and IR 0 0 binary; active 1 0 two’s complement; active X[1] 1 high-impedance [1] X = don’t care. Table 9. Sample-and-hold selection SH Sample-and-hold 1 active 0 inactive; tracking mode ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 13 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz sample N sample N + 1 sample N + 2 tw(clk)L tw(clk)H HIGH CLK 50 % LOW sample N sample N + 1 sample N + 2 IN th(o) td(s) HIGH DATA D0 TO D11 DATA N−2 DATA N−1 DATA N DATA N+1 50 % LOW td(o) Fig 3. Timing diagram ADC1206S040_055_070_2 Product data sheet 014aaa396 © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 14 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz VCCD 50 % CE 0V tdHZ tdZH HIGH 90 % output data 50 % LOW tdZL tdLZ HIGH output data 50 % LOW 10 % VCCO ADC1206S 070 TEST S1 tdLZ VCCO tdZL VCCO tdHZ OGND tdZH OGND 3.3 kΩ S1 15 pF CE 014aaa397 frequency on pin CE = 100 kHz Fig 4. Timing diagram and test conditions of 3-state output delay time ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 15 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 014aaa371 10.6 014aaa372 −56 THD (dBFS) ENOB (bits) (1) 10.2 −60 (2) (3) 9.8 −64 9.4 −68 (3) (2) (1) −72 9 1 10 1 100 10 (1) 40 MHz (1) 40 MHz (2) 55 MHz (2) 55 MHz (3) 70 MHz (3) 70 MHz Fig 5. Effective Number Of Bits (ENOB) as a function of input frequency (sample device). 014aaa373 76 100 fi (MHz) fi (MHz) SFDR (dBFS) Fig 6. Total Harmonic Distortion (THD) as a function of input frequency (sample device). 014aaa374 66 SNR (dBFS) 72 65 (1) (2) (3) 68 64 64 63 (3) (1) (2) 60 62 1 10 100 1 fi (MHz) 100 fi (MHz) (1) 40 MHz (1) 40 MHz (2) 55 MHz (2) 55 MHz (3) 70 MHz (3) 70 MHz Fig 7. Spurious Free Dynamic Range (SFDR) as a function of input frequency (sample device). Fig 8. Signal-to-Noise ratio (S/N) as a function of input frequency (sample device). ADC1206S040_055_070_2 Product data sheet 10 © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 16 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 014aaa375 0 power spectrum (dB) −40 −80 −120 −160 0 Fig 9. 5 10 15 20 25 30 measured output range (MHz) Single-tone; fi = 20 MHz; fclk = 55 MHz. 014aaa376 0 power spectrum (dB) −40 −80 −120 −160 0 5 10 15 20 25 30 measured output range (MHz) Fig 10. Two-tone; fi 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz. ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 17 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 014aaa377 2 output range (INL) 1 0 −1 −2 0 1024 2048 3072 4096 output code Fig 11. Integral Non-Linearity (INL) 014aaa378 0.6 DNL (LSB) 0.2 −0.2 −0.6 0 1024 2048 3072 4096 output code Fig 12. Differential Non-Linearity (DNL) ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 18 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 014aaa379 80 SFDR (dBFS) 60 (1) 40 (3) (2) 20 −60 −40 −20 0 Input amplitude (dBFS) (1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB Fig 13. SFDR as a function of input amplitude; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; fclk = 40 MHz 014aaa380 80 SFDR (dBFS) 60 (2) 40 (3) 20 −60 (1) −40 −20 0 Input amplitude (dBFS) (1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB Fig 14. SFDR as a function of input amplitude; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; fclk = 55 MHz ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 19 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 11 72 014aaa382 2.6 (dB) bits (3) (2) 68 10 (Vi − Vi)(p - p) (V) 2.2 1.8 9 64 (1) 1.4 60 1.3 1.5 1.7 1.9 8 2.1 2.3 Vref (V) 1 1.3 014aaa381 1.5 1.7 1.9 2.1 2.3 VCCA − Vref (V) (1) S/N (2) ENOB (3) SFDR Fig 15. ENOB, SFDR and S/R as a function of Vref; fclk = 55 MHz; fi = 4.43 MHz Fig 16. ADC full-scale; VI(IN)(p-p) − VI(INN)(p-p) as a function of VCCA − Vref ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 20 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 12. Application information 5V 100 nF 220 nF SH mode 5V 100 nF IN 1:1 100 Ω 100 Ω CLK INN 5V 10 nf 5V 100 nF 100 nF 44 43 42 41 40 39 38 37 36 35 34 33 100 nF 1 2 32 D0 (LSB) 3 31 D1 4 30 D2 29 D3 28 D4 5 n.c. 6 n.c. 7 27 D5 n.c. 6 26 D6 n.c. 9 25 D7 n.c. 10 24 D8 11 23 12 13 14 15 16 17 18 19 20 21 22 D9 Vref ADC1206S070 n.c. 5V n.c. IR n.c. 100 nF D10 D11 (MSB) chip select input output format select 014aaa386 The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram TTL input D CLKN ADC1206S 070 PECL MC 100 ELT20 270 Ω CLK CLKN 270 Ω TTL input 014aaa387 Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator CLK 014aaa388 Fig 19. Application diagram for TTL single-ended clock ADC1206S040_055_070_2 Product data sheet ADC1206S 070 © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 21 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 D5 B11 D4 12.1 Demonstration board VCC J2 C6 330 nF CLK2 R4 50 Ω 33 AGND4 C17 10 nF VCCA4 IN C9 TR1 CMADC J1 220 nF INN IN AGND1 R9 100 Ω D9 D8 D7 D3 D6 17 ADC1206S070 40 16 41 15 42 14 43 13 44 12 1 MCLT1_6T_KK81 C8 D2 39 2 CMADC R1 100 Ω 18 IC2 3 4 5 6 7 8 9 10 D10 D11 IR S4 CE OTC DGND2 S3 VCC n.c. FL2 VCCD2 n.c. C12 100 nF n.c. C5 330 nF C18 10 nF FSREF FL1 11 Vref S5 19 38 n.c. SH 37 n.c. VCCA DGND1 20 n.c. VCCD 10 nF 36 n.c. VCCD1 21 n.c. C19 35 DEC CLK1 CLK 22 AGDN3 CLK1 34 VCCA3 CLKN B5 31 30 29 28 27 26 25 24 23 VCCA1 OGND C13 100 nF R3 100 Ω 32 D1 VCCO D0 VCCO C15 10 nF FL3 J3 B8 S2 S1 330 nF C10 100 nF C16 10 nF VCCA C11 100 nF B7 VCC FL4 P1 5 kΩ C14 100 nF P2 VCCA C7 330 nF 1 kΩ R7 1.2 kΩ VCCA R6 2.4 KΩ 12 V GND J4 1 J4 2 1 IN C1 22 µF (20 V) VCC VCC ICI BYD17G D3 TM3 OUT 3 MC78MO5CDT GND C2 4.7 µF (16 V) R2 62 Ω PMBT 2222A VCCO T1 R8 750 Ω D1 LGT679 C3 1 µF D2 BZV55C3V6 R5 4.7 kΩ C4 1 µF TP2 VCCO 014aaa370 C8 = close to TR1 pin. Fig 20. Demonstration board schematic. ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 22 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz TM2 R1 J1 J3 C9 B4 1 1 S5 TR1 S1 R3 34 P1 1 R9 C7 FL4 IC1 R8 R2 T1 R5 1 C12 D1 C3 D2 2 1 R6 B5 P2 C4 J4 23 112 TP2 C2 D3 IC2 C14 B7 C11 TM3 C1 C10 S2 R7 S3 S4 FL2 J2 C5 B8 R4 B11 TM1 1 014aaa391 Fig 21. Component placement (top side). C6 FL3 C19 C15 C8 C13 C16 FL1 C17 C18 014aaa392 Fig 22. Component placement (underside). ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 23 of 32 NXP Semiconductors ADC1206S040/055/070 Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 014aaa393 Fig 23. PCB layout (top layer). 014aaa394 Fig 24. PCB layout (ground layer). ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 24 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 014aaa395 Fig 25. PCB layout (power plane). 12.2 Alternative parts The following alternative parts are also available: Table 10. Alternative parts Type number ADC1006S055 ADC1006S070 [1] Description Sampling frequency Single 10 bits ADC [1] 55 MHz Single 10 bits ADC [1] 70 MHz Pin to pin compatible 12.3 Recommended companion chip The recommended companion chip is the TDA9901 wide band differential digital controlled variable gain amplifier. 13. Support information 13.1 Non-linearities 13.1.1 Integral Non-Linearity (INL). It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V in ( i ) – V in ( ideal ) INL ( i ) = ----------------------------------------------S where n i = 0 ⋅ ( 2 – 1 ) and ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 25 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz S = slope of the ideal straight line = code width; i = code value. 13.1.2 Differential Non-Linearity (DNL). V in ( i + 1 ) – V in ( i ) It is the deviation in code width from the value of 1 LSB. DNL ( i ) = --------------------------------------------–1 S n where i = 0 ⋅ ( 2 – 2 ) 13.2 Dynamic parameters (single tone) Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft/fs = M/N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. magnitude a1 SFDR s a2 a3 ak measured output range fs/2 014aaa389 Fig 26. Spectrum of full-scale input sine wave with frequency ft. Remark: in the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and “quantization noise”. 13.2.1 Signal-to-noise and distortion (SINAD) The ratio of the output signal power to the noise-plus-distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ db ] = 10 log -----------------------------------------P noise + distortion 13.2.2 Effective Number Of Bits (ENOB) It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: ENOB = ( SINAD [ dB ] – ( 1 ⋅ 76 ) ) ⁄ ( 6 ⋅ 02 ) ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 26 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 13.2.3 Total Harmonic Distortion (THD) The ratio of the power of the harmonics to the power of the fundamental. For k-1 P harmonics harmonics the THD is: THD [ dB ] = 10 log --------------------------P signal 2 2 where P harmonics = α 2 + α 3 + α P signal = α 2 k 2 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). 13.2.4 Signal-to-Noise ratio (S/N) The ratio of the output signal power to the noise power, excluding the harmonics and the P signal DC component. S/N [ dB ] = 10 log ----------------P noise 13.2.5 Spurious Free Dynamic Range (SFDR) The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and α1 non-harmonic, excluding DC component). SFDR [ dB ] = 20 log ----------------max ( s ) 13.3 Intermodulation distortion 13.3.1 Spectral analysis (dual-tone) 014aaa384 0 (dB) IMD3 −40 −80 −120 −160 0 5 10 15 20 25 30 measured output range (HHz) Fig 27. Spectral analysis (dual-tone) From a dual-tone input sinusoid (ft 1 and ft 2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined, as follows. ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 27 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 13.3.2 IMD2 (IMD3) The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total intermodulation distortion IMD is given by P intermod IMD [ dB ] = 10 log ----------------------P signal where, P intermod = α +α 2 (f im t1 2 (f im t1 – f t2 ) – α + 2 f t2 ) + α 2 ( 2 f t1 im 2 (f im t1 + f t2 ) + α – f t2 ) + α 2 ( 2 f t1 im 2 (f im t1 – 2 f t2 ) + f t2 ) P signal = α 2 ( f t1 ) + α 2 ( f t2 ) and α 2 (f ) im t is the power in the intermodulation component at frequency ft. 13.4 Noise Power Ratio (NPR) When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set. ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 28 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 14. Package outline QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.1 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 97-08-01 03-02-25 SOT307-2 Fig 28. SOT307-2 (QFP44) ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 29 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1206S040_055_070_2 20080812 Product data sheet - Modifications: ADC1206S040_055_070_1 • • • Corrections made to DNL value in Table 1. Corrections made to several entries in Table 6. Corrections made to note in Figure 4. 20080612 Product data sheet ADC1206S040_055_070_2 Product data sheet ADC1206S040_055_070_1 - - © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 30 of 32 ADC1206S040/055/070 NXP Semiconductors Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] ADC1206S040_055_070_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 12 August 2008 31 of 32 NXP Semiconductors ADC1206S040/055/070 Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 12.2 12.3 13 13.1 13.1.1 13.1.2 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.3 13.3.1 13.3.2 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 13 Application information. . . . . . . . . . . . . . . . . . 21 Demonstration board . . . . . . . . . . . . . . . . . . . 22 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 25 Recommended companion chip . . . . . . . . . . . 25 Support information . . . . . . . . . . . . . . . . . . . . 25 Non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 25 Integral Non-Linearity (INL). . . . . . . . . . . . . . . 25 Differential Non-Linearity (DNL).. . . . . . . . . . . 26 Dynamic parameters (single tone) . . . . . . . . . 26 Signal-to-noise and distortion (SINAD). . . . . . 26 Effective Number Of Bits (ENOB) . . . . . . . . . . 26 Total Harmonic Distortion (THD). . . . . . . . . . . 27 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 27 Spurious Free Dynamic Range (SFDR) . . . . . 27 Intermodulation distortion . . . . . . . . . . . . . . . . 27 Spectral analysis (dual-tone) . . . . . . . . . . . . . 27 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . . 28 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 August 2008 Document identifier: ADC1206S040_055_070_2