INTEGRATED CIRCUITS DATA SHEET TDA8793 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) Preliminary specification Supersedes data of 1998 May 14 File under Integrated Circuits, IC02 1999 Oct 06 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 FEATURES GENERAL DESCRIPTION • 8-bit low-power ADC (170 mW typical) The TDA8793 is an 8-bit low-power Analog-to-Digital Converter (ADC) which includes a track-and-hold circuit and internal references. The device converts an analog input signal, up to 100 MHz, into 8-bit binary codes at a maximum sample rate of 100 Msps. All digital inputs and output are TTL/CMOS compatible. A sine wave clock input signal can also by used. • 2.7 to 3.6 V operation • Sampling rate up to 100 Msps • Track-and-hold circuit • CMOS/TTL compatible digital inputs and outputs • Internal references The Power-down mode enables the device power consumption to be reduced to 5 mW. • Adjustable full scale range possibility with external reference • Power-down mode; 5 mW. APPLICATIONS • Radio communications • Digital data storage read channels • Medical imaging • Digital instrumentation. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 2.7 3.0 3.6 V VCCD digital supply voltage 2.7 3.0 3.6 V VCCO output stages supply voltage ICCA analog supply current ICCD digital supply current 2.7 3.0 3.6 V operating 32 40 48 mA standby 0 5 100 µA operating 13 16 22 mA standby 0 0.65 1.1 mA − 0.1 − mA ICCO output stages supply current INL integral non-linearity ramp input; fCLK = 2 MHz; VCCA = VCCD = 3 V − ±0.8 tbf LSB DNL differential non-linearity ramp input; fCLK = 2 MHz; VCCA = VCCD = 3 V − ±0.25 tbf LSB fCLK(max) maximum clock input frequency 100 − − MHz Ptot total power dissipation − 170 − mW VCC = 3 V ORDERING INFORMATION TYPE NUMBER TDA8793HL 1999 Oct 06 PACKAGE NAME LQFP32 DESCRIPTION plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm 2 VERSION SOT401-1 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 BLOCK DIAGRAM VCCA TEN handbook, full pagewidth 12 VCCD VCCO2 VCCO1 10 22 20 7 26 25 24 INP INN REFOUT REFIN 4 3 23 TRACK-ANDHOLD CMOS OUTPUTS LATCHES ADC STDBY 15 2 32 11 D5 D4 D3 D2 D1 D0 CLK VREFOUT = 1.85 V REFERENCE VSDN = 1.25 V TDA8793 8 31 DEC 6 9 AGND DGND Fig.1 Block diagram. 1999 Oct 06 17 16 5 CLOCK DRIVER SDN 18 D7 D6 3 19 21 OGND1 ODGND2 MGR016 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN D2 17 DESCRIPTION data output bit 2 n.c. 1 not connected D3 18 data output bit 3 REFIN 2 reference input for ADC OGND1 19 output ground 1 INN 3 negative input VCCO1 20 output supply voltage 1 INP 4 positive input OGND2 21 output ground 2 REFOUT 5 reference for AC coupling VCCO2 22 output supply voltage 2 AGND 6 analog ground D4 23 data output bit 4 VCCA 7 analog supply voltage D5 24 data output bit 5 STDBY 8 standby mode input D6 25 data output bit 6 DGND 9 digital ground D7 26 data output bit 7 (MSB) not connected track enable input (active LOW) n.c 29 not connected n.c. 13 not connected n.c 30 not connected n.c. 14 not connected DEC 31 decoupling D0 15 data output bit 0 (LSB) SDN 32 stabilized decoupling node D1 16 data output bit 1 handbook, full pagewidth 25 D6 28 12 26 D7 n.c TEN 27 n.c. not connected 28 n.c. 27 29 n.c. n.c clock input 30 n.c. digital supply voltage 11 31 DEC 10 32 SDN VCCD CLK n.c. 1 24 D5 REFIN 2 23 D4 INN 3 22 VCCO2 INP 4 21 OGND2 TDA8793 18 D2 STDBY 8 17 D3 DGND Fig.2 Pin configuration. 1999 Oct 06 4 D1 16 7 D0 15 VCCA n.c. 14 19 OGND1 n.c. 13 6 TEN 12 AGND CLK 11 20 VCCO1 VCCD 10 5 9 REFOUT MGR017 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VCCO output stages supply voltage −0.3 +7.0 V ∆VCC supply voltage differences between VCCA and VCCD −1.0 +1.0 V VCCO and VCCD −1.0 +1.0 V −1.0 +1.0 V −0.3 +7.0 V VCCA and VCCO VINP, INN input voltage range IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature 0 70 °C Tj junction temperature − − °C referenced to AGND HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Oct 06 PARAMETER CONDITIONS thermal resistance from junction to ambient 5 in free air VALUE UNIT 94 K/W Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 CHARACTERISTICS VCCA = V7 to V6 = 2.7 to 3.6 V; VCCD = V10 to V9 = 2.7 to 3.6 V; VCCO = V20 (or V22) to V19 (or V21) = 2.7 to 3.6 V; AGND to DGND and OGND shorted together; VCCA to VCCD = −0.15 to +0.15 V; VCCD to VCCO = −0.15 to +0.15 V; VCCA to VCCO = −0.15 to +0.15 V; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = VCCO = 3.0 V and Tamb = 25 °C; single-ended input; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 2.7 3.0 3.6 V VCCD digital supply voltage 2.7 3.0 3.6 V VCCO output stages supply voltage 2.7 3.0 3.6 V ICCA analog supply current 32 40 48 mA ICCD digital supply current 13 16 22 mA ICCO output stages supply current fi = ramp input − 0.1 tbf mA fi = 20 MHz − 4 tbf mA 1.21 1.25 1.29 V Internal reference (pin SDN); note 1 Vref reference voltage Vreg line regulation voltage − 0.4 3 mV TC temperature coefficient − 18 − ppm/K IL load current −1 − − mA 1.76 1.82 1.88 V − 1.5 4 mV 2.7 < VCCA < 3.6 V Internal reference (pin REFOUT) Vo(ref) reference voltage Vo(reg) line regulation voltage 2.7 < VCCA < 3.6 V TC temperature coefficient − 18 − ppm/K IL load current −1 − − mA − −0.87 − mA Adjustable full scale input (pin REFIN); see Figs 3, 4, and 7 Iref input current VREFIN = 1.25 V Clock input (pin CLK); note 2 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VCLK = 0 −2 − +2 µA IIH HIGH-level input current VCLK = VCCD − − 5 µA tr clock rise time 0.75 − tbf ns tf clock fall time 0.75 − tbf ns Zi input impedance fCLK = 100 MHz − 32 − kΩ Ci input capacitance fCLK = 100 MHz − 2 − pF Standby input (pin STDBY); see Table 1 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VSTDBY = 0 −5 − − µA IIH HIGH-level input current VSTDBY = VCCD − − 5 µA 1999 Oct 06 6 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8793 CONDITIONS MIN. TYP. MAX. UNIT Track enable input (pin TEN); see Table 2 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VTEN = 0 −5 − − µA IIH HIGH-level input current VTEN = VCCD − − 5 µA Inputs (pins INP and INN); analog input voltage referenced to AGND; VREFIN = 1.27 V; see Table 3 Vi(p-p) input voltage range (peak-to-peak value) Vi = VINP − VINN; Tamb = 25 °C 0.90 0.97 1.040 V ∆TCI input voltage range drift − 0.5 − mV/K Vi(os) input offset voltage output code = 127 −25 − +25 mV Zi input impedance fINP = 50 MHz − 90 − kΩ Ci input capacitance fINP = 50 MHz − 2 − pF IIL LOW-level input current VINP = VREFOUT + 0.5 −1 − − µA VINP = VREFOUT − 0.5 −1 − − µA VINP = VREFOUT + 0.5 − − 40 µA VINP = VREFOUT − 0.5 − − 40 µA − 1 − V IIH HIGH-level input current Adjustable full scale range; VREFIN = 1.2 to 1.35 V; see Fig.3 VI(p-p) input voltage range (peak-to-peak value) Vi = VINP − VINN; Tamb = 25 °C Voltage controlled regulator input pin VREFIN (referenced to AGND); note 3 Vi(ref) reference voltage tbf 1.25 tbf V Ii(ref) input current on pin VREFIN − tbf 1.1 mA − 0.5 V Outputs; ADC data outputs VOL LOW-level output voltage IO = 1 mA − IO = −0.4 mA VCCO − 0.5 − VCCO V − − 10 pF 10% to 90%; CL = 10 pF − 1.2 − V/ns track = LOW − − 6 MHz VOH HIGH-level output voltage CL output load capacitance δv/δt slew rate Switching characteristics; note 2; see Table 1 fCLK(min) minimum clock frequency fCLK(max) maximum clock frequency 100 − − MHz tW(CLKH) clock pulse width HIGH 4 − − ns tW(CLKL) clock pulse width LOW 4 − − ns 1999 Oct 06 7 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8793 CONDITIONS MIN. TYP. MAX. UNIT Analog signal processing; note 3; see Figs 4, 5, 6 and 7 INL integral non-linearity ramp input; fCLK = 2 MHz; VCCA = VCCD = 3 V − ±0.8 tbf LSB DNL differential non-linearity ramp input; fCLK = 2 MHz; VCCA = VCCD = 3 V − ±0.25 tbf LSB S/N signal-to-noise ratio (full scale) without harmonics; fCLK = 100 MHz fi = 20 MHz 42 45 − dB fi = 50 MHz − 45 − dB − 350 − MHz fi = 20 MHz − −56 − dB fi = 50 MHz − −52 − dB fi = 20 MHz − − 0 dB fi = 50 MHz − − 0 dB fi = 20 MHz − 66 − dB fi = 50 MHz − 57 − dB fi = 20 MHz − 66 − dB fi = 50 MHz − 55 − dB fi = 20 MHz − 64 − dB fi = 50 MHz − 61 − dB fi = 20 MHz − 64 − dB fi = 50 MHz − 59 − dB BW(−3dB) −3 dB analog bandwidth THD total harmonics distortion Hfund(FS) HD2(FS) full scale fundamental harmonics second harmonic distortion (full scale) all components included fCLK = 100 MHz differential inputs; fCLK = 100 MHz single-ended input; fCLK = 100 MHz HD3(FS) third harmonic distortion (full scale) all components included differential inputs; fCLK = 100 MHz single-ended input; fCLK = 100 MHz SFDR EB spurious free dynamic range effective bits fCLK = 100 MHz dB fi = 20 MHz − 57 − dB fi = 50 MHz − 54 − dB fCLK = 100 MHz; note 4 bits fi = 20 MHz 7.0 7.4 − bits fi = 50 MHz − 7.2 − bits − − 1.5 ns Data timing; fCLK = 100 MHz; CL = 10 pF; see Fig.8 tds sampling delay th output hold time 3 − − ns td output delay time − 5 8 ns 1999 Oct 06 8 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 Notes 1. It is possible to use the reference output voltage (pin SDN) to drive other analog circuits under the limits indicated. 2. In addition to a good layout of the digital and analog grounds, it is recommended that the rise and fall times of the clock must be not less than 0.75 ns. 3. It is possible with an external reference voltage connected to REFIN pin to adjust the ADC input range. The input range variation will be fixed. 4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 k acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). Conversion to signal-to-noise ratio: SINAD = 6.02 × EB + 1.76 dB. Table 1 Table 2 Table 3 Standby selection PIN STDBY D0 TO D7 ICCA + ICCD LOW inactive 56 mA HIGH active; output logic state LOW 0.7 mA Track-and-hold selection PIN TEN TRACK-AND-HOLD LOW active HIGH inactive; tracking mode Output coding and input voltage (typical values; referenced to AGND); VREFIN = 1.27 V BINARY OUTPUT BITS STEP VINP (V) VINN (V) Underflow <1.6 0 1.6 D7 D6 D5 D4 D3 D2 D1 D0 >2.1 0 0 0 0 0 0 0 0 2.1 0 0 0 0 0 0 0 0 1 ... ... 0 0 0 0 0 0 0 1 ... ... ... ... ... ... ... ... ... ... ... 127 1.85 1.85 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 254 ... ... 1 1 1 1 1 1 1 0 255 2.1 1.6 1 1 1 1 1 1 1 1 Overflow >2.1 <1.6 1 1 1 1 1 1 1 1 1999 Oct 06 9 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 FCE421 1.4 FCE423 67 handbook, halfpage handbook, halfpage SFDR S/N (dB) Vi(p-p) (V) (1) 62 1.2 57 1 52 (2) 0.8 47 0.6 1.15 1.35 1.25 42 1.15 1.45 VREFIN (V) 1.35 1.25 1.45 VREFIN (V) Typical values measured at VCCA = VCCD = VCCO = 3.0 V, fCLK = 100 MHz, Tamb = 25 °C and single-ended input. (1) SFDR (2) S/N Typical values measured at VCCA = VCCD = VCCO = 3.0 V, fCLK = 100 MHz, Tamb = 25 °C and single-ended input. Fig.3 Fig.4 ADC input voltage as a function of VREFIN reference input voltage. FCE419 55 FCE420 8 handbook, halfpage THD S/N (dB) Noise and spurious free dynamic range as a function of VREFIN reference input voltage. handbook, halfpage EB (bits) (1) 53 (1) 7.5 (2) (2) 51 7 49 6.5 (3) 47 6 45 1 10 fi (MHz) 5.5 102 1 (1) THD for differential inputs (2) THD for single-ended input (3) S/N Typical values measured at VCCA = VCCD = VCCO = 3.0 V, fCLK = 100 MHz and Tamb = 25 °C. Fig.5 fi (MHz) 102 (1) Differential inputs (2) Single-ended input Typical values measured at VCCA = VCCD = VCCO = 3.0 V, fCLK = 100 MHz and Tamb = 25 °C. Noise and distortion as a function of input frequency. 1999 Oct 06 10 Fig.6 Effective bits as a function of input frequency. 10 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 FCE422 8 handbook, halfpage EB (bits) 7 6 5 1.15 1.25 1.35 VREFIN (V) 1.45 Typical values measured at VCCA = VCCD = VCCO = 3.0 V, fCLK = 100 MHz, Tamb = 25 °C and single-ended input. Fig.7 Effective bits as a function of VREFIN reference input voltage. tCPL handbook, full pagewidth tCPH HIGH 50 % CLK LOW sample N sample N + 1 sample N + 2 Vl th tds HIGH DATA D0 to D7 DATA N−2 DATA N−1 DATA N DATA N+1 50 % LOW td MGR018 Fig.8 Timing diagram. 1999 Oct 06 11 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 APPLICATION INFORMATION handbook, full pagewidth 100 nF SND 100 nF REFIN 10 nF INN 220 nF INP input 50 Ω 32 DEC 31 2 3 4 TDA8793 50 Ω REFOUT 5 100 nF MGR019 Fig.9 Application diagram for single-ended input mode with internal reference. handbook, full pagewidth EXTERNAL REFERENCE 1.25 V 100 nF DEC 100 nF 10 nF 220 nF REFIN INN INP input 50 Ω 31 2 3 4 TDA8793 50 Ω REFOUT 5 100 nF MGR020 Fig.10 Application diagram for single-ended input mode with external reference. 1999 Oct 06 12 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 handbook, full pagewidth 100 nF SND 100 nF REFIN 220 nF input 2 INN 50 Ω DEC 32 31 2 3 TDA8793 220 nF input 1 50 Ω INP REFOUT 4 5 100 nF MGR021 Fig.11 Application diagram for differential input mode with internal reference. handbook, full pagewidth 100 nF SND 100 nF 220 nF input REFIN INN 1:1 32 DEC 31 2 3 100 nF 100 Ω 100 Ω INP REFOUT TDA8793 4 5 100 nF MGR022 Fig.12 Application diagram for differential input mode using a transformer. 1999 Oct 06 13 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 PACKAGE OUTLINE SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index θ bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT401-1 1999 Oct 06 EUROPEAN PROJECTION 14 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Oct 06 15 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Oct 06 16 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 NOTES 1999 Oct 06 17 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 NOTES 1999 Oct 06 18 Philips Semiconductors Preliminary specification 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter (ADC) TDA8793 NOTES 1999 Oct 06 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/02/pp20 Date of release: 1999 Oct 06 Document order number: 9397 750 06028