ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter General Description Features The ADC121S625 is a 12-bit, 50 ksps to 200 ksps sampling Analog-to-Digital (A/D) converter that features a fully differential, high impedance analog input and an external reference. While best performance is achieved with reference voltage between 500mV and 2.5V, the reference voltage can be varied from 100mV to 2.5V, with a corresponding resolution between 49µV and 1.22mV. n n n n n The output serial data is binary 2’s complement, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and with many common DSP serial interfaces. The differential input, low power, automatic power down, and small size make the ADC121S625 ideal for direct connection to transducers in battery operated systems or remote data acquisition applications. Operating from a single +5V supply, the normal power consumption is reduced to a few nanowatts in the power-down mode. The ADC121S625 is a pin-compatible superior replacement for the ADS7817 and is available in the MSOP-8 package. Operation is guaranteed over the industrial temperature range of −40˚C to +85˚C and clock rates of 800 kHz to 3.2 MHz. Key Specifications n n n n n n n True Differential Inputs Guaranteed performance from 50ksps to 200ksps External Reference High AC Common-Mode Rejection SPI™/QSPI™/MICROWIRE™/DSP compatible Serial Interface Conversion Rate Offset Error Gain Error INL DNL CMRR Power Consumption — Active, 200ksps — Active, 50ksps — Power Down 50 to 200 ksps 0.4 LSB (typ) 0.05 LSB (typ) ± 1 LSB (max) ± 0.75 LSB (max) 82 dB (typ) 2.25 mW (typ) 1.33 mW (typ) 60 nW (typ) Applications n n n n n n Automotive Navigation Portable Systems Medical Instruments Instrumentation and Control Systems Motor Control Direct Sensor Interface Connection Diagram 20132705 Ordering Information Temperature Range Description Top Mark ADC121S625CIMM Order Code −40˚C to +85˚C 8-Lead MSOP Package, 1000 Units Tape & Reel X0AC ADC121S625CIMMX −40˚C to +85˚C 8-Lead MSOP Package, 3500 Units Tape & Reel X0AC ADC121S625EVAL Evaluation Board TRI-STATE ® is a trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2005 National Semiconductor Corporation DS201327 www.national.com ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter May 2005 ADC121S625 Block Diagram 20132702 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description 1 VREF 2 +IN Non-inverting input. 3 −IN Inverting input. 4 GND 5 CS Reference Voltage input. Ground pin. The ADC is in the active move when this pin is LOW and in the Power-Down Mode when this pin is HIGH. A conversion begins at the fall of CS. 6 DOUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of SCLK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 SCLK edges. 7 SCLK Serial Clock used to control data transfer. Also serves as the conversion clock. 8 VA www.national.com Power Supply input. 2 Operating Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Temperature Range Voltage on Any Pin to GND Supply Voltage, VA ± 10 mA ± 50 mA Package Input Current (Note 3) Power Consumption at TA = 25˚C See Figure 1 (Sect 2.3) Digital Input Pins Voltage Range Clock Frequency See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model +0.1V to 2.5V Input Common-Mode Voltage, VCM −0.3V to (VA +0.3V) Input Current at Any Pin (Note 3) +4.5V to +5.5V Reference Voltage, VREF −0.3V to 6.5V Analog Supply Voltage VA −40˚C ≤ TA ≤ +85˚C 0 to VA 0.8 MHz to 3.2 MHz Differential Analog Input Voltage −VREF to +VREF 2500V 250V Charge Device Modeling (CDM) 750V Soldering Temperature, Infrared, 10 seconds (Note 6) 260˚C Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Package Thermal Resistance Package θJA 8-lead MSOP 20˚C / W ADC121S625 Converter Electrical Characteristics (Note 8) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 to 3.2 MHz, fIN = 20 kHz, CL = 100 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Units (Note 7) Typical Limits 12 Bits +1.0 -1.0 LSB (max) LSB (min) ± 0.75 ±4 LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non-Linearity +0.5 −0.3 DNL Differential Non-Linearity ± 0.4 OE Offset Error FSE GE 0.4 LSB (max) Positive Full-Scale Error +0.2 LSB Negative Full-Scale Error +0.2 LSB Gain Error -0.05 ±4 LSB 68.5 dBc (min) DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, −0.1 dBFS 72.6 SNR Signal-to-Noise Ratio fIN = 20 kHz, −0.1 dBFS 72.9 70 dBc (min) THD Total Harmonic Distortion fIN = 20 kHz, −0.1 dBFS −84 −74 dBc (max) SFDR Spurious-Free Dynamic Range fIN = 20 kHz, −0.1 dBFS 85.2 74 dBc (min) ENOB Effective Number of Bits fIN = 20 kHz, −0.1 dBFS 11.8 11.1 bits (min) −3 dB Full Power Bandwidth Output at 70.7%FS with FS Input FPBW Differential Input 26 MHz Single-Ended Input 22 MHz ANALOG INPUT CHARACTERISTICS VIN Differential Input Range IDCL DC Leakage Current CINA Input Capacitance CMRR Common Mode Rejection Ratio VREF Reference Voltage Range ± 0.04 −VREF V (min) +VREF V (max) ±2 µA (max) In Track Mode 17 In Hold Mode 3 pF 82 dB 3 pF 0.1 V (min) 2.5 V (max) www.national.com ADC121S625 Absolute Maximum Ratings (Notes 1, 2) ADC121S625 ADC121S625 Converter Electrical Characteristics (Note 8) (Continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 to 3.2 MHz, fIN = 20 kHz, CL = 100 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 7) ANALOG INPUT CHARACTERISTICS IREF Reference Current CS low, fSCLK = 3.2 MHz, fS = 200 ksps, output = FF8h 12 µA CS low, fSCLK = 3.2 MHz, fS = 50 ksps, output = FF8h 3 µA CS low, fSCLK = 3.2 MHz, 12.5 ksps, output = FF8h 0.7 µA CS high, fSCLK = 0 0.3 µA DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage VA = 4.5V to 5.5V 2.4 V (min) VIL Input Low Voltage VA = 4.5V to 5.5V 0.8 V (max) IIN Input Current VIN = 0V or VA ± 0.03 1 µA (max) CIND Input Capacitance 2 4 pF (max) VA = 4.5V to 5.5V, ISOURCE = 250 µA VA − 0.05 VA − 0.2 V (min) VA = 4.5V to 5.5V, ISOURCE = 2 mA VA − 0.1 0.4 V (max) DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage IOZH, IOZL TRI-STATE Leakage Current COUT TRI-STATE Output Capacitance VA = 4.5V to 5.5V, ISINK = 250 µA 0.02 VA = 4.5V to 5.5V, ISOURCE = 2 mA 0.1 V V ± 0.03 ±1 µA (max) 2 4 pF (max) Output Coding Binary 2’S Complement POWER SUPPLY CHARACTERISTICS VA IA Active Analog Supply Voltage Supply Current, Normal Mode (Operational) IA Supply Current, Shutdown (CS high) Shutdown PWR Active Power Consumption, Normal Mode (Operational) PWR Power Consumption, Shutdown (CS Shutdown high) www.national.com 4.5 V (min) 5.5 V (max) 510 µA (max) fSCLK = 3.2 MHz, fSMPL = 200 ksps, fIN = 20 kHz, CL = 15pF 410 fSCLK = 3.2 MHz, fSMPL = 12.5 ksps, CL = 15pF, Power Down between conversions 31 µA fSCLK = 0.8 MHz, fSMPL = 50 ksps, CL = 15pF 242 µA fSCLK = 0.2 MHz, fSMPL = 12.5 ksps, CL = 15pF (Note 10) 200 µA fSCLK = 0 0.01 fSCLK = 3.2 MHz 2 6 µA (max) µA fSCLK = 3.2 MHz, fSMPL = 200 ksps, fIN = 20 kHz, CL = 15pF 2.25 fSCLK = 3.2 MHz, fSMPL = 12.5 ksps, CL = 15pF, Power Down between conversions 0.18 mW fSCLK = 0.8 MHz, fSMPL = 50 ksps, CL = 15pF 1.33 mW fSCLK = 0.2 MHz, fSMPL = 12.5 ksps, CL = 15pF (Note 10) 1.1 mW fSCLK = 0 0.06 fSCLK = 3.2 MHz 4 33 2.8 11 mW (max) µW (max) µW (Note 8) (Continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 to 3.2 MHz, fIN = 20 kHz, CL = 100 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits Units (Note 7) POWER SUPPLY CHARACTERISTICS PSRR Power Supply Rejection Ratio Offset Change with 1.0V change in VA 71 dB Gain Error Change with 1.0V change in VA 83 dB AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency 4.8 3.2 fSCLK Minimum Clock Frequency 200 800 kHz (max) fS Maximum Sample Rate 300 200 ksps (min) 1.5 SCLK cycles (min) 2.0 SCLK cycles (max) tACQ tCONV Track/Hold Acquisition Time Conversion Time tCYC Throughput Time fRATE Throughput Rate tAD Aperture Delay 12 MHz (min) 12 SCLK cycles Normal Operation 16 SCLK cycles Short Cycled 14 SCLK cycles (min) 200 ksps (max) 6 ns ADC121S625 Timing Specifications (Note 8) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 MHz to 3.2 MHz, CL = 100 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C. Symbol Parameter Conditions Typical Limits Units 0 ns (min) 0 ns (min) tCFCS SCLK Fall toCS Fall tCSCR CS Fall to SCLK Rise (Note 9) tCHLD SCLK Fall to Data Change Hold Time (Note 9) 10 ns (min) tCDV SCLK Fall to Next DOUT Valid 38 100 ns (max) tDIS Rising Edge of CS To DOUT Disabled 38 50 ns (max) tEN 2nd SCLK Fall after CS Fall to DOUT Enabled 6 50 ns (max) tCH SCLK High Time 42 60 ns (min) tCL SCLK Low Time 42 60 ns (min) tr DOUT Rise Time 5 50 ns (max) tf DOUT Fall Time 13 50 ns (max) Note 1: Absolute maximum ratings are limiting values which indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC121S625 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms. Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: Clock should be in low when CS is asserted, as indicated by the tCSCR and tCFCS specifications. Note 10: While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate being slower than fSCLK/16. 5 www.national.com ADC121S625 ADC121S625 Converter Electrical Characteristics ADC121S625 Timing Diagrams 20132701 ADC121S625 Single Cycle Timing Diagram 20132704 ADC121S625 Double Cycle Timing Diagram 20132710 Voltage Waveform for tEN 20132708 Timing Test Circuit 20132706 Voltage Waveform for DOUT, tr, tf 20132712 Voltage Waveform for tDIS 20132711 Voltage Waveforms for dOUT delay time, tCDV www.national.com 6 APERTURE DELAY is the time between the second falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the supply voltage is rejected. It is the ratio of the change in Full-Scale Gain Error or the Offset Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR = 20 LOG (∆VA / ∆Offset) PSRR = 20 LOG (∆VA / ∆Gain) COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. CMRR = 20 LOG (∆Common Input / ∆Output) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the difference between Positive Full Scale Error and Negative Full Scale Error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S625 is guaranteed not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from negative full scale and the next code and −VREF + 0.5 LSB OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 000h to 001h and 1/2 LSB. where Af1 is the RMS power of the input frequency at the output and Af2 through Af10 are the RMS power in the first 9 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. 7 www.national.com ADC121S625 POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale VREF minus 1.5 LSB. Specification Definitions ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. DNL - 50 ksps INL - 50 ksps 20132718 20132719 DNL - 200 ksps INL - 200 ksps 20132721 20132722 DNL vs. VA INL vs. VA 20132723 www.national.com 20132724 8 DNL vs. fSCLK INL vs. fSCLK 20132725 20132726 DNL vs. SCLK DUTY CYCLE INL vs. SCLK DUTY CYCLE 20132727 20132728 DNL vs. TEMPERATURE INL vs. TEMPERATURE 20132729 20132730 9 www.national.com ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. (Continued) ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. (Continued) SNR vs. VA THD vs. VA 20132731 20132732 SINAD vs. VA SFDR vs. VA 20132733 20132734 SNR vs. VREF THD vs. VREF 20132735 www.national.com 20132736 10 SINAD vs. VREF SFDR vs. VREF 20132737 20132738 SNR vs. CLOCK FREQUENCY THD vs. CLOCK FREQUENCY 20132739 20132740 SINAD vs. CLOCK FREQUENCY SFDR vs. CLOCK FREQUENCY 20132741 20132742 11 www.national.com ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. (Continued) ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. (Continued) SNR vs. SCLK DUTY CYCLE THD vs. SCLK DUTY CYCLE 20132743 20132744 SINAD vs. SCLK DUTY CYCLE SFDR vs. SCLK DUTY CYCLE 20132745 20132746 SNR vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY 20132747 www.national.com 20132748 12 SINAD vs. INPUT FREQUENCY SFDR vs. INPUT FREQUENCY 20132749 20132750 REF. CURRENT vs. TEMPERATURE (Output = FF8h) REF. CURRENT vs. SAMPLE RATE (Output = FF8h) 20132751 20132752 SUPPLY CURRENT vs. TEMPERATURE POWER DOWN CURRENT vs. TEMPERATURE 20132754 20132755 13 www.national.com ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. (Continued) ADC121S625 Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz unless otherwise stated. (Continued) OFFSET ERROR vs. VREF OFFSET ERROR vs. TEMPERATURE 20132756 20132757 GAIN ERROR vs. VREF GAIN ERROR vs. TEMPERATURE 20132758 20132759 Spectral Response - 50 ksps Spectral Response - 200 ksps 20132760 www.national.com 20132714 14 The ADC121S625 analog-to-digital converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sample/hold function. The architecture and process allow the ADC121S625 to acquire and convert an analog signal at sample rates up to 200,000 conversions per second while consuming very little power. The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the input is sampled. Hence, the only current required at the reference and at the analog inputs is only a series of transient spikes. The amount of these current spikes will depend, to some degree, upon the conversion code, but will not vary a great deal. The current required to recharge the input capacitance at the reference and analog signal inputs will cause voltage spikes at these pins. Do not try to filter our these noise spikes. Rather, ensure that the transient settles out during the sample period (1.5 clock cycles after the fall at the CS input). Lower reference voltages will decrease the current pulses at the reference input and, therefore, will slightly decrease the average input current there because the internal capacitance is required to take on a lower charge at lower reference voltages. The reference current changes only slightly with temperature. See the curves, “Reference Current vs. Sample Rate”, “Reference Current vs. Temperature” and “SNR vs. VREF” in the Typical Performance Curves section. The ADC121S625 requires an external reference and external clock, and a single +5V power source that can be as low as +4.5V. The external reference can be any voltage between 100mV and 2.5V. The value of the reference voltage determines the range of the analog input, while the reference input current depends on the conversion rate. The external clock can take on values as indicated in the Electrical Characteristics Table of this data sheet. The duty cycle of the clock is essentially unimportant, provided the minimum clock high and low times are met. The minimum clock frequency is set by internal capacitor leakage. Each conversion requires 16 SCLK cycles to complete. Short cycling can reduce this to 14 or 15 SCLK cycles, depending upon whether the clock edge after the fall of CS is a rise or a fall. See the timing diagrams. The analog input is presented to the two input pins: +IN and –IN. Upon initiation of a conversion, the differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from internal circuitry while a conversion is in progress. The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in progress. It is possible to continue to clock the ADC121S625 after the conversion is complete and to obtain the serial data least significant bit first. Each bit of the data word (including the leading null bit) is clocked out on subsequent falling edges of SCLK and can be clocked into the receiving device on the rising edges. See the Digital Interface section and timing diagram for more information. 2.0 ANALOG SIGNAL INPUTS The ADC121S625 has a differential input. As such, the effective input voltage that is digitized is (+IN) − (−IN). As is the case with any differential input A/D converter, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. Yet, the ADC121S625 can be presented with a single-ended input. 2.1 Differential Input Operation With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be obtained when (+IN) − (−IN) ≥ VREF − 1.5 LSB and a negative full scale code (1000 0000 0000b or 800h) will be obtained when (+IN) − (−IN) ≤ −VREF + 0.5 LSB. This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will determine any given output code. 1.0 REFERENCE INPUT The externally supplied reference voltage sets the analog input range. The ADC121S625 will operate with a reference voltage in the range of 100mV to 2.5V. However, care must be exercised when the reference voltage is less than 500 millivolts. As the reference voltage is reduced, the range of input voltages corresponding to each digital output code is reduced. That is, a smaller analog input range corresponds to one LSB (Least Significant Bit). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes below the noise floor of the ADC121S625, the noise will span an increasing number of codes and overall noise performance will suffer. That is, for dynamic signals the SNR will degrade and for d.c. measurements the code uncertainty will increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D converter will increase in terms of LSB size as the reference voltage is reduced. The ADC121S625 is more sensitive to nearby signals and EMI (electromagnetic interference) when a low reference 2.2 Single-Ended Input Operation For single-ended operation, the non-inverting input (+IN) of the ADC121S625 should be driven with a signal or voltages that have a maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting input (−IN) should be biased to a stable voltage that is half way between these maximum and minimum values. Note that single-ended operation should only be used if the performance degradation (compared with differential operation) is acceptable. 2.3 Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC121S625 and are depicted in Figure 1 and Figure 2. The minimum and maximum common mode voltages for differential and single-ended operation are shown in Table 1. 15 www.national.com ADC121S625 voltage is used. For this reason, extra care should be exercised in planning a clean layout, a low noise reference and a clean power supply when using low reference voltages. Functional Description ADC121S625 Functional Description 3.1 Digital Inputs The Digital inputs consist of the SCLK and CS. A falling CS initiates the conversion and data transfer. The time between the fall of CS and the second falling edge of SCLK is used to sample the input signal. The data output is enabled at the second falling edge of SCLK that follows the fall of CS. Since the first bit clocked out is a null bit, the MSB is clocked out on the third falling edge of SCLK after the fall of CS. For the next 12 SCLK periods DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, the output data is repeated if CS remains low after the LSB is output, but in a least significant bit first format, with the LSB being output only once, as indicated in the Double Cycle Timing Diagram. DOUT will go into its high impedance state after the B9 - B10 - B11 sequence. If CS is raised between prior to or at the 15th clock fall, DOUT will go into its high impedance state after the LSB (B0) is output and the data is not repeated. Additional clock cycles will not effect the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. (Continued) 20132761 3.1 SCLK Input The SCLK (serial clock) is used to time the conversion process and to clock out the conversion results. This input is TTL/CMOS compatible. Internal settling time limits the maximum clock frequency and internal capacitor leakage, or droop, limits the minimum clock frequency. The ADC121S625 offers guaranteed performance with clock rates in the range indicated in the electrical table. FIGURE 1. VCM range for Differential Input operation 3.2 Data Output The output data format of the ADC121S625 is Two’s Complement, as shown in Table 2. This table indicates the ideal output code for the given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. TABLE 2. Ideal Output Code vs. Input Voltage 2’s Complement Binary Output 2’s Comp. Hex Code VREF − 1 LSB 0111 1111 1111 7FF Midscale 0V 0000 0000 0000 000 Midscale − 1 LSB 0V − 1 LSB 1111 1111 1111 FFF −VREF 1000 0000 0000 800 Analog Input Description (+IN) − (−IN) + Full Scale 20132762 FIGURE 2. VCM range for single-ended operation TABLE 1. Allowable VCM Range Input Signal Differential Single-Ended Minimum VCM Maximum VCM VREF / 2 − 0.3V VA + 0.3V − ( VREF / 2 ) VREF − 0.3V VA + 0.3V − VREF − Full Scale Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC121S625: −40˚C ≤ TA ≤ +85˚C +4.5V VA ≤ +5.5V 0.1V ≤ VREF ≤ 2.5V 0.8 MHz ≤ fCLK ≤ 4.8 MHz VCM: See Section 2.3 3.0 SERIAL DIGITAL INTERFACE The ADC121S625 communicates via a synchronous 3-wire serial interface as shown in the timing diagram. Each output bit is sent on the falling edge of SCLK. While most receiving systems will capture the digital output bits on the rising edge of SCLK, the falling edge of SCLK may be used to capture each bit if the minimum hold time for DOUT is acceptable. www.national.com 16 sumption in both the converter and the rest of the system, because they spend more time in the power down mode and less time in the active mode. (Continued) 4.0 POWER CONSUMPTION The architecture, design and fabrication process allows the ADC121S625 to operate at conversion rates up to 200ksps while requiring very little power. In order to minimize power consumption in applications requiring sample rates below 50ksps, the ADC121S625 should be run at a fSCLK of 3.2 MHz and with the CS rate as slow as the system requires. The ADC will go into the power down mode at the end of each conversion, minimizing power consumption. See Section 4.2 for more information. However, some things should be kept in mind to absolutely minimize power consumption. The consumption scales directly with conversion rate, so minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. The ADC121S625 goes into its power down mode on the rising edge of CS or the 14th or 16th falling edge of SCLK after the fall of CS, as described in the Functional Description, whichever occurs first (see Timing Diagrams). Ideally, each conversion should occur as quickly as possible, preferably at the maximum rated clock rate and the CS rate used to determine the sample rate. This causes the converter to spend the longest possible time in the power down mode. This is very important for minimizing power consumption as the converter uses current for the analog circuitry, which continuously consumes power when converting. So, if less than 12 bits are needed, power may be saved by bringing CS high after clocking out the number of bits needed. Of course, the converter also uses power on each SCLK transition, as is typical for digital CMOS components, so stopping the clock when in the power down mode will further reduce power consumption. As mentioned in the Reference Input Section 1.0, power consumption is also slightly lower with lower reference voltages. There is an important difference between entering the power down mode after a conversion is complete and CS if left LOW and the full power down mode when CS is HIGH. Both of these power down the analog portion of the ADC121S625, but the digital portion is powered down only when CS is HIGH. So, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. Short cycling can also be used to reduce the required number of SCLK cycles from 16 to 14, allowing for a little faster throughput. That is, SCLK can be raised after the rise of the 14th SCLK, reducing the overall cycle time (tCYC) by about 12%. 4.2 Burst Mode Operation Normal operation requires the SCLK frequency to be 16 times the sample rate and the CS rate to be the same as the sample rate. However, because starting a new conversion requires a new fall of CS, it is possible to have the SCLK rate much higher than 16 times the CS rate. When this is done, the device is said to be operating in the Burst Mode. Burst Mode operation has the advantage of lowering overall power consumption because the device goes into power down when conversion is complete and only the output register and output drivers remain powered up to clock out the data. This circuit also powers down and the output drivers go into their high impedance state once the last bit is clocked out. Note that the output register and output drivers will remain powered up longer if CS is not brought high before the 15th fall of SCLK after the fall of CS. See the Double Cycle Timing Diagram. 5.0 TIMING CONSIDERATIONS Proper operation requires that the fall of CS occur between the fall and rise of SCLK. If the fall of CS occurs while SCLK is high, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and characteristics of the individual device. To ensure that the data is always clocked out at a time, it is essential that the fall of CS always occurs while SCLK is low. 6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS Care should be taken with the physical layout of the printed circuit board so that best performance may be realized. This is especially true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out much faster if accuracy is to be maintained. Any SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Spikes might originate, for example, from switching power supplies, digital logic, and high power devices, and other sources. This type of problem can be very difficult to track down if the glitch is almost synchronous to the converter’s SCLK, but the phase difference between SCLK and the noise source may change with time and temperature, causing sporadic problems. Power to the ADC121S625 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor and a 1µF to 10µF capacitor should be used to bypass the ADC121S625 supply, with the 0.1µF capacitor placed as close to the ADC121S625 package as possible. Adding a 10Ω resistor in series with the power supply line will help to low pass filter a noisy supply. The reference input should be bypassed with a minimum 0.1µF capacitor. A series resistor and large capacitor can be used to low pass filter the reference voltage. If the reference voltage originates from an op-amp, be careful that the opamp can drive the bypass capacitor without oscillation (the 4.1 Short Cycling Another way of saving power is to short cycle the conversion process. This is done by pulling the CS line high after the last required bit is received from the ADC121S625 output. This is possible because the ADC121S625 places the latest data bit on the DOUT line as it is generated. If only 8-bits of the conversion result are needed, for example, the conversion can be terminated by pulling CS HIGH after the 8th bit has been clocked out. Halting conversion after the last needed bit is received is called short cycling. Short cycling can be used to lower the power consumption in those applications that do not need a full 12-bit resolution, or where an analog signal is being monitored until some condition occurs. For example, it may not be necessary to use the full 12-bit resolution of the ADC121S625 as long as the signal being monitored is within certain limits. The conversion, then, can be terminated after the first few bits (as low as 3 or 4 bits, in some cases). This can lower power con- 17 www.national.com ADC121S625 Applications Information ADC121S625 Applications Information 7.1 Data Acquisition (Continued) Figure 3 shows a basic low cost, low power data acquisition circuit. Maximum clock rate with a minimum sample rate can reduce the power consumption further. series resistor can help in this case). Keep in mind that while the AD121S625 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference input that must settle out while SCLK is HIGH. Because these transient spikes can be almost as high as 20mA, it is important that the reference circuit be capable of providing this much current and settle out during the minimum 1.5 clock sampling period. Be sure to observe the minimum SCLK HIGH and LOW times. The reference input of the ADC121S625, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results. While high frequency noise can be filtered out as described above, voltage variation due to supply ripple (50Hz to 120Hz) can be difficult to remove. The use of an active reference source can ease this problem. The LM4040 and LM4050 shunt reference families and the LM4120, LM4121 and LM4140 low dropout series reference families offer a range of choices for a reference source. The GND pin on the ADC121S625 should be connected to the ground plane at a quiet point. While there are many opinions as to the best way to use power and ground planes, we have looked into this in great detail and have concluded that all methods can work well up to speeds of about 30MHz to 40MHz if there is strict adherence to the individual method. However, many of these methods lead to excessive EMI/RFI, which is not acceptable from a system standpoint. Generally, good layout and interconnect techniques can provide the provide excellent performance required while minimizing EMI/RFI, often without the need for shielding. We recommend a single ground plane and the use of two or more power planes. The power planes should all be in the same board layer and will define, for example, the analog board area, general digital board area and high power digital board area. Lines associated with these areas should always be routed within their respective areas. There are rules for those cases where a line must cross to another area, but that is beyond the scope of this document. Avoid connecting the GND pin too close to the ground point for a microprocessor, microcontroller, digital signal processor, or other high power digital device. 20132763 FIGURE 3. Low cost, low power Data Acquisition System 7.2 Motor Control Figure 4 is a motor control application that isolates the digital outputs of the AD121S625 instead of isolating the analog signal from the motor. As shown here, the reference voltage for the AD121S625 is 150mV, and the analog input of the AD121S625 is connected directly to the current sense resistor. Keeping isolation amplifiers out of the signal path enables a greater system signal-to-noise ratio. However, three optical isolators are needed to isolate the A/D converters rather than an isolation amplifier. For three-phase motors, three of these circuits are needed. 7.3 Strain Gauge Interface Figure 5 shows an example of interfacing a strain gauge or load cell to the AD121S625. The same voltage used to bias the strain gauge is used as a source for the reference voltage, providing ratiometric operation and making the system immune to variations in the source voltage. Of course, there is no immunity to noise on the reference source or on the strain gauge source. The value of the divider resistors to provide the reference voltage for the ADC121S625 may need to be changed to provide the desired reference voltage for the specific application. 7.0 APPLICATION CIRCUITS The following figures are examples of ADC121S625 typical application circuits. These circuits are basic ones and will generally require modification for specific circumstances. www.national.com 18 ADC121S625 Applications Information (Continued) 20132765 FIGURE 4. Motor Control using isolated ADC121S625 20132766 FIGURE 5. Interfacing the ADC121S625 to a strain gauge 19 www.national.com ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead MSOP Order Number ADC121S625CIMM NS Package Number MUA08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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