Preliminary Technical Data Integrated TFT Panel Power Supply with Gate Modulation and VCOM ADD8733 FEATURES BLOCK DIAGRAM XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ADD8733 STEP-UP SWITCHING REGULATOR AND POWER SEQUENCING STEP-DOWN SWITCHING REGULATOR TWO VCOM AMPLIFIERS GATE PULSE MODULATION VGH REGULATOR VGL REGULATOR X X X X X X UNDERVOLTAGE LOCKOUT AND THERMAL PROTECTION X X CONTROL 05952-001 Step-up switching regulator with 3 A switch current limit 8 V to 16.5 V input voltage range Adjustable output voltage up to 20 V 1.2 A series switch for power sequencing Overvoltage protection (OVP) Step-down switching regulator with 3 A switch current limit 8 V to 16.5 V input voltage range Adjustable output voltage down to 2.5 V Gate pulse modulator circuitry Independently adjustable delay and falling slope Positive charge-pump regulator for VGH Negative charge-pump regulator for VGL Two VCOM amplifiers General Power supply sequencing Thermal fault protection 650 kHz or 1.2 MHz PWM frequency Soft start Undervoltage lockout (UVLO) 48-lead RoHS compliant LFCSP Figure 1. APPLICATIONS TFT LCD panels for TVs and monitors GENERAL DESCRIPTION The ADD8733 is a 4-channel regulator with two VCOM amplifiers and gate pulse modulation (GPM) that provides all the necessary voltages for thin film transistor (TFT) liquid crystal displays (LCD). Included is a step-up regulator, a stepdown regulator for digital logic, two VCOM amplifiers, two charge-pump regulators for VGH and VGL, and an integrated gate pulse modulator. By offering a complete power integration solution optimized for TFT LCD TVs and monitors, the ADD8733 helps to lower cost, simplify board design, and increase performance over existing solutions. The ADD8733 is offered in a 48-lead RoHS compliant LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADD8733 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 VCOM Amplifier Specifications .................................................6 Applications....................................................................................... 1 General Specifications ..................................................................6 Block Diagram .................................................................................. 1 Absolute Maximum Ratings ............................................................7 General Description ......................................................................... 1 ESD Caution...................................................................................7 Specifications..................................................................................... 3 Pin Configuration And Function Descriptions ............................8 Step-Up Switching Regulator Specifications............................. 3 Timing Diagrams............................................................................ 10 Step-Down Regulator Specifications ......................................... 4 Typical Application Circuit ........................................................... 12 Positive Charge-Pump Regulator Specifications...................... 5 Land Pattern.................................................................................... 13 Negative Charge-Pump Regulator Specifications .................... 5 Outline Dimensions ....................................................................... 14 Gate Pulse Modulator Specifications ......................................... 5 Ordering Guide .......................................................................... 14 Rev. PrA | Page 2 of 16 Preliminary Technical Data ADD8733 SPECIFICATIONS STEP-UP SWITCHING REGULATOR SPECIFICATIONS VVIN = VSD_VIN = 12 V, L1= 15 μH, TA = 25°C, fOSC = 650 kHz, unless otherwise noted. Table 1. Parameter SUPPLY Input Voltage Maximum Duty Cycle OUTPUT Output Voltage Load Regulation Line Regulation Overall Regulation Overvoltage Protection REFERENCE FB Regulation Voltage ERROR AMPLIFIER Transconductance Error Amplifier Open-Loop Voltage Gain Input Bias Current SWITCH On Resistance Peak Current Limit OSCILLATOR Oscillator Frequency 1 Symbol Conditions VIN Min Typ 8.0 Max Unit 16.5 V % 20 V % % % V 70 VSU_OUT VIN + 1 200 mA ≤ ILOAD ≤ 800 mA, VSU_OUT = 18 V ILOAD = 500 mA, 8 V ≤ VSD_VIN ≤ 16.5 V, VSU_OUT = 18 V Line, load, temperature VSU_D 1 1 19.5 20 ±3 20.5 VSU_FB 2.5 V gm AVSU IB 100 1000 100 μA/V V/V nA RDS (ON)SU ISUCLSET 100 3 mΩ A 650 1200 kHz kHz fOSC FREQ = GND FREQ = VSR_OUT 1 VSR_OUT pin provides a logic-high output of 5 V. Rev. PrA | Page 3 of 16 ADD8733 Preliminary Technical Data STEP-DOWN REGULATOR SPECIFICATIONS VVIN = VSD_VIN = 12 V, L2=10 μH, TA = 25°C, fOSC = 650 kHz, unless otherwise noted. Table 2. Parameter SUPPLY Input Voltage Minimum Duty Cycle OUTPUT Output Voltage Load Regulation Line Regulation Overall Regulation ERROR AMPLIFER FB Regulation Voltage FB Input Bias Current Error Amplifier Open-Loop Voltage Gain COMP Output Current SWITCH On Resistance Peak Current Limit OSCILLATOR Oscillator Frequency 1 Symbol Conditions VSD_VIN Min Typ 8.0 Max Unit 16.5 V % 5 V % % % 15 VSTEP_DN 2.5 500 mA ≤ ILOAD ≤ 1000 mA, VSTEP_DN = 3.3 V ILOAD = 750 mA, 8 V ≤ VSD_VIN ≤ 16.5 V, VSTEP_DN = 3.3 V Line, load, temperature VSD_FB ISD_FB AVSD ISD_COMP 1 1 ±3 2.5 TBD TBD TBD V nA V/V μA RDS (ON)SD ISDCLSET SD_BS = 5 V, ISD_LOAD = 750 mA 100 3 mΩ A fOSC FREQ = GND FREQ = VSR_OUT 1 650 1200 kHz kHz VSR_OUT pin provides a logic-high output of 5 V. Rev. PrA | Page 4 of 16 Preliminary Technical Data ADD8733 POSITIVE CHARGE-PUMP REGULATOR SPECIFICATIONS VNPCP_SUP = 12 V, TA = 25°C, fOSC = 650 kHz, unless otherwise noted. Table 3. Parameter SUPPLY Supply Voltage OUTPUT Output Current REFERENCE FB Regulation Voltage Symbol Min VNPCP_SUP 8 Typ Max Unit 20 V IVGH 50 mA VNPCP_FB 2.5 V NEGATIVE CHARGE-PUMP REGULATOR SPECIFICATIONS VNPCP_SUP = 12 V, TA = 25°C, fOSC = 650 kHz, unless otherwise noted. Table 4. Parameter SUPPLY Supply Voltage OUTPUT Output Voltage Output Current REFERENCE Reference Voltage FB Regulation Voltage Symbol Min VNPCP_SUP 8 VGL IVGL Typ (−VNPCP_SUP + 3) VNCP_REF VNCP_FB Max Unit 20 V −2 70 V mA 2.5 0 V V GATE PULSE MODULATOR SPECIFICATIONS VSD_VIN = 12 V, VGPM_H = 28 V, VGPM_L = 12 V 1 , TA = 25°C, unless otherwise noted. Table 5. Parameter INPUT CHARACTERISTICS GPM_H Voltage GPM_H Input Current GPM_L Voltage GPM_L Input Current CONTROL INPUT CHARACTERISTICS GPM_FLK Voltage Low GPM_FLK Voltage High GPM_FLK Input Current GPM_DPM Voltage Low GPM_DPM Voltage High GPM_DPM Input Current SWITCHING CHARACTERISTICS GPM_OUT Discharge Current DELAY CHARACTERISTICS Delay Time 1 Symbol VGPM__H IGPM__H VGPM_L IGPM_L Conditions Min Typ GPM_L + 6 GPM_FLK = GND, GPM_DPM = logic high Max Unit 30 V μs V μs TBD 5 GPM_FLK = GPM_DPM = logic high GPM_H – 6 TBD VLOWFLK VHIGHFLK IGPM_FLK VLOWDPM VHIGHDPM IGPM_DPM 0.9 V ≤ GPM_FLK ≤ 3.3 V 2.2 −1 0.8 0.9 V ≤ VGPM_DPM ≤ 3.3 V 2.2 −1 IGPM_OUT RE = 400 Ω , GPM_L = 12 V 30 mA tDELAY CE = 470 pF TBD μs Refer to Figure 6 in the Typical Application Circuit section. Rev. PrA | Page 5 of 16 +1 0.8 +1 V V μA V V μA ADD8733 Preliminary Technical Data VCOM AMPLIFIER SPECIFICATIONS VSU_S = 12 V, VCx_POS = 6.0 V, TA = 25°C, unless otherwise noted. Table 6. Parameter INPUT CHARACTERISTICS Offset Voltage Noninverting Input Bias Current Input Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing (High) Output Voltage Swing (Low) Output Current Limit POWER SUPPLY Supply Voltage Power Supply Rejection Ratio Supply Current 1 1 Symbol Conditions Min Typ VOS IB TBD 50 Max Unit 300 SU_S − 2 CMRR VCM = 2 V to (SU_S − 3) V 60 mV nA V dB VOH VOL IOUT Buffer, IVC_OUT (source) = 100 μA Buffer, IVC_OUT (sink) = 100 μA SU_S − 0.08 30 ±250 V mV mA 2 VSU_S PSRR ISY 7.5 V ≤ SU_S ≤ 20.5 V No load, VCx_POS = SU_S/2 8 65 20 V dB mA 70 2 Supply current for one VCOM amplifier. GENERAL SPECIFICATIONS VVIN = VSD_VIN = 12 V, TA = 25°C, unless otherwise noted. Table 7. Parameter SUPPLY Applied Input Voltage (VIN) UNDERVOLTAGE LOCKOUT Rising Input Voltage (VIN) Falling Input Voltage (VIN) THERMAL PROTECTION Thermal Shutdown Thermal Shutdown SERIES SWITCH On Resistance Peak Current Symbol Conditions VVIN VUVLOR VUVLOF Min Typ 8 Max Unit 16.5 V TBD 7.5 7.2 V V Rising temperature Falling temperature 145 105 °C °C RDS (ON)SSW ISSWPKC 200 TBD Rev. PrA | Page 6 of 16 mΩ mA Preliminary Technical Data ADD8733 ABSOLUTE MAXIMUM RATINGS Table 8. 1 Parameter SD_VIN/SD_SW/SD_BS/SD_FB/SD_COMP to SU_PGND NCP_REF/NCP_FB/NCP_DRV to NPCP_GND PCP_FB/PCP_DRV/NPCP_SUP to NPCP_GND GPM_FLK/GPM_CE/GPM_DPM to GND GPM_RE/GPM_OUT/GPM_H/GPM_L to GND VC1_POS/VC1_NEG/VC1_OUT/VC2_OUT/VC2_POS/ VC2_NEG to VC1_GND SU_SW/SU_D/SU_S/SU_FB/SU_COMP to SU_PGND VGL_DLY/SU_DLY/SD_SS/SU_SS/VSR_OUT to GND Voltage Between SU_PGND, NPCP_GND, and GND Package Power Dissipation (PD) Thermal Resistance for Exposed Pad Soldered to 4-Layer JEDEC PC Board (θJA) Maximum Junction Temperature (TJ) Operating Temperature Range (TA) Storage Temperature Range (TS) Reflow Peak Temperature (20 sec to 40 sec) 1 Rating TBD TBD TBD TBD TBD TBD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION TBD TBD ±0.5 (TJ max − TA)/θJA 25.88°C/W 125°C −40°C to +85°C −65°C to +150°C 250°C SU_PGND, VC1_GND, NPCP_GND, and GND are connected to a common ground connection. Rev. PrA | Page 7 of 16 ADD8733 Preliminary Technical Data 48 47 46 45 44 43 42 41 40 39 38 37 VC1_NEG VC1_GND VC2_OUT VC2_POS VC2_NEG SU_S SU_S SU_FB SU_D SU_D SU_SW SU_SW PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VC1_POS VC1_OUT 1 2 ADD8733 TOP VIEW (Not to Scale) 36 35 34 33 SU_PGND SU_PGND GND SD_EN 32 31 30 29 28 27 26 25 SU_EN SU_COMP SU_SS SU_DLY FREQ VSR_OUT SD_VIN SD_VIN 05952-002 NPCP_SUP NCP_DRV GND NCP_FB NCP_REF VGL_DLY SD_SS SD_COMP SD_FB SD_BS SD_SW SD_SW 13 14 15 16 17 18 19 20 21 22 23 24 GPM_L 3 GPM_CE 4 GPM_FLK 5 GPM_DPM 6 GPM_RE 7 GPM_OUT 8 GPM_H 9 PCP_FB 10 NPCP_GND 11 PCP_DRV 12 PIN 1 INDICATOR Figure 2. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23, 24 25, 26 27 28 29 30 31 Mnemonic VC1_POS VC1_OUT GPM_L GPM_CE GPM_FLK GPM_DPM GPM_RE GPM_OUT GPM_H PCP_FB NPCP_GND PCP_DRV NPCP_SUP NCP_DRV GND NCP_FB NCP_REF VGL_DLY SD_SS SD_COMP SD_FB SD_BS SD_SW SD_VIN VSR_OUT FREQ SU_DLY SU_SS SU_COMP Function Input Output Input Input Power Out Power In Input GND Power In GND Input Input Input Power In Description VCOM Amplifier 1 Positive Input VCOM Amplifier 1 Output Low Level Voltage for Gate Pulse Modulation Capacitor Programmable FLK to Falling Slope Delay Control Pin for Gate Pulse Modulation Control Pin for Gate Pulse Modulation (On/Off ) Resistor Programmable Gate Pulse Modulation Falling Slope VGH/Gate Pulse Modulation Output High Level Voltage for Gate Pulse Modulation Positive Charge Pump Feedback Positive and Negative Charge Pump Ground Positive Charge Pump Capacitor Drive Positive and Negative Charge Pump Power In Negative Charge Pump Capacitor Drive Voltage Subregulator Ground Pin Negative Charge Pump Feedback Negative Charge Pump Reference Delay for Step-Down Soft Start for Step-Down Step-Down Regulator Compensation Step-Down Regulator Feedback Step-Down Regulator Bootstrap Driver Power Input Step-Down Regulator Switch Node Power VIN for Step-Down Regulator's High Side Switch Voltage Subregulator Output Voltage Frequency Select Delay for Step-Up Soft Start for Step-Up Step-Up Regulator Compensation Rev. PrA | Page 8 of 16 Preliminary Technical Data Pin No. 32 33 34 35, 36 37, 38 39, 40 41 42, 43 44 45 46 47 48 Mnemonic SU_EN SD_EN GND SU_PGND SU_SW SU_D SU_FB SU_S VC2_NEG VC2_POS VC2_OUT VC1_GND VC1_NEG Function GND GND Power In Input Power Out Input Input Output GND Input ADD8733 Description Step-Up Enable for Power Supply Sequencing Step-Down Enable for Power Supply Sequencing Ground Pin Ground Pin for Step-Up Step-Up Regulator Switch Node Power In for Step-Up Regulator Power Supply Sequencing Switch Step-Up Regulator Feedback Output from Step-Up Regulator Power Supply Sequencing Switch VCOM Amplifier 2 Negative Input VCOM Amplifier 2 Positive Input VCOM Amplifier 2 Output Ground Pin for VCOM Amplifier 1 VCOM Amplifier 1 Negative Input Rev. PrA | Page 9 of 16 ADD8733 Preliminary Technical Data TIMING DIAGRAMS GPM_DPM GND GPM_FLK GND t1 t2 SLOPE CONTROLLED BY GPM_RE AND V GMP_L GMP_H GMP_L GPM_OUT GND t1 05952-003 t2 DELAY CONTROLLED BY GPM_CE Figure 3. Timing Diagram for Gate Pulse Modulator Rev. PrA | Page 10 of 16 Preliminary Technical Data ADD8733 SU_EN SD_EN SU_DLY SU_OUT SU_OUT SD_OUT SD_OUT, VGL VGL VGL_DLY GPM_OUT 05952-004 GPM_DPM GPM_FLK Figure 4. Timing Diagram for Power-Up Sequence 1 SU_EN (HIGH) SD_EN SU_DLY SU_OUT SU_OUT STEP_DN STEP_DN, VGL VGL VGL_DLY GPM_OUT 05952-005 GPM_DPM GPM_FLK Figure 5. Timing Diagram for Power-Up Sequence 2 Rev. PrA | Page 11 of 16 ADD8733 Preliminary Technical Data TYPICAL APPLICATION CIRCUIT C6, C7, C8 C5 R18 VIN1 SD_VIN SD_VIN C1, C2, C3, C4 SU_SW VIN D1 SK33A-TP L1 15µH VIN1 SU_SW F1 SU_PGND SU_PGND SU_D SU_D NPCP_SUP C26 R24 SU_D R31 C32 C38 NCP_REF SU_COMP R17 NCP_FB R11 D4 C11 R21 VGL SU_S C31 SU_OUT SU_S NCP_DRV R30 C16 R36 R33 C39 C40 R34 R27 VCOM1_NEG VCOM1_OUT R35 SU_OUT VIN1 GPM_L R2 VC1_NEG VC1_OUT R23 VC2_NEG VC2_OUT R29 VCOM2_NEG VCOM2_OUT SU_FB VC1_GND GMP_H PCP_FB R10 ADD8733 R37 SU_OUT PCP_DRV R13 GPM_FLK GPM_FLK C42 SD_BS C22, C23, C24, C25 R6 C10 R8 SD_SW GPM_DPM SD_SW GPM_OUT D2 GPM_CE SD_FB R4 GPM_OUT C28 R7 GPM_RE C20 SD_COMP R20 GPM_DPM C15 C37 C21 D5 C12 D3 L2 C9 R9 VSR_OUT C27, C41 STEP_DN R25 GPM_H FREQ R28 JP4 C33, C34, C35 R32 VC2_POS VC1_POS POT2 POT1 NPCP_GND R26 C18 VGL_DLY R3 SD_EN R14 C13 C19 SD_EN SU_EN SU_EN C14 SD_SS C29 GND SU_DLY C30 GND SU_SS Figure 6. Typical Application Circuit with Component Variables, 650 kHz Rev. PrA | Page 12 of 16 05952-006 R16 Preliminary Technical Data ADD8733 LAND PATTERN 7.31mm HEAT SINK SOLDER PASTE AREA 5.40mm 1.90mm 1.60mm 5.93mm 5.78mm 0.69mm 1.60mm 0.075mm 0.5mm 0.33mm DIAMETER THERMAL VIA Figure 7. 48-Lead LFCSP (CP-48-1) Land Pattern Rev. PrA | Page 13 of 16 0.28mm 05952-007 0.075mm ADD8733 Preliminary Technical Data OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 48 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 8. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model ADD8733ACPZ-REEL 1 1 Temperature Range −40°C to +85°C Package Description 48-Lead LFCSP Z = RoHS Compliant Part. Rev. PrA | Page 14 of 16 Package Option CP-48-1 Preliminary Technical Data ADD8733 NOTES Rev. PrA | Page 15 of 16 ADD8733 Preliminary Technical Data NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05952-0-4/07(PrA) Rev. PrA | Page 16 of 16