High Speed, Dual, 2 A MOSFET Driver ADP3629/ADP3630/ADP3631 FEATURES GENERAL DESCRIPTION Industry-standard-compatible pinout High current drive capability Precise threshold shutdown comparator UVLO with hysteresis Overtemperature warning signal Overtemperature shutdown 3.3 V-compatible inputs Rise time and fall time: 10 ns typical at 2.2 nF load Fast propagation delay Matched propagation delays between channels Supply voltage: 9.5 V to 18 V Dual outputs can be operated in parallel (ADP3629/ADP3630) Rated from −40°C to +85°C ambient temperature 8-lead SOIC_N and 8-lead MSOP The ADP3629/ADP3630/ADP3631 are dual, high current, high speed drivers, capable of driving two independent N-channel power MOSFETs. The ADP3629/ADP3630/ADP3631 use the industry-standard footprint but add high speed switching performance and improved system reliability. APPLICATIONS The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers. The ADP3629/ADP3630/ADP3631 have an internal temperature sensor and provide two levels of overtemperature protection: an overtemperature warning and an overtemperature shutdown at extreme junction temperatures. The SD function, generated from a precise internal comparator, provides fast system enable or shutdown. This feature allows redundant overvoltage protection, complementing the protection inside the main controller device, or provides safe system shutdown in the event of an overtemperature warning. AC-to-DC switch mode power supplies DC-to-DC power supplies Synchronous rectification Motor drives Digital power controllers are supplied from a low voltage supply, and the driver is supplied from a higher voltage supply. The ADP3629/ADP3630/ADP3631 add UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers. FUNCTIONAL BLOCK DIAGRAM VDD ADP3629/ADP3630/ADP3631 8 SD 1 OTW OVERTEMPERATURE PROTECTION VDD VEN NONINVERTING INA, 2 INA 7 OUTA INVERTING PGND 3 UVLO 6 VDD NONINVERTING INB, 4 INB 08401-101 5 OUTB INVERTING Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP3629/ADP3630/ADP3631 TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuit ...................................................................................... 10 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Input Drive Requirements (INA, INA, INB, INB, and SD) .. 11 Functional Block Diagram .............................................................. 1 Low-Side Drivers (OUTA, OUTB) .......................................... 11 Revision History ............................................................................... 2 Shutdown (SD) Function .......................................................... 11 Specifications..................................................................................... 3 Overtemperature Protections ................................................... 12 Timing Diagrams.......................................................................... 4 Supply Capacitor Selection ....................................................... 12 Absolute Maximum Ratings............................................................ 6 PCB Layout Considerations ...................................................... 12 Thermal Resistance ...................................................................... 6 Parallel Operation ...................................................................... 12 ESD Caution .................................................................................. 6 Thermal Considerations............................................................ 13 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 14 REVISION HISTORY 9/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADP3629/ADP3630/ADP3631 SPECIFICATIONS VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted. 1 Table 1. Parameter SUPPLY Supply Voltage Range Supply Current Symbol Standby Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Hysteresis DIGITAL INPUTS (INA, INA, INB, INB, SD) Input Voltage High Input Voltage Low Input Current SD Threshold High ISBY No switching, INA, INA, INB, and INB disabled SD = 5 V VUVLO_ON VUVLO_OFF VDD rising, TA = 25°C VDD falling, TA = 25°C SD Threshold Low SD Hysteresis Internal Pull-Up/Pull-Down Current OUTPUTS (OUTA, OUTB) Output Resistance, Unbiased Peak Source Current Peak Sink Current SWITCHING TIME OUTA, OUTB Rise Time OUTA, OUTB Fall Time OUTA, OUTB Rising Propagation Delay OUTA, OUTB Falling Propagation Delay SD Propagation Delay Low SD Propagation Delay High Delay Matching Between Channels OVERTEMPERATURE PROTECTION Overtemperature Warning Threshold Overtemperature Shutdown Threshold Temperature Hysteresis for Shutdown Temperature Hysteresis for Warning Overtemperature Warning Low 1 VDD IDD VIH VIL IIN VSD_H VSD_L VSD_HYST Test Conditions/Comments Min Typ Max Unit 1.2 18 3 V mA 1.2 3 mA 8.7 7.7 1.0 9.5 8.5 V V V 9.5 8.0 7.0 2.0 0 V < VIN < VDD TA = 25°C TA = 25°C TA = 25°C −20 1.19 1.21 0.95 240 1.28 1.28 1.0 280 6 0.8 +20 1.38 1.35 1.05 320 V V μA V V V mV μA VDD = PGND See Figure 20 See Figure 20 80 2 −2 tRISE tFALL tD1 tD2 tdL_SD tdH_SD CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 See Figure 2 See Figure 2 10 10 14 22 32 48 2 25 25 30 35 45 75 ns ns ns ns ns ns ns TW TSD THYS_SD THYS_W VOTW_OL See Figure 6 See Figure 6 See Figure 6 See Figure 6 Open drain, −500 μA 135 165 30 10 150 180 °C °C °C °C V 120 150 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods. Rev. 0 | Page 3 of 16 kΩ A A 0.4 ADP3629/ADP3630/ADP3631 TIMING DIAGRAMS SD tdL_SD tdH_SD OUTA, OUTB 08401-002 90% 10% Figure 2. Shutdown Timing Diagram VIH INA, INB VIL tD1 tRISE tD2 90% 90% OUTA, OUTB tFALL 10% 08401-003 10% Figure 3. Output Timing Diagram (Noninverting) VIL INA, INB VIH tD1 tRISE tD2 90% 90% OUTA, OUTB tFALL 10% 08401-103 10% Figure 4. Output Timing Diagram (Inverting) VUVLO_ON VUVLO_OFF UVLO MODE NORMAL OPERATION OUTPUTS DISABLED UVLO MODE OUTPUTS DISABLED Figure 5. UVLO Function Rev. 0 | Page 4 of 16 08401-005 VDD ADP3629/ADP3630/ADP3631 TSD TSD – THYS_SD TW TW – THYS_W TJ OT WARNING OT SHUTDOWN OT WARNING OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED NORMAL OPERATION 08401-006 NORMAL OPERATION OTW Figure 6. Overtemperature Warning and Shutdown Rev. 0 | Page 5 of 16 ADP3629/ADP3630/ADP3631 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VDD OUTA, OUTB DC <200 ns INA, INA, INB, INB, SD ESD Human Body Model (HBM) Field Induced Charged Device Model (FICDM) SOIC_N MSOP Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) θJA is specified for a device soldered in a 4-layer circuit board and is measured per JEDEC standards JESD51-2, JESD51-5, and JESD51-7. Rating −0.3 V to +20 V −0.3 V to VDD + 0.3 V −2 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Table 3. Thermal Resistance Package Type 8-Lead SOIC_N 8-Lead MSOP 3.5 kV 1.5 kV 1.0 kV −40°C to +150°C −65°C to +150°C ESD CAUTION 300°C 215°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 16 θJA 110.6 162.2 Unit °C/W °C/W ADP3629/ADP3630/ADP3631 SD 1 INA 2 ADP3629 8 OTW 7 OUTA PGND 3 6 VDD TOP VIEW INB 4 (Not to Scale) 5 OUTB 08401-008 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 7. ADP3629 Pin Configuration Table 4. ADP3629 Pin Function Descriptions Mnemonic SD INA PGND INB OUTB VDD OUTA OTW Description Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. Inverting Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Inverting Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor. Output Pin for Channel A Gate Driver. Overtemperature Warning Flag. Open drain, active low. SD 1 INA 2 ADP3630 8 OTW 7 OUTA PGND 3 6 VDD TOP VIEW INB 4 (Not to Scale) 5 OUTB 08401-001 Pin No. 1 2 3 4 5 6 7 8 Figure 8. ADP3630 Pin Configuration Table 5. ADP3630 Pin Function Descriptions Mnemonic SD INA PGND INB OUTB VDD OUTA OTW Description Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor. Output Pin for Channel A Gate Driver. Overtemperature Warning Flag. Open drain, active low. SD 1 INA 2 ADP3631 8 OTW 7 OUTA PGND 3 6 VDD TOP VIEW INB 4 (Not to Scale) 5 OUTB 08401-009 Pin No. 1 2 3 4 5 6 7 8 Figure 9. ADP3631 Pin Configuration Table 6. ADP3631 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic SD INA PGND INB OUTB VDD OUTA OTW Description Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. Inverting Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor. Output Pin for Channel A Gate Driver. Overtemperature Warning Flag. Open drain, active low. Rev. 0 | Page 7 of 16 ADP3629/ADP3630/ADP3631 TYPICAL PERFORMANCE CHARACTERISTICS 25 9 V UVLO_ON 8 20 V UVLO_OFF TIME (ns) UVLO (V) 7 6 15 tFALL 10 tRISE 5 5 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 08401-022 3 –50 0 5 Figure 10. UVLO vs. Temperature 10 VDD (V) 15 20 08401-012 4 Figure 13. Rise and Fall Times vs. VDD 14 70 12 60 tFALL 10 tdH_SD 50 TIME (ns) TIME (ns) tRISE 8 6 40 tdL_SD 30 tD2 4 20 2 10 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 08401-010 0 5 Figure 11. Rise and Fall Times vs. Temperature 20 1400 VDD = 12V tdH_SD SHUTDOWN THRESHOLD (mV) 40 tdL_SD 30 tD2 20 VSD_H 1200 50 tD1 10 1000 VSD_L 800 600 400 VSD_HYST 200 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 –50 08401-011 TIME (ns) 15 Figure 14. Propagation Delay vs. VDD 60 0 –50 10 VDD (V) Figure 12. Propagation Delay vs. Temperature –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 Figure 15. Shutdown Threshold vs. Temperature Rev. 0 | Page 8 of 16 130 08401-014 0 –50 08401-013 tD1 ADP3629/ADP3630/ADP3631 OUTA/OUTB OUTA/OUTB 2 2 VDD = 12V TIME = 20ns/DIV 1 08401-023 VDD = 12V TIME = 20ns/DIV 1 INA/INB Figure 16. Typical Rising Propagation Delay (Noninverting) Figure 18. Typical Rise Time (Noninverting) OUTA/OUTB OUTA/OUTB 2 2 INA/INB INA/INB 1 Figure 17. Typical Falling Propagation Delay (Noninverting) VDD = 12V TIME = 20ns/DIV Figure 19. Typical Fall Time (Noninverting) Rev. 0 | Page 9 of 16 08401-026 VDD = 12V TIME = 20ns/DIV 08401-024 1 08401-025 INA/INB ADP3629/ADP3630/ADP3631 TEST CIRCUIT ADP3629/ADP3630/ADP3631 1 SD 2 OTW 8 INA, INA A OUTA 7 INVERTING VDD 3 PGND NONINVERTING VDD 6 4.7µF CERAMIC 100nF CERAMIC CLOAD B INB, INB OUTB 5 INVERTING 08401-007 4 SCOPE PROBE NONINVERTING Figure 20. Test Circuit Rev. 0 | Page 10 of 16 ADP3629/ADP3630/ADP3631 THEORY OF OPERATION The ADP3629/ADP3630/ADP3631 family of dual drivers is optimized for driving two independent enhancement N-channel MOSFETs or insulated gate bipolar transistors (IGBTs) in high switching frequency applications. LOW-SIDE DRIVERS (OUTA, OUTB) These applications require high speed, fast rise and fall times, and short propagation delays. The capacitive nature of MOSFETs and IGBTs requires high peak current capability, as well. When the ADP3629/ADP3630/ADP3631 are disabled, both low-side gates are held low. An internal impedance is present between the OUTA/OUTB pins and GND, even when VDD is not present; this feature ensures that the power MOSFET is normally off when bias voltage is not present. ADP3629/ADP3630/ADP3631 2 OTW 8 VDS NONINVERTING INA, INA When interfacing the ADP3629/ADP3630/ADP3631 to external MOSFETs, the designer should consider ways to create a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the OUTA and OUTB pins, as well as on the external MOSFET. A OUTA 7 INVERTING VDD 3 PGND NONINVERTING VDD 6 VDS 4 B INB, INB OUTB Power MOSFETs are usually selected to have low on resistance to minimize conduction losses, which usually implies a large input gate capacitance and gate charge. 5 08401-017 INVERTING Figure 21. Typical Application Circuit INPUT DRIVE REQUIREMENTS (INA, INA, INB, INB, AND SD) The inputs of the ADP3629/ADP3630/ADP3631 are designed to meet the requirements of modern digital power controllers; the signals are compatible with 3.3 V logic levels. At the same time, the input structure allows for input voltages as high as VDD. The signals applied to the inputs (INA, INA, INB, and INB) should have steep and clean fronts. It is not recommended that slow changing signals be applied to drive these inputs because such signals can result in multiple switching output signals when the thresholds are crossed, causing damage to the power MOSFET or IGBT. SHUTDOWN (SD) FUNCTION The ADP3629/ADP3630/ADP3631 feature an advanced shutdown function with accurate thresholds and hysteresis. The SD signal is an active high signal. An internal pull-up is present on this pin and, therefore, it is necessary to pull down the pin externally for the drivers to operate normally. In some power systems, it is sometimes necessary to provide an additional overvoltage protection (OVP) or overcurrent protection (OCP) shutdown signal to turn off the power devices (MOSFETs or IGBTs) in case of failure of the main controller. An accurate internal reference is used for the SD comparator so that it can be used to detect OVP or OCP fault conditions. + DC OUTPUT An internal pull-down resistor is present at the input, which guarantees that the power device is off in the event that the input is left floating. AC INPUT The SD input has a precision comparator with hysteresis and is therefore suitable for slow changing signals (such as a scaleddown output voltage); see the Shutdown (SD) Function section for more information about this comparator. – OUTA PGND SD VEN ADP3629/ADP3630/ADP3631 Figure 22. Shutdown Function Used for Redundant OVP Rev. 0 | Page 11 of 16 08401-018 1 SD The ADP3629/ADP3630/ADP3631 family of dual drivers is designed to drive ground referenced N-channel MOSFETs. The bias is internally connected to the VDD supply and to PGND. ADP3629/ADP3630/ADP3631 OVERTEMPERATURE PROTECTIONS PCB LAYOUT CONSIDERATIONS The ADP3629/ADP3630/ADP3631 provide two levels of overtemperature protection: Use the following general guidelines when designing printed circuit boards (PCBs) for the ADP3629/ADP3630/ADP3631: • • • Overtemperature warning (OTW) Overtemperature shutdown The overtemperature warning is an open-drain logic signal and is active low. In normal operation, when no thermal warning is present, the signal is high, whereas when the warning threshold is crossed, the signal is pulled low. 3.3V VDD • • • • OTW Trace out the high current paths and use short, wide (>40 mil) traces to make these connections. Minimize trace inductance between the OUTA and OUTB outputs and the MOSFET gates. Connect the PGND pin as close as possible to the source of the MOSFETs. Place the VDD bypass capacitor as close as possible to the VDD and PGND pins. When possible, use vias to other layers to maximize thermal conduction away from the IC. Figure 24 shows an example of the typical layout based on the preceding guidelines. FLAGIN ADP3629/ADP3630/ADP3631 ADP1043 PGND VDD ADP3629/ADP3630/ADP3631 PGND 08401-019 OTW 08401-027 Figure 23. OTW Signaling Scheme Example The OTW open-drain configuration allows the connection of multiple devices to the same warning bus in a wire-OR’ed configuration, as shown in Figure 23. PARALLEL OPERATION The overtemperature shutdown turns off the device to protect it in the event that the die temperature exceeds the absolute maximum limit of 150°C (see Table 2). The two driver channels in the ADP3629 and ADP3630 devices can be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver. SUPPLY CAPACITOR SELECTION The connection scheme for the ADP3630 is shown in Figure 25. In this configuration, INA and INB are connected together, and OUTA and OUTB are connected together. Figure 24. External Component Placement Example An improper decoupling can dramatically increase the rise times, cause excessive resonance on the OUTA and OUTB pins, and, in some extreme cases, even damage the device due to inductive overvoltage on the VDD or OUTA/OUTB pins. Particular attention must be paid to the layout in this case to optimize load sharing between the two drivers. The minimum capacitance required is determined by the size of the gate capacitances being driven, but as a general rule, a 4.7 μF, low ESR capacitor should be used. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. To further reduce noise, use a smaller ceramic capacitor (100 nF) with a better high frequency characteristic in parallel with the main capacitor. Place the ceramic capacitor as close as possible to the ADP3629/ ADP3630/ADP3631 device and minimize the length of the traces going from the capacitor to the power pins of the device. Rev. 0 | Page 12 of 16 OTW 8 1 SD ADP3630 2 INA A OUTA 7 VDD 3 PGND VDD 6 VDS 4 INB B OUTB 5 08401-021 A local bypass capacitor for the supply input (VDD) of the ADP3629/ADP3630/ADP3631 is recommended to reduce the noise and to supply some of the peak currents that are drawn. Figure 25. Parallel Operation ADP3629/ADP3630/ADP3631 THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding the maximum junction temperature. In addition to the gate charge losses, there are also dc bias losses (PDC) due to the bias current of the driver. This current is present regardless of the switching frequency. Data on package thermal resistance is provided in Table 3 to help the designer in this task. Several equally important aspects must also be considered. • • • • • • In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be ignored, and the extra loss is assumed to be in the driver, providing a good guard band for the power loss calculations. PDC = VDD × IDD Gate charge of the power MOSFET being driven Bias voltage value used to power the driver Maximum switching frequency of operation Value of external gate resistance Maximum ambient (and PCB) temperature Type of package The total estimated loss is the sum of PDC and PGATE. PLOSS = PDC + (n × PGATE) where n is the number of gates driven. When the total power loss is calculated, the temperature increase can be calculated as follows: All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundreds of nC and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as follows: ΔTJ = PLOSS × θJA Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 100 kHz, using an ADP3630 in the MSOP package. The maximum PCB temperature considered for this design is 85°C. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 100 kHz = 144 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 144 mW) = 302.4 mW The MSOP thermal resistance is 162.2°C/W (see Table 3). ΔTJ = 302.4 mW × 162.2°C/W = 49.0°C PGATE = VGS × QG × fSW TJ = TA + ΔTJ = 134.0°C ≤ TJ_MAX where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. The power dissipated for each gate (PGATE) must be multiplied by the number of drivers (in this case, 1 or 2) being used in each package; this PGATE value represents the total power dissipated in charging and discharging the gates of the power MOSFETs. If a lower junction temperature is required by the design, the SOIC_N package, which provides a thermal resistance of 110.6°C/W, can be used. Using the SOIC_N package, the maximum junction temperature is Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and to minimize switching losses. ΔTJ = 302.4 mW × 110.6°C/W = 33.4°C TJ = TA + ΔTJ = 118.4°C ≤ TJ_MAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing the switching frequency, and choosing a power MOSFET with a smaller gate charge. Rev. 0 | Page 13 of 16 ADP3629/ADP3630/ADP3631 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model ADP3629ARZ-R7 1 ADP3629ARMZ-R71 ADP3630ARZ-R71 ADP3630ARMZ-R71 ADP3631ARZ-R71 ADP3631ARMZ-R71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 Package Option R-8 RM-8 R-8 RM-8 R-8 RM-8 Ordering Quantity 2,500 3,000 2,500 3,000 2,500 3,000 Branding L8Q L8R L8S ADP3629/ADP3630/ADP3631 NOTES Rev. 0 | Page 15 of 16 ADP3629/ADP3630/ADP3631 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08401-0-9/09(0) Rev. 0 | Page 16 of 16