High Speed, Dual, 4 A MOSFET Driver with Thermal Protection ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 FEATURES GENERAL DESCRIPTION Industry-standard-compatible pinout High current drive capability Precise threshold shutdown comparator UVLO with hysteresis Overtemperature warning signal Overtemperature shutdown 3.3 V-compatible inputs 10 ns typical rise time and fall time @ 2.2 nF load Matched propagation delays between channels Fast propagation delay 9.5 V to 18 V supply voltage (ADP3633/ADP3634/ADP3635) 4.5 V to 18 V supply voltage (ADP3623/ADP3624/ADP3625) Parallelable dual outputs Rated from −40°C to +85°C ambient temperature Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead MINI_SO_EP The ADP362x/ADP363x is a family of high current and dual high speed drivers, capable of driving two independent N-channel power MOSFETs. The family uses the industry-standard footprint but adds high speed switching performance and improved system reliability. The family has an internal temperature sensor and provides two levels of overtemperature protection, an overtemperature warning, and an overtemperature shutdown at extreme junction temperatures. The SD function, generated from a precise internal comparator, provides fast system enable or shutdown. This feature allows redundant overvoltage protection, complementing the protection inside the main controller device, or provides safe system shutdown in the event of an overtemperature warning. The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers. APPLICATIONS Digital power controllers are supplied from a low voltage supply, and the driver is supplied from a higher voltage supply. The ADP362x/ADP363x family adds UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers. AC-to-dc switch mode power supplies DC-to-dc power supplies Synchronous rectification Motor drives The device family is available in thermally enhanced SOIC_N_EP and MINI_SO_EP packaging to maximize high frequency and current switching in a small printed circuit board (PCB) area. FUNCTIONAL BLOCK DIAGRAM VDD ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 8 SD 1 OTW OVERTEMPERATURE PROTECTION VDD VEN NONINVERTING INA, 2 INA 7 OUTA INVERTING PGND 3 UVLO 6 VDD NONINVERTING INB, 4 INB 08132-101 5 OUTB INVERTING Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Input Drive Requirements (INA, INA, INB, INB, and SD) .. 12 General Description ......................................................................... 1 Low-Side Drivers (OUTA, OUTB) .......................................... 12 Functional Block Diagram .............................................................. 1 Shutdown (SD) Function .......................................................... 12 Revision History ............................................................................... 2 Overtemperature Protections ................................................... 12 Specifications..................................................................................... 3 Supply Capacitor Selection ....................................................... 13 Timing %JBHSBNT ................................................................ 4 PCB Layout Considerations ...................................................... 13 Absolute Maximum Ratings ............................................................ 6 Parallel Operation ...................................................................... 13 ESD Caution .................................................................................. 6 Thermal Considerations............................................................ 14 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 16 Test Circuit ...................................................................................... 11 REVISION HISTORY 7/09—Rev. 0 to Rev. A Added ADP3623, ADP3625, ADP3633, and ADP3635 .............................................................................. Universal Changes to Features Section, General Description Section, and Figure 1 ....................................................................................... 1 Changes to Table 1 ............................................................................ 3 Added Figure 4; Renumbered Sequentially .................................. 4 Added Figure 7.................................................................................. 7 Added Table 3; Renumbered Sequentially .................................... 7 Added Figure 9 and Table 5............................................................. 8 Changes to Figure 10 ........................................................................ 9 Changes to Figure 16 to Figure 19 Captions ............................... 10 Changes to Figure 20...................................................................... 11 Changes to Figure 21, Input Drive Requirements (INA, INA, INB, INB, and SD) Section, and Figure 22 ........................ 12 Changes to Figure 23 and Parallel Operation Section ............... 13 Changes to Design Example Section ........................................... 14 Changes to Ordering Guide .......................................................... 16 5/09—Revision 0: Initial Version Rev. A | Page 2 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 SPECIFICATIONS VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted. 1 Table 1. Parameter SUPPLY Supply Voltage Range Supply Current Standby Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Symbol Test Conditions/Comments Min VDD VDD IDD ISBY ADP3633/ADP3634/ADP3635 ADP3623/ADP3624/ADP3625 No switching, INA, INA, INB, and INB disabled SD = 5 V 9.5 4.5 VUVLO_ON VUVLO_ON VUVLO_OFF VUVLO_OFF VDD rising, TA = 25°C, ADP3633/ADP3634/ADP3635 VDD rising, TA = 25°C, ADP3623/ADP3624/ADP3625 VDD falling, TA = 25°C, ADP3633/ADP3634/ADP3635 VDD falling, TA = 25°C, ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 ADP3623/ADP3624/ADP3625 8.0 3.8 7.0 3.5 Hysteresis DIGITAL INPUTS (INA, INA, INB, INB, SD) Input Voltage High Input Voltage Low Input Current SD Threshold High SD Threshold Low SD Hysteresis Internal Pull-Up/Pull-Down Current OUTPUTS (OUTA, OUTB) Output Resistance, Unbiased Peak Source Current Peak Sink Current SWITCHING TIME OUTA, OUTB Rise Time OUTA, OUTB Fall Time OUTA, OUTB Rising Propagation Delay OUTA, OUTB Falling Propagation Delay SD Propagation Delay Low SD Propagation Delay High Delay Matching Between Channels OVERTEMPERATURE PROTECTION Overtemperature Warning Threshold Overtemperature Shutdown Threshold Temperature Hysteresis for Shutdown Temperature Hysteresis for Warning Overtemperature Warning Low 1 VIH VIL IIN VSD_H VSD_H VSD_L VSD_HYST Typ Max Unit 1.2 1.2 18 18 3 3 V V mA mA 9.5 4.5 8.5 4.3 V V V V V V 8.7 4.2 7.7 3.9 1.0 0.3 2.0 0 V < VIN < VDD TA = 25°C TA = 25°C TA = 25°C −20 1.19 1.21 0.95 240 1.28 1.28 1.0 280 6 0.8 +20 1.38 1.35 1.05 320 V V µA V V V mV µA VDD = PGND See Figure 20 See Figure 20 80 4 −4 tRISE tFALL tD1 tD2 tdL_SD tdH_SD CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 See Figure 2 See Figure 2 10 10 14 22 32 48 2 25 25 30 35 45 75 ns ns ns ns ns ns ns TW TSD THYS_SD THYS_W VOTW_OL See Figure 6 See Figure 6 See Figure 6 See Figure 6 Open drain, −500 µA 135 165 30 10 150 180 °C °C °C °C V All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods. Rev. A | Page 3 of 16 120 150 kΩ A A 0.4 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TIMING %*"(3".4 SD tdL_SD tdH_SD OUTA, OUTB 08132-002 90% 10% Figure 2. Shutdown Timing Diagram VIH INA, INB VIL tD1 tRISE tFALL tD2 90% 90% OUTA, OUTB 10% 08132-003 10% Figure 3. Output Timing Diagram (Noninverting) INA, INB VIH VIL tD1 tRISE tD2 90% 90% OUTA, OUTB tFALL 10% 08132-003 10% Figure 4. Output Timing Diagram (Inverting) VUVLO_ON VUVLO_OFF UVLO MODE NORMAL OPERATION OUTPUTS DISABLED UVLO MODE OUTPUTS DISABLED Figure 5. UVLO Function Rev. A | Page 4 of 16 08132-005 VDD ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TSD TSD – THYS_SD TW TW – THYS_W TJ OT WARNING OT SHUTDOWN OT WARNING OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED NORMAL OPERATION 08132-006 NORMAL OPERATION OTW Figure 6. Overtemperature Warning and Shutdown Rev. A | Page 5 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD OUTA, OUTB DC <200 ns INA, INA, INB, INB, and SD ESD Human Body Model (HBM) Field Induced Charged Device Model (FICDM) SOIC_N_EP MINI_SO_EP θJA, JEDEC 4-Layer Board SOIC_N_EP1 MINI_SO_EP1 Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +20 V −0.3 V to VDD + 0.3 V −2 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V 3.5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1.5 kV 1.0 kV 59°C/W 43°C/W −40°C to +150°C −65°C to +150°C 300°C 215°C 260°C θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as appropriate with the exposed pad soldered to the PCB. Rev. A | Page 6 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SD 1 INA 2 ADP3623/ ADP3633 8 OTW 7 OUTA PGND 3 NOTES 1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. 08132-008 6 VDD TOP VIEW INB 4 (Not to Scale) 5 OUTB Figure 7. ADP3623/ADP3633 Pin Configuration Table 3. ADP3623/ADP3633 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic SD INA PGND INB OUTB VDD OUTA OTW Description Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. Inverting Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Inverting Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor. Output Pin for Channel A Gate Driver. Overtemperature Warning Flag. Open drain, active low. SD 1 INA 2 ADP3624/ ADP3634 8 OTW 7 OUTA 6 VDD TOP VIEW INB 4 (Not to Scale) 5 OUTB NOTES 1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. 08132-001 PGND 3 Figure 8. ADP3624/ADP3634 Pin Configuration Table 4. ADP3624/ADP3634 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic SD INA PGND INB OUTB VDD OUTA OTW Description Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor. Output Pin for Channel A Gate Driver. Overtemperature Warning Flag. Open drain, active low. Rev. A | Page 7 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 SD 1 INA 2 ADP3625/ ADP3635 8 OTW 7 OUTA 6 VDD TOP VIEW INB 4 (Not to Scale) 5 OUTB NOTES 1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. 08132-009 PGND 3 Figure 9. ADP3625/ADP3635 Pin Configuration Table 5. ADP3625/ADP3635 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic SD INA PGND INB OUTB VDD OUTA OTW Description Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. Inverting Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor. Output Pin for Channel A Gate Driver. Overtemperature Warning Flag. Open drain, active low. Rev. A | Page 8 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TYPICAL PERFORMANCE CHARACTERISTICS 25 9 V UVLO_ON 8 20 V UVLO_OFF ADP3633/ADP3634/ADP3635 TIME (ns) UVLO (V) 7 6 5 15 tFALL 10 tRISE ADP3623/ADP3624/ADP3625 V UVLO_ON 5 4 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 08132-022 3 –50 0 5 10 VDD (V) 15 20 08132-012 V UVLO_OFF Figure 13. Rise and Fall Times vs. VDD Figure 10. UVLO vs. Temperature 70 14 60 12 tFALL tdH_SD 50 10 TIME (ns) TIME (ns) tRISE 8 6 40 tdL_SD 30 tD2 4 20 2 10 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 08132-010 0 5 60 20 1400 VDD = 12V tdH_SD SHUTDOWN THRESHOLD (mV) 40 tdL_SD 30 tD2 20 SD THRESHOLD HIGH 1200 50 tD1 10 1000 SD THRESHOLD LOW 800 600 400 SD THRESHOLD HYSTERESIS 200 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 –50 08132-011 TIME (ns) 15 Figure 14. Propagation Delay vs. VDD Figure 11. Rise and Fall Times vs. Temperature 0 –50 10 VDD (V) Figure 12. Propagation Delay vs. Temperature –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 Figure 15. Shutdown Threshold vs. Temperature Rev. A | Page 9 of 16 130 08132-014 0 –50 08132-013 tD1 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 OUTA/OUTB OUTA/OUTB 2 2 VDD = 12V TIME = 20ns/DIV 1 08132-023 VDD = 12V TIME = 20ns/DIV 1 INA/INB Figure 16. Typical Rise Propagation Delay (Noninverting) Figure 18. Typical Rise Time (Noninverting) OUTA/OUTB OUTA/OUTB 2 2 INA/INB INA/INB 1 Figure 17. Typical Fall Propagation Delay (Noninverting) VDD = 12V TIME = 20ns/DIV Figure 19. Typical Fall Time (Noninverting) Rev. A | Page 10 of 16 08132-026 VDD = 12V TIME = 20ns/DIV 08132-024 1 08132-025 INA/INB ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TEST CIRCUIT ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 1 SD 2 OTW 8 INA, INA A OUTA 7 INVERTING VDD 3 PGND NONINVERTING VDD 6 4.7µF CERAMIC 100nF CERAMIC CLOAD B INB, INB OUTB 5 INVERTING 08132-007 4 SCOPE PROBE NONINVERTING Figure 20. Test Circuit Rev. A | Page 11 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 THEORY OF OPERATION The ADP362x/ADP363x family of dual drivers is optimized for driving two independent enhancement N-channel MOSFETs or insulated gate bipolar transistors (IGBTs) in high switching frequency applications. These applications require high speed, fast rise and fall times, as well as short propagation delays. The capacitive nature of the aforementioned gated devices requires high peak current capability as well. VDS INA, INA SHUTDOWN (SD) FUNCTION A OUTA 7 The ADP362x/ADP363x family features an advanced shutdown function, with accurate threshold and hysteresis. INVERTING VDD 3 PGND NONINVERTING The SD signal is an active high signal. An internal pull-up is present on this pin and, therefore, it is necessary to pull down the pin externally for drivers to operate normally. VDD 6 VDS 4 B INB, INB OUTB 5 08132-017 INVERTING Figure 21. Typical Application Circuit INPUT DRIVE REQUIREMENTS (INA, INA, INB, INB, AND SD) The ADP362x/ADP363x family inputs are designed to meet the requirements of modern digital power controllers; the signals are compatible with 3.3 V logic levels. At the same time, the input structure allows for input voltages as high as VDD. In some power systems, it is sometimes necessary to provide an additional overvoltage protection (OVP) or overcurrent protection (OCP) shutdown signal to turn off the power devices (MOSFETs or IGBTs) in case of failure of the main controller. An accurate internal reference is used for the SD comparator so that it can be used to detect OVP or OCP fault conditions. + DC OUTPUT AC INPUT The signals applied to the inputs (INA, INA, INB, and INB) should have steep and clean fronts. It is not recommended to apply slow changing signals to drive these inputs because they can result in multiple switching when the thresholds are crossed, causing damage to the power MOSFET or IGBT. – OUTA PGND SD VEN An internal pull-down resistor is present at the input, which guarantees that the power device is off in the event that the input is left floating. ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 The SD input has a precision comparator with hysteresis and is therefore suitable for slow changing signals (such as a scaled down output voltage); see the Shutdown (SD) Function section for more details on this comparator. LOW-SIDE DRIVERS (OUTA, OUTB) The ADP362x/ADP363x family of dual drivers is designed to drive ground referenced N-channel MOSFETs. The bias is internally connected to the VDD supply and PGND. When the ADP362x/ADP363x family is disabled, both low-side gates are held low. An internal impedance is present between the OUTA/OUTB pins and GND, even when VDD is not present; 08132-018 2 OTW 8 NONINVERTING When interfacing the ADP362x/ADP363x family to external MOSFETs, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the OUTA and OUTB pins, as well as the external MOSFET. Power MOSFETs are usually selected to have a low on resistance to minimize conduction losses, which usually implies a large input gate capacitance and gate charge. ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 1 SD this feature ensures that the power MOSFET is normally off when bias voltage is not present. Figure 22. Shutdown Function Used for Redundant OVP OVERTEMPERATURE PROTECTIONS The ADP362x/ADP363x family provides two levels of overtemperature protections: • • Overtemperature warning (OTW) Overtemperature shutdown The overtemperature warning is an open-drain logic signal and is active low. In normal operation, when no thermal warning is present, the signal is high, whereas when the warning threshold is crossed, the signal is pulled low. Rev. A | Page 12 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 • 3.3V VDD • OTW Place the VDD bypass capacitor as close as possible to the VDD and PGND pins. Use vias to other layers, when possible, to maximize thermal conduction away from the IC. Figure 24 shows an example of the typical layout based on the preceding guidelines. FLAGIN ADP3623/ADP3624/ADP3625/ ADP3633/ADP3634/ADP3635 ADP1043A PGND VDD ADP3623/ADP3624/ADP3625/ ADP3633/ADP3634/ADP3635 PGND 08132-019 OTW Figure 23. OTW Signaling Scheme Example 08132-027 The OTW open-drain configuration allows connection of multiple devices to the same warning bus in a wire-OR’ed configuration, as shown in Figure 23. The overtemperature shutdown turns off the device to protect it in the event that the die temperature exceeds the absolute maximum limit in Table 2. SUPPLY CAPACITOR SELECTION For the supply input (VDD) of the ADP362x/ADP363x family, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. An improper decoupling can dramatically increase the rise times, cause excessive resonance on the OUTA and OUTB pins, and, in some extreme cases, even damage the device, due to inductive overvoltage on the VDD or OUTA/OUTB pins. The minimum capacitance required is determined by the size of the gate capacitances being driven, but as a general rule, a 4.7 µF, low ESR capacitor should be used. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Use a smaller ceramic capacitor (100 nF) with a better high frequency characteristic in parallel to the main capacitor to further reduce noise. Figure 24. External Component Placement Example Note that the exposed pad of the package is not directly connected to any pin of the package, but it is electrically and thermally connected to the die substrate, which is the ground of the device. PARALLEL OPERATION The two driver channels present in the ADP3623/ADP3633 or ADP3624/ADP3634 devices can be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver. The connection scheme for the ADP3624/ADP3634 devices is shown in Figure 25. In this configuration, INA and INB are connected together, and OUTA and OUTB are connected together. Particular attention must be paid to the layout in this case to optimize load sharing between the two drivers. Keep the ceramic capacitor as close as possible to the ADP362x/ ADP363x device, and minimize the length of the traces going from the capacitor to the power pins of the device. PCB LAYOUT CONSIDERATIONS • 2 INA A OUTA 7 Trace out the high current paths and use short, wide (>40 mil) traces to make these connections. Minimize trace inductance between the OUTA and OUTB outputs and MOSFET gates. Connect the PGND pin of the ADP362x/ADP363x device as closely as possible to the source of the MOSFETs. Rev. A | Page 13 of 16 3 PGND VDD 6 VDS 4 INB B OUTB 5 08132-021 • ADP3624/ADP3634 VDD Use the following general guidelines when designing printed circuit boards (PCBs): • OTW 8 1 SD Figure 25. Parallel Operation ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding maximum junction temperature. Data on package thermal resistance is provided in Table 2 to help the designer in this task. There are several equally important aspects that must be considered. • • • • • • In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be neglected, and the extra loss is assumed in the driver, providing a good guard band to the power loss calculations. In addition to the gate charge losses, there are also dc bias losses, due to the bias current of the driver. This current is present regardless of the switching. PDC = VDD × IDD The total estimated loss is the sum of PDC and PGATE. Gate charge of the power MOSFET being driven Bias voltage value used to power the driver Maximum switching frequency of operation Value of external gate resistance Maximum ambient (and PCB) temperature Type of package PLOSS = PDC + (n × PGATE) where n is the number of gates driven. When the total power loss is calculated, the temperature increase can be calculated as All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundreds of nC, and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as: ΔTJ = PLOSS × θJA Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 300 kHz, using an ADP3624 in the SOIC_N_EP package. The maximum PCB temperature considered for this design is 85°C. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 300 kHz = 432 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW From the MOSFET data sheet, the SOIC_N_EP thermal resistance is 59°C/W. ΔTJ = 878.4 mW × 59°C/W = 51.8°C PGATE = VGS × QG × fSW TJ = TA + ΔTJ = 136.8°C ≤ TJMAX where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. The power dissipated for each gate (PGATE) still needs to be multiplied by the number of drivers (in this case, 1 or 2) being used in each package, and it represents the total power dissipated in charging and discharging the gates of the power MOSFETs. If a lower junction temperature is required by the design, the MINI_SO_EP package can be used, which provides a thermal resistance of 43°C/W, so that the maximum junction temperature is Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor is, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and minimize switching losses. ΔTJ = 878.4 mW × 43°C/W = 37.7°C TJ = TA + ΔTJ = 122.7°C ≤ TJMAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing switching frequency, and choosing a power MOSFET with smaller gate charge. Rev. A | Page 14 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 OUTLINE DIMENSIONS 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 8 2.29 (0.090) 5 2.29 (0.090) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) TOP VIEW 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 4 BOTTOM VIEW 1.27 (0.05) BSC (PINS UP) 0.50 (0.020) 0.25 (0.010) 1.65 (0.065) 1.25 (0.049) 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) MAX COPLANARITY 0.10 SEATING PLANE 0.51 (0.020) 0.31 (0.012) 0.25 (0.0098) 0.17 (0.0067) 45° 1.27 (0.050) 0.40 (0.016) 8° 0° COMPLIANT TO JEDEC STANDARDS MS-012-A A 072808-A CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters and (inches) 3.10 3.00 2.90 5 8 TOP VIEW 1 EXPOSED PAD 4 PIN 1 INDICATOR 0.65 BSC 0.94 0.86 0.78 0.15 0.10 0.05 COPLANARITY 0.10 5.05 4.90 4.75 0.525 BSC 1.10 MAX 0.40 0.33 0.25 SEATING PLANE BOTTOM VIEW 1.83 1.73 1.63 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.23 0.18 0.13 8° 0° 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA-T Figure 27. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] (RH-8-1) Dimensions shown in millimeters Rev. A | Page 15 of 16 071008-A 3.10 3.00 2.90 2.26 2.16 2.06 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 ORDERING GUIDE Model ADP3623ARDZ-RL1 UVLO Option 4.5 V Temperature Range −40°C to +85°C ADP3623ARHZ-RL1 4.5 V −40°C to +85°C ADP3624ARDZ1 4.5 V −40°C to +85°C ADP3624ARDZ-RL1 4.5 V −40°C to +85°C ADP3624ARHZ1 ADP3624ARHZ-RL1 4.5 V 4.5 V −40°C to +85°C −40°C to +85°C ADP3625ARDZ-RL1 4.5 V −40°C to +85°C ADP3625ARHZ-RL1 4.5 V −40°C to +85°C ADP3633ARDZ-RL1 9.5 V −40°C to +85°C ADP3633ARHZ-RL1 9.5 V −40°C to +85°C ADP3634ARDZ1 9.5 V −40°C to +85°C ADP3634ARDZ-RL1 9.5 V −40°C to +85°C ADP3634ARHZ1 ADP3634ARHZ-RL1 9.5 V 9.5 V −40°C to +85°C −40°C to +85°C ADP3635ARDZ-RL1 9.5 V −40°C to +85°C ADP3635ARHZ-RL1 9.5 V −40°C to +85°C 1 Package Description 8-Lead Standard Small Outline Package (SOIC_N_EP), 13“ Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP) 8-Lead Standard Small Outline Package (SOIC_N_EP), Tape Reel 8-Lead Mini Small Outline Package (MINI_SO_EP) 8-Lead Mini Small Outline Package (MINI_SO_EP), Tape Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP) 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP) 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08132-0-7/09(A) Rev. A | Page 16 of 16 Package Option RD-8-1 Ordering Quantity 2,500 Branding RH-8-1 3,000 P3 RD-8-1 RD-8-1 2,500 RH-8-1 RH-8-1 3,000 RD-8-1 2,500 RH-8-1 3,000 RD-8-1 2,500 RH-8-1 3,000 P4 P4 P5 L3 RD-8-1 RD-8-1 2,500 RH-8-1 RH-8-1 3,000 RD-8-1 2,500 RH-8-1 3,000 L4 L4 L5