ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 14-/12-Bit, 250-MSPS ADCs With Integrated Analog Buffer FEATURES 1 • • • • • • • • • • • Integrated High Impedance Analog Input Buffer Maximum Sample Rate: 250 MSPS 14-Bit Resolution – ADS61B49 12-Bit Resolution – ADS61B29 790 mW Total Power Dissipation at 250 MSPS Double Data Rate (DDR) LVDS and Parallel CMOS Output Options Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation DC Offset Correction Supports Input Clock Amplitude Down to 400 mVPP Differential 48-QFN Package (7mm × 7mm) Pin Compatible with ADS6149 Family APPLICATIONS • • • • • • • • • Multicarrier, Wide Bandwidth Communications Wireless Multi-Carrier Communications Infrastructure Software Defined Radio Power Amplifier Linearization Feedback ADC 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems DESCRIPTION The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range. The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C). ADS614X 14-Bit Family ADS612X 12-Bit Family ANALOG BUFFER 250 MSPS 210 MSPS NO ADS6149 ADS6148 YES ADS61B49 NO ADS6129 YES ADS61B29 ADS6128 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DRGND DRVDD AGND AVDD ADS61B49 BLOCK DIAGRAM LVDS Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P Analog Buffer D2_D3_M D4_D5_P D4_D5_M INP Sample and Hold 14-Bit ADC Digital Encoder Serializer D6_D7_P D6_D7_M INM D8_D9_P D8_D9_M D10_D11_P D10_D11_M VCM Control Interface Reference D12_D13_P D12_D13_M OVR_SDOUT DFS MODE SEN SDATA SCLK RESET ADS61B49 B0095-08 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 DRGND DRVDD AGND AVDD ADS61B29 BLOCK DIAGRAM LVDS Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P Analog Buffer D2_D3_M D4_D5_P D4_D5_M INP Sample and Hold 14-Bit ADC Digital Encoder Serializer D6_D7_P D6_D7_M INM D8_D9_P D8_D9_M D10_D11_P D10_D11_M VCM Control Interface Reference OVR_SDOUT DFS MODE SEN SDATA SCLK RESET ADS61B29 B0095-09 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 3 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com PACKAGE/ORDERING INFORMATION (1) (2) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE LEAD/BALL FINISH PACKAGE MARKING ADS61B49 QFN-48 RGZ –40°C to 85°C Cu NiPdAu AZ61B49 ADS61B29 QFN-48 RGZ –40°C to 85°C Cu NiPdAu AZ61B29 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS61B49IRGZR Tape and reel ADS61B49IRGZT ADS61B29IRGZR Tape and reel ADS61B29IRGZT For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41° C/W (0LFM air flow), θJC = 16.5° C/W when used with 2oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62 cm) PCB. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT Supply Voltage, AVDD -0.3 to 3.9 V Supply Voltage, DRVDD -0.3 to 2.2 V Voltage between AGND and DRGND -0.3 to 0.3 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 to 3.3 V Voltage between DRVDD to AVDD (when DRVDD leads AVDD) -1.5 to 1.8 V -0.3 to minimum (3.6, AVDD + 0.3) V -0.3 to (AVDD + 0.3) V Voltage applied to analog input pins - INP, INM Voltage applied to input pins - CLKP, CLKM (2), RESET, SCLK, SDATA, SEN, DFS and MODE TA Operating free-air temperature range -40 to 85 °C TJ Max Operating junction temperature 125 °C Tstg Storage temperature range -65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < 0.3V.) This prevents the ESD protection diodes at the clock input pins from turning on. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage DRVDD Digital supply voltage ANALOG INPUTS Differential input voltage range 2 Vpp Input common-mode voltage (different than ADS6149 family) 2.3 ±0.1 Maximum analog input frequency with 2Vpp input amplitude (1) 500 MHz V Maximum analog input frequency with 1Vpp input amplitude (1) 800 MHz CLOCK INPUT Input clock sample rate 1 Sine wave, ac-coupled Input clock amplitude differential (VCLKP–VCLKM) (1) 4 0.3 250 MSPS 1.5 LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled 3.3 Vpp V See the Theory of Operations in the applications section. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) Input clock duty cycle MIN NOM MAX 40% 50% 60% UNIT DIGITAL OUTPUTS CL Maximum external load capacitance from each output pin to DRGND RL Differential load resistance between the LVDS output pairs (LVDS mode) TA Operating free-air temperature 5 pF Ω 100 –40 85 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 °C 5 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS – ADS61B49 and ADS61B29 Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS61B49/ADS61B29 250 MSPS MIN TYP UNIT MAX ANALOG INPUT Differential input voltage range Differential input resistance (at dc), See Figure 62 Differential input capacitance, See Figure 63 2 VPP 10 kΩ 2 Analog input bandwidth pF 750 Analog Input common-mode current (per input pin) MHz µA 2 VCM common-mode output voltage (different than ADS6149 family) 2.3 V VCM output current capability ±4 mA DC ACCURACY Offset error -15 Temperature coefficient of offset error Gain error due to internal reference inaccuracy alone EGCHAN Gain error of channel alone Temperature coefficient of EGCHAN +15 0.005 Variation of offset error with supply EGREF ±2 mV/°C 0.3 -2.5 ±0.2 mV mV/V +2.5 %FS 0.2 %FS .001 Δ%/°C POWER SUPPLY IAVDD IDRVDD Analog supply current 200 mA Output buffer supply current, LVDS interface with 100-Ω external termination 70 mA Output buffer supply current, CMOS interface Fin = 3 MHz, 10-pF external load capacitance 56 mA Analog power 660 730 mW Digital power LVDS interface 130 160 mW Digital power CMOS interface, Fin = 3 MHz, 10-pF external load capacitance 101 Global power down 20 Standby 6 120 Submit Documentation Feedback mW 75 mW mW Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS – ADS61B49 and ADS61B29 Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS61B49 250 MSPS MIN SNR Signal-to-noise ratio, LVDS MIN 72.3 70.1 72 69.8 71.6 69.6 Fin = 100 MHz 68.5 70.7 66.5 67.8 Fin = 20 MHz 72.5 70.3 Fin = 80 MHz 71.8 69.7 Fin = 100 MHz 71.6 67.5 dBFS 69 69 Fin = 170 MHz UNIT TYP MAX Fin = 80 MHz Fin = 300 MHz ENOB Effective number of bits TYP MAX Fin = 20 MHz Fin = 170 MHz SINAD Signal-to-noise and distortion ratio, LVDS ADS61B29 250 MSPS 69.5 70 65.7 dBFS 68.4 Fin = 300 MHz 67.1 66.3 Fin = 170 MHz (using SINAD in dBFS) 11.3 11.1 LSB DNL Differential non-linearity -0.95 ±0.4 1 -0.5 ±0.2 1 LSB INL Integrated non-linearity -5 ±2 5 -2.5 ±1 2.5 LSB Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 7 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS – ADS61B49 and ADS61B29 Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS61B49/ADS61B29 250 MSPS MIN SFDR Spurious free dynamic range THD Total harmonic distortion Fin = 20 MHz 92 Fin = 80 MHz 86 Fin = 100 MHz 86 Fin = 170 MHz (all spurs/harmonics) 74 84 Fin = 170 MHz (excluding 2nd harmonic) 77 87 Fin = 300 MHz 76 Fin = 20 MHz 89 Fin = 80 MHz 83 Fin = 100 MHz Fin = 170 MHz HD2, Second harmonic distortion 73 94 Fin = 80 MHz 90 Fin = 100 MHz 76 Fin = 20 MHz 93 Fin = 80 MHz 86 Fin = 100 MHz 76 Fin = 20 MHz 96 Fin = 80 MHz 94 Fin = 100 MHz 94 80 90 F1 = 46 MHz, F2 = 50 MHz, Each tone at –7 dBFS 94 F1 = 185 MHz, F2 = 190 MHz, Each tone at –7 dBFS 90 PSRR AC power supply rejection ratio For 100-mVpp signal on AVDD supply Submit Documentation Feedback dBc dBc dBc 92 Fin = 300 MHz Recovery to within 1% (of final value) for 6-dB overload with sine wave input dBc 87 Fin = 300 MHz Input overload recovery 8 85 77 dBc 84 Fin = 300 MHz Fin = 170 MHz IMD 2-tone inter-modulation distortion 88 74 UNIT MAX 79 Fin = 20 MHz Fin = 170 MHz Worst Spur Other than second, third harmonics 82 72 Fin = 300 MHz Fin = 170 MHz HD3 Third harmonic distortion TYP dBFS 1 Clock Cycles 25 dB Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 DIGITAL CHARACTERISTICS – ADS61B49 and ADS61B29 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS61B49/ADS61B29 TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS – RESET, SCLK, SDATA, SEN (1) High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels Low-level input voltage High-level input current Low-level input current 1.3 V 0.4 SDATA, SCLK (2) VHigh = 3.3 V 16 SEN (3) VHigh = 3.3 V 10 SDATA, SCLK VLow = 0 V 0 SEN VLow = 0 V –20 Input capacitance V µA µA 4 pF V DIGITAL OUTPUTS – CMOS INTERFACE (Pins D0 to D13 and OVR_SDOUT) High-level output voltage with IOH = 1mA DRVDD DRVDD -0.1 Low-level output voltage with IOL = 1mA 0 Output capacitance (internal to device) 0.1 2 V pF DIGITAL OUTPUTS – LVDS INTERFACE (Pins D0_D1_P/M to D12_D13_P/M) (4) VODH, High-level output voltage (5) VODL, Low-level output voltage (5) VOCM, Common-mode output voltage 275 350 425 mV –425 –350 –275 mV 1 1.2 1.3 Capacitance inside the device, from either output to ground Output capacitance (1) (2) (3) (4) (5) 2 V pF SCLK, SDATA, SEN function as digital input pins in serial configuration mode. SDATA, SCLK have internal 200-kΩ pull-down resistor. SEN has internal 100-kΩ pull-up resistor to AVDD. OVR_SDOUT has CMOS output logic levels, determined by DRVDD voltage. With external 100-Ω termination Dn_Dn+1_P Dn_Dn+1_P Logic 1 Logic 0 VODL = –350 mV (1) VODH = 350 mV (1) Dn_Dn+1_M Dn_Dn+1_M V V OCM OCM GND GND T0399-01 Figure 1. LVDS Voltage Levels Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 9 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com TIMING REQUIREMENTS – LVDS AND CMOS MODES (1) Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5 pF (2), RLOAD = 100 Ω (3), Low Speed mode disabled, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.7 V to 1.9 V. PARAMETER ta Aperture delay tj Aperture jitter Wake-up time ADC Latency (4) DDR LVDS MODE TEST CONDITIONS MIN TYP MAX 0.7 1.2 1.7 170 UNIT ns fs rms Time to valid data after coming out of STANDBY mode 0.3 1 Time to valid data after coming out of PDN GLOBAL mode 25 100 Time to valid data after stopping and restarting the input clock 10 Clock Cycles Default, after reset 18 Clock Cycles 0.8 1.2 ns 0.25 0.6 ns µs (5) (6) tsu Data setup time Data valid th Data hold time Zero-crossing of CLKOUT to data becoming invalid (6) tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 100 MSPS ≤ Sampling frequency ≤ 250 MSPS tdelay to zero-crossing of CLKOUTP 0.2 × ts + tdelay 5 6.2 ns 7.5 ns LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP–CLKOUTM) 100 MSPS ≤ Sampling frequency ≤ 250 MSPS tRISE, tFALL Data rise time, Data fall time Rise time measured from –100 mV to 100 mV Fall time measured from 100 mV to –100 mV 1 MSPS ≤ Sampling frequency ≤ 250 MSPS 0.08 0.14 0.2 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from –100 mV to 100 mV Fall time measured from 100 mV to –100 mV 1 MSPS ≤ Sampling frequency ≤ 250 MSPS 0.08 0.14 0.2 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active 52% 40 ns PARALLEL CMOS MODE (7) tSTART Input clock to data delay Input clock rising edge cross-over to start of data valid (8) tDV Data valid time Time interval of valid data (8) 0.7 tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 100 MSPS ≤ Sampling frequency ≤ 150 MSPS 0.78 × ts + tdelay tdelay 3.2 5 1.5 6.5 ns ns ns 8 ns Output clock duty cycle Duty cycle of differential clock, (CLKOUT) 100 MSPS ≤ Sampling frequency ≤ 150 MSPS tRISE, tFALL Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ Sampling frequency ≤ 250 MSPS 0.7 1.2 2 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ Sampling frequency ≤ 150 MSPS 0.5 1 1.5 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active (1) (2) (3) (4) (5) (6) (7) (8) 10 50% 20 ns Timing parameters are specified by design and characterization and not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground RLOAD is the differential load resistance between the LVDS output pair. At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to logic high of +100 mV and logic low of –100 mV. For Fs > 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). Data valid refers to logic high of 1.26 V and logic low of 0.54 V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 LVDS Timings at Lower Sampling Frequencies SAMPLING FREQUENCY, MSPS SETUP TIME, ns HOLD TIME, ns MIN TYP MIN TYP 210 1.0 1.4 MAX 0.4 0.8 190 1.1 1.5 0.5 0.9 170 1.3 1.7 0.7 1.1 150 1.6 1.9 0.9 1.2 125 1.9 2.2 1.1 1.4 <100 Enable low speed mode 2.5 MAX 2.0 tPDI, ns MIN 1 ≤ Fs ≤ 100, Enable low speed mode TYP MAX 8.2 CMOS Timings at Lower Sampling Frequencies TIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK SAMPLING FREQUENCY, MSPS tSTART, ns MIN TYP DATA VALID TIME, ns MAX MIN TYP 210 1.7 1.6 2.4 190 0.4 2.2 3.0 170 5.1 2.4 3.6 150 4.8 3.0 4.3 MAX TIMINGS SPECIFIED WITH RESPECT TO CLKOUT SAMPLING FREQUENCY, MSPS SETUP TIME, ns MIN TYP 150 2.0 125 2.9 <100 Enable low speed mode 5.0 HOLD TIME, ns MAX MIN TYP 3.2 1.5 2.2 4 2.2 2.7 MAX 3.8 tPDI, ns MIN 1 ≤ Fs ≤ 100 Enable low speed mode TYP MAX 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 11 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com N+4 N+3 N+2 N+1 Sample N N+20 N+19 N+18 Input Signal ta Input Clock CLKP CLKM CLKOUTM CLKOUTP tsu Output Data DXP, DXM E E – Even Bits D0,D2,D4,... O – Odd Bits D1,D3,D5, ... O E O N–18 E O N–17 E O N–16 E tPDI th 18 Clock Cycles* DDR LVDS O E O E O E N–15 O N E E O O N+2 N+1 tPDI CLKOUT tsu Parallel CMOS 18 Clock Cycles* Output Data N–18 N–17 N–16 N–15 th N–14 N–1 N N+1 N+2 * This is the ADC latency. At higher sampling frequencies, tPDI > 1 clock cycle. Then, overall latency = ADC latency + 1. T0105-10 Figure 2. Latency Diagram 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Input Clock CLKP CLKM tPDI Output Clock CLKOUTP CLKOUTM tsu th tsu Output Data Pair (1) (2) Dn Dn_Dn+1_P, Dn_Dn+1_M th Dn (1) Dn+1 (2) – Bits D0, D2, D4,... Dn+1 – Bits D1, D3, D5, ... T0106-07 Figure 3. LVDS Mode Timing Input Clock CLKM CLKP tPDI Output Clock CLKOUT th tsu Output Data Input Clock Dn Dn* CLKM CLKP tSTART tDV Output Data Dn Dn* *Dn – Bits D0, D1, D2, ... T0107-05 Figure 4. CMOS Mode Timing Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 13 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com DEVICE CONFIGURATION The ADS61B49/29 can be configured independently using either parallel interface control or serial interface programming. PARALLEL CONFIGURATION ONLY To put the device in parallel configuration mode, keep RESET tied to high (DRVDD). Now, pins DFS, MODE, SEN, and SDATA can be used to directly control certain modes of the ADC. The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in Table 3 to Table 6). There is no need to apply reset. In this mode, SEN and SDATA function as parallel interface control pins. Frequently used functions can be controlled in this mode – standby, selection between LVDS/CMOS output formats, 2s complement/straight binary output format, and position of the output clock edge. Table 1 briefly describes the modes controlled by the parallel pins. Table 1. Parallel Pin Functions PIN TYPE OF CONTROL DFS Analog Data format and LVDS/CMOS output interface. MODE Analog In the ADS61B49/B29, external reference is not supported. Prior use of the MODE pin in the ADS6149/29 family is therefore not the same in the ADS61B49/B29 family. In the next generation pin-compatible ADC family, MODE is converted to a digital control pin for certain reserved functions. The MODE pin can be routed to a digital controller for possible future migration to a next generation ADC. SEN Analog CLKOUT edge programmability. SDATA Digital Global power down (ADC, internal references and output buffers are powered down) CONTROL MODES SERIAL INTERFACE CONFIGURATION ONLY To exercise this mode, first the serial registers have to be reset to their default values and the RESET pin has to be kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by setting the <RESET> bit (D7 in register 0x00) high. The serial interface section describes register programming and register reset in more detail. Since the parallel pin DFS is not to be used in this mode, it has to be tied to ground. 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 CONFIGURATION USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS For increased flexibility, an additional configuration mode is supported wherein a combination of serial interface registers and parallel pin control (DFS) can be used to configure the device. To exercise this mode, the serial registers have to be reset to their default values and the RESET pin has to be kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the internal registers of ADC. The registers can be reset either by applying a pulse on the RESET pin or by setting the <RESET> bit (D7 in register 0x00) high. The serial interface section describes register programming and register reset in more detail. The parallel interface control pin DFS can be used and its function is determined by the appropriate voltage levels as described in Table 3. The voltage levels can be easily derived, by using a resistor string as illustrated with an example as shown in Figure 5. Since some functions can be controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table as listed in Table 2. Table 2. Priority Between Parallel Pins and Serial Registers FUNCTION Int/ext reference - not used Data format selection LVDS or CMOS interface selection PRIORITY MODE is not used in this device (legacy from the ADS6149 and future family this pin could be redefined) DFS pin controls this selection ONLY if the register bits <DATA FORMAT> = 00, otherwise <DATA FORMAT> controls the selection DFS pin controls this selection ONLY if the register bits <LVDS CMOS> = 00, otherwise <LVDS CMOS> controls the selection DESCRIPTION OF PARALLEL PINS Table 3. SDATA – DIGITAL CONTROL PIN SDATA 0 AVDD DESCRIPTION Normal operation (default) Global power down. ADC, internal references and the output buffers are powered down. Table 4. SEN – ANALOG CONTROL PIN DESCRIPTION – OUTPUT CLOCK EDGE PROGRAMMABILITY (1) SEN 0 (3/8)AVDD LVDS: Setup time decreases by (4xTs/26), hold time increases by (4xTs/26) CMOS: Setup time increases by (9xTs/26), hold time reduces by (9xTs/26) (5/8)AVDD LVDS: Setup time increases by (4xTs/26), hold time reduces by (4xTs/26) CMOS: Setup time increases by (3xTs/26), hold time reduces by (3xTs/26) AVDD (1) LVDS: Data and output clock transitions are aligned CMOS: Setup time increases by (6xTs/26), hold time reduces by (6xTs/26) Default output clock position (setup/hold timings of output data with respect to this clock position is specified in the timing characteristics table). Ts = 1 / sampling frequency Table 5. DFS – ANALOG CONTROL PIN DFS 0 DESCRIPTION 2s complement data and DDR LVDS output (3/8)AVDD 2s complement data and parallel CMOS output (5/8)AVDD Offset binary data and parallel CMOS output AVDD Offset binary data and DDR LVDS output Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 15 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com Table 6. MODE – ANALOG CONTROL PIN MODE DESCRIPTION Not used In the ADS61B49/B29, external reference is not supported. The prior use of the MODE pin in ADS6149/29 family is therefore not the same in the ADS61B49/B29 family. In the next generation pin-compatible ADC family, MODE could be converted to a digital control pin for certain reserved functions. The MODE pin can be routed to a digital controller for possible future migration to a next generation ADC. AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD (3/8) AVDD 3R To Parallel Pin GND S0321-01 Figure 5. Simple Scheme to Configure Parallel Pins SEN and SCLK SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first 8 bits form the register address, and the remaining 8 bits are the register data. The interface can work with a SCLK frequency from 20 MHz down to very low speeds (few hertz) and also with a non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on the RESET pin (of width greater than 10 ns) as shown in Figure 6. OR 2. By applying a software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to high. This initializes the internal registers to their default values and then self-resets the <RESET> bit to low. In this case the RESET pin is kept low. 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Register Data Register Address SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-01 Figure 6. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V, unless otherwise noted. PARAMETER MIN > dc TYP MAX UNIT 20 MHz fSCLK SCLK frequency (= 1/ tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns SERIAL REGISTER READOUT The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. a. First, set register bit <SERIAL READOUT> = 1. This also disables any further writes into the registers (EXCEPT register bit <SERIAL READOUT> itself). b. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. c. The device outputs the contents (D7-D0) of the selected register on the OVR_SDOUT pin. d. The external controller can latch the contents at the falling edge of SCLK. e. To enable register writes, reset register bit <SERIAL READOUT> = 0. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 17 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com A) Enable serial readout (<SERIAL READOUT> = 1) Register Data (D7:D0) = 0x01 Register Address (A7:A0) = 0x00 SDATA 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN Pin OVR_SDOUT functions as OVR (<SERIAL READOUT> = 0) OVR_SDOUT B) Read contents of register 0x3F. This register has been initialized with 0x04 (device is put in global power down mode) Register Data (D7:D0) = XX (Don't Care) Register Address (A7:A0) = 0x3F SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 SCLK SEN OVR_SDOUT Pin OVR_SDOUT functions as serial readout (<SERIAL READOUT> = 1) T0386-01 Figure 7. Serial Readout 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise noted. PARAMETER t1 TEST CONDITIONS Power-on delay time MIN TYP Delay from power-up of AVDD and DRVDD to RESET pulse active t2 Reset pulse width Pulse width of active RESET signal that resets the serial registers t3 Delay time Delay from RESET disable to SEN active MAX UNIT 1 ms 10 ns µs 1 100 ns Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN T0108-01 Figure 8. Reset Timing Diagram SERIAL REGISTER MAP Table 7. Summary of Functions Supported by Serial Interface (1) REGISTER ADDRESS REGISTER FUNCTIONS A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 <RESET> Software Reset 0 0 0 0 0 0 <SERIAL READOUT> 20 0 0 0 0 0 <ENABLE LOW SPEED MODE> 0 0 3F 0 0 0 <PDN GLOBAL> <STANDBY> <PDN OBUF> 0 0 0 0 0 0 0 <LVDS CMOS> Output interface 41 0 0 52 0 0 53 0 <ENABLE OFFSET CORR> 51 0 0 0 <DATA FORMAT> 2s complement or offset binary 0 <CUSTOM PATTERN LOW> 55 (1) 0 <CLKOUT POSN> Output clock position control 44 50 <REF> (RESERVED) <CUSTOM PATTERN HIGH> 0 0 0 0 0 63 0 0 0 0 <OFFSET CORR TIME CONSTANT> Offset correction time constant <FINE GAIN > 62 0 0 0 0 <TEST PATTERNS> <PROGRAM OFFSET PEDESTAL > Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 19 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com DESCRIPTION OF SERIAL REGISTERS A) A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 <RESET> Software Reset 0 0 0 0 0 0 <SERIAL READOUT> D7 <RESET> 1 Software reset applied – resets all internal registers and self-clears to 0. D0 <SERIAL READOUT> 0 Serial readout disabled 1 Serial readout enabled, pin OVR_SDOUT functions as serial data readout. B) A7–A0 IN HEX 20 D2 D7 D6 0 D5 0 0 D4 D3 D2 D1 D0 0 <ENABLE LOW SPEED MODE> 0 0 D3 D2 D1 D0 0 <PDN GLOBAL> <STANDBY> <PDN OBUF> 0 <ENABLE LOW SPEED MODE> 0 Low speed mode disabled. Use for sampling frequency > 100 MSPS 1 Enable low speed mode for sampling frequencies ≤ 100 MSPS. C) A7–A0 IN HEX 3F D6,D5 D7 0 D6 D5 <REF>(RESERVED) D4 0 <REF> RESERVED (Not used) In the ADS61B49/61B29, external reference mode is not supported. See ADS6149/6129 non-buffered ADCs if an external reference is required. This register controls the reference mode in those devices. D2 <PDN GLOBAL> 0 Normal operation 1 Total power down – ADC, internal references and output buffers are powered down. Slow wake-up time. D1 <STANDBY> 0 Normal operation 1 ADC alone powered down. Internal references, output buffers are active. Quick wake-up time D0 <PDN OBUF> Power down output buffer 0 Output buffer enabled 1 Output buffer powered down D) A7–A0 IN HEX 41 D7,D6 D7 D6 <LVDS CMOS> D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D4 D3 D2 D1 D0 0 0 <LVDS CMOS> 00 DFS pin controls LVDS or CMOS interface selection 10 DDR LVDS interface 11 Parallel CMOS interface E) A7–A0 IN HEX 44 20 D7 D6 D5 CLKOUT POSN> Output clock position control Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 LVDS Interface D7-D5 <CLKOUT POSN> Output clock rising edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by + (4/26)Ts 110 Rising edge aligned with data transition 111 Rising edge shifted by - (4/26)Ts D4-D2 <CLKOUT POSN> Output clock falling edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by + (4/26)Ts 110 Falling edge aligned with data transition 111 Falling edge shifted by - (4/26)Ts CMOS Interface D7-D5 <CLKOUT POSN> Output clock rising edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by + (4/26)Ts 110 Rising edge shifted by + (6/26)Ts 111 Rising edge aligned with data transition D4-D2 <CLKOUT POSN> Output clock falling edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by + (4/26)Ts 110 Falling edge shifted by + (6/26)Ts 111 Falling edge aligned with data transition F) A7–A0 IN HEX D7 D6 D5 D4 D3 50 0 0 0 0 0 D5 D4 D2,D1 D2 D1 <DATA FORMAT> 2s complement or offset binary D0 0 <DATA FORMAT> 00 DFS pin controls data format selection 10 2s complement 11 Offset binary G) A7–A0 IN HEX D7 D6 51 52 D7–D0 D3 D2 D1 D0 <Custom LOW> <Custom HIGH> <CUSTOM LOW> 8 lower bits of custom pattern available at the output instead of ADC data. D5–D0 <CUSTOM HIGH> 6 upper bits of custom pattern available at the output instead of ADC data Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 21 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com H) A7–A0 IN HEX 53 D6 D7 D6 D5 D4 D3 D2 D1 D0 0 <ENABLE OFFSET CORR> Offset correction enable 0 0 0 0 0 0 <ENABLE OFFSET CORR> 0 Offset correction disabled 1 Offset correction enabled I) A7–A0 IN HEX D7 55 D7–D4 D6 <FINE GAIN> D4 D3 D2 D1 D0 <OFFSET CORR TC> Offset correction time constant <FINE GAIN> Gain programmability in 0.5-dB steps 0000 0-dB gain, default after reset 0001 0.5-dB gain 0010 1.0-dB gain 0011 1.5-dB gain 0100 2.0-dB gain 0101 2.5-dB gain 0110 3.0-dB gain 0111 3.5-dB gain 1000 4.0-dB gain 1001 4.5-dB gain 1010 5.0-dB gain 1011 5.5-dB gain 1100 6.0-dB gain D3–D0 D5 <OFFSET CORR TC> Time constant of correction loop in number of clock cycles. See Offset Correction in application section. 0000 256 k 0001 512 k 0010 1M 0011 2M 0100 4M 0101 8M 0110 16 M 0111 32 M 1000 64 M 1001 128 M 1010 256 M 1011 512 M 1100 to 1111 Reserved 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 J) A7–A0 IN HEX D7 D6 D5 D4 D3 62 0 0 0 0 0 D2–D0 D2 D1 D0 <TEST PATTERNS> <TEST PATTERNS> Test patterns to verify data capture 000 Normal operation 001 Outputs all zeros 010 Outputs all ones 011 Outputs toggle pattern 100 Outputs digital ramp 101 Outputs custom pattern 110 Unused 111 Unused K) A7–A0 IN HEX D7 D6 63 0 0 D5–D0 D5 D4 D3 D2 D1 D0 <OFFSET PEDESTAL> <OFFSET PEDESTAL> When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. For example, See Offset Correction in application section. 011111 Mid-code + 31 LSB 011110 Mid-code + 30 LSB 011101 Mid-code + 29 LSB .... 000000 Mid-code 111111 Mid-code - 1 LSB 111110 Mid-code - 2 LSB .... 100000 Mid-code - 32 LSB Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 23 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com D12_D13_M D10_D11_P D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M 47 45 44 43 42 41 40 39 38 37 1 46 DRGND 48 D12_D13_P DEVICE INFORMATION Pad is connected to DRGND 36 DRGND 35 DRVDD DRVDD 2 OVR_SDOUT 3 34 D0_D1_P CLKOUTM 4 33 D0_D1_M CLKOUTP 5 32 NC DFS 6 31 NC Thermal Pad 22 23 24 AVDD MODE AVDD 21 NC AGND 20 AVDD 25 AVDD 26 12 18 11 19 CLKM AGND AVDD SEN AGND 27 17 10 AGND CLKP 16 SDATA INM SCLK 28 14 29 9 15 AVDD AGND INP RESET AGND 30 8 13 7 VCM OE P0023-12 D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M D0_D1_P D0_D1_M 47 45 44 43 42 41 40 39 38 37 1 46 DRGND 48 D10_D11_P Figure 9. PIN CONFIGURATION (LVDS MODE) — ADS61B49 Pad is connected to DRGND 36 DRGND 35 DRVDD DRVDD 2 OVR_SDOUT 3 34 NC CLKOUTM 4 33 NC CLKOUTP 5 32 NC DFS 6 31 NC Thermal Pad OE 7 30 RESET 22 23 24 AVDD AVDD 21 NC MODE 20 AVDD AGND 18 AGND 19 AVDD 25 AVDD 26 12 AGND 11 17 CLKM AGND SEN 16 27 INM 10 14 CLKP 15 SDATA INP SCLK 28 AGND 29 9 13 8 VCM AVDD AGND P0023-13 Figure 10. PIN CONFIGURATION (LVDS MODE) — ADS61B29 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS61B49 and ADS61B29 PIN NAME NO. I/O NO. of PINS DESCRIPTION AVDD 8, 18, 20, 22, 24, 26 I 6 3.3-V analog power supply AGND 9, 12, 14, 17, 19, 25 I 6 Analog ground CLKP, CLKM 10, 11 I 2 Differential clock input INP, INM 15, 16 I 2 Differential analog input 13 IO 1 Internal reference mode – Common-mode voltage output. VCM External reference mode – Reference input. The voltage forced on this pin sets the internal references. Serial interface RESET input. RESET 30 I 1 SCLK 29 I 1 When using serial interface mode, the user MUST initialize the internal registers through a hardware RESET by applying a high-going pulse on this pin or by using the software reset option. Refer to the SERIAL INTERFACE section. In parallel interface mode, the user has to tie the RESET pin permanently high. (SDATA and SEN are used as parallel pin controls in this mode.) The pin has an internal 100-kΩ pull-down resistor. Serial interface clock input. The pin has an internal 100-kΩ pull-down resistor. This pin functions as the serial interface data input when RESET is low. It functions as the power-down control pin when RESET is tied high. SDATA 28 I 1 See Table 3 for detailed information. The pin has an internal 100-kΩ pull-down resistor. This pin functions as the serial interface enable input when RESET is low. It functions as the output clock edge control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100-kΩ pull-up resistor to AVDD. SEN 27 I 1 OE 7 I 1 Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up resistor to DRVDD DFS 8 I 1 Data format select input. This pin sets the data format (2s complement or offset binary) and the LVDS/CMOS output interface type. MODE (1) 23 I 1 Not used. See Table 6 and note below for detailed information. CLKOUTP 5 O 1 Differential output clock, true CLKOUTM 4 O 1 Differential output clock, complement D0_D1_P O 1 Differential output data D0 and D1 multiplexed, true D0_D1_M O 1 Differential output data D0 and D1 multiplexed, complement D2_D3_P O 1 Differential output data D2 and D3 multiplexed, true D2_D3_M O 1 Differential output data D2 and D3 multiplexed, complement D4_D5_P O 1 Differential output data D4 and D5 multiplexed, true D4_D5_M O 1 Differential output data D4 and D5 multiplexed, complement O 1 Differential output data D6 and D7 multiplexed, true O 1 Differential output data D6 and D7 multiplexed, complement O 1 Differential output data D8 and D9 multiplexed, true D8_D9_M O 1 Differential output data D8 and D9 multiplexed, complement D10_D11_P O 1 Differential output data D10 and D11 multiplexed, true D10_D11_M O 1 Differential output data D10 and D11 multiplexed, complement D12_D13_P O 1 Differential output data D12 and D13 multiplexed, true D12_D13_M O 1 Differential output data D12 and D13 multiplexed, complement 3 O 1 It is a CMOS output with logic levels determined by the DRVDD supply. It functions as an out-of-range indicator after a reset and when register bit <SERIAL READOUT> = 0. It functions as the serial register readout pin when register bit <SERIAL READOUT> = 1. DRVDD 2, 35 I 2 1.8-V digital and output buffer supply DRGND 1, 36, PAD I 2 Digital and output buffer ground See Table 5 for detailed information. D6_D7_P D6_D7_M D8_D9_P OVR_SDOUT (1) See Figure 9 and Figure 10 In the next generation pin-compatible ADC family, MODE is converted to a digital control pin for certain reserved functions. So, the selection of the internal or external reference and low speed functions are supported using MODE. In a system board using the ADS61x9/x8, the MODE pin can be routed to a digital controller. This avoids board modification if migrating to the next generation ADC. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 25 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS61B49 and ADS61B29 (continued) PIN NAME NC 26 NO. See Figure 9 and Figure 10 I/O NO. of PINS DESCRIPTION Do not connect Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 46 45 44 43 42 41 40 39 38 37 D13 1 48 DRGND 47 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Pad is connected to DRGND 36 DRGND 35 DRVDD DRVDD 2 OVR_SDOUT 3 34 D1 UNUSED 4 33 D0 CLKOUT 5 32 NC DFS 6 31 NC Thermal Pad 22 23 24 MODE AVDD AGND AVDD 25 21 12 NC AGND 20 AVDD AVDD SEN 26 18 27 11 19 CLKP CLKM AVDD SDATA AGND 28 10 17 9 AGND AGND 16 SCLK INM 29 15 8 INP AVDD 13 RESET 14 30 VCM 7 AGND OE P0023-14 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 46 45 44 43 42 41 40 39 38 37 D11 1 48 DRGND 47 Figure 11. PIN CONFIGURATION (CMOS MODE) – ADS61B49 Pad is connected to DRGND 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC UNUSED 4 33 NC CLKOUT 5 32 NC DFS 6 31 NC Thermal Pad 23 24 MODE AVDD AGND 22 25 AVDD 12 21 AGND NC AVDD 20 26 AVDD 11 18 CLKM 19 SEN AVDD 27 AGND 10 17 CLKP AGND SDATA 16 28 INM 9 15 AGND INP SCLK 13 RESET 29 14 30 8 VCM 7 AGND OE AVDD P0023-15 Figure 12. PIN CONFIGURATION (CMOS MODE) – ADS61B29 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 27 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com PIN ASSIGNMENTS (CMOS MODE) – ADS61B49 and ADS61B29 PIN NAME NO. I/O NO. of PINS DESCRIPTION AVDD 8, 18, 20, 22, 24, 26 I 6 3.3-V analog power supply AGND 9, 12, 14, 17, 19, 25 I 6 Analog ground CLKP, CLKM 10, 11 I 2 Differential clock input INP, INM 15, 16 I 2 Differential analog input 13 IO 1 Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the internal references. VCM RESET 30 I 1 Serial interface RESET input. When using serial interface mode, the user MUST initialize the internal registers through a hardware RESET by applying a high-going pulse on this pin or by using the software reset option. Refer to the SERIAL INTERFACE section. In parallel interface mode, the user has to tie the RESET pin permanently high. (SDATA and SEN are used as parallel pin controls in this mode.) The pin has an internal 100-kΩ pull-down resistor. SCLK 29 I 1 Serial interface clock input. The pin has an internal 100-kΩ pull-down resistor. 1 This pin functions as the serial interface data input when RESET is low. It functions as the power-down control pin when RESET is tied high. See Table 3 for detailed information. The pin has an internal 100-kΩ pull-down resistor. SDATA 28 I SEN 27 I 1 This pin functions as the serial interface enable input when RESET is low. It functions as the output clock edge control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100-kΩ pull-up resistor to DVDD. DFS 8 I 1 Data format select input. This pin sets the data format (2s complement or offset binary) and the LVDS/CMOS output interface type. See Table 5 for detailed information. MODE (1) 23 I 1 Not used. See Table 6 and note below for detailed information. CLKOUT 5 O 1 CMOS output clock OE 7 I 1 Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up resistor to DRVDD See Figure 11 and Figure 12 O 14/12 3 O 1 It is a CMOS output with logic levels determined by the DRVDD supply. It functions as an out-of-range indicator after a reset and when register bit <SERIAL READOUT> = 0. It functions as the serial register readout pin when <SERIAL READOUT> = 1. DRVDD 2, 35 I 2 1.8-V digital and output buffer supply DRGND 1, 36, PAD I 2 Digital and output buffer ground 1 Unused pin in CMOS mode D0–D13 OVR_SDOUT UNUSED NC (1) 28 4 See Figure 11 and Figure 12 14-bit/12-bit CMOS output data Do not connect In the next generation pin-compatible ADC family, MODE is converted to a digital control pin for certain reserved functions. So, the selection of the internal or external reference and low speed functions are supported using MODE. In a system board using the ADS61x9/x8, the MODE pin can be routed to a digital controller. This avoids board modification while migrating to the next generation ADC. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS - ADS61B49 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 65 MHz INPUT SIGNAL 0 0 SFDR = 91.5 dBc SINAD = 72.5 dBFS SNR = 72.6 dBFS THD = 86.8 dBc −20 Amplitude − dB Amplitude − dB −20 SFDR = 88.9 dBc SINAD = 72.1 dBFS SNR = 72.2 dBFS THD = 84.9 dBc −40 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 f − Frequency − MHz 125 0 25 G001 Figure 13. FFT for 170 MHz INPUT SIGNAL 100 125 G002 FFT for 300 MHz INPUT SIGNAL 0 SFDR = 80.3 dBc SINAD = 70.2 dBFS SNR = 70.7 dBFS THD = 79.2 dBc SFDR = 75.7 dBc SINAD = 67.2 dBFS SNR = 68.4 dBFS THD = 72.4 dBc −20 Amplitude − dB −20 Amplitude − dB 75 Figure 14. 0 −40 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 f − Frequency − MHz 125 0 25 G003 75 100 125 G004 Figure 16. FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD) 0 0 fIN1 = 190 MHz, –7 dBFS fIN2 = 185 MHz, –7 dBFS 2-Tone IMD = –90 dBFS SFDR = –95 dBFS fIN1 = 190.1 MHz, –36 dBFS fIN2 = 185.1 MHz, –36 dBFS 2-Tone IMD = –112 dBFS SFDR = –99 dBFS −20 Amplitude − dB −20 50 f − Frequency − MHz Figure 15. Amplitude − dB 50 f − Frequency − MHz −40 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 f − Frequency − MHz 100 125 0 25 G005 Figure 17. 50 75 100 f − Frequency − MHz 125 G006 Figure 18. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 29 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS61B49 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 100 Gain = 0 dB Gain = 0 dB 95 92 90 88 85 SNR − dBFS SFDR − dBc 96 84 80 76 80 75 70 72 65 68 60 64 55 60 50 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G007 Figure 19. Figure 20. SFDR vs INPUT FREQUENCY and INTERNAL GAIN SINAD vs INPUT FREQUENCY and INTERNAL GAIN 95 74 Input adjusted to get −1dBFS input 1 dB 72 2 dB 90 6 dB 85 4 dB 3 dB 80 75 0 dB Input adjusted to get −1dBFS input 2 dB 5 dB SINAD − dBFS SFDR − dBc G008 3 dB 70 0 dB 68 66 1 dB 4 dB 64 5 dB 6 dB 70 62 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 G009 Figure 21. 30 fIN − Input Frequency − MHz G010 Figure 22. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS - ADS61B49 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 85 92 76 fIN = 65 MHz External Reference Mode SFDR (dBFS) 75 SNR (dBFS) 60 70 40 65 SFDR (dBc) 20 88 2.10 2.15 2.20 2.25 2.30 2.35 71 2.40 VCM − Common-Mode Voltage − V G011 G012 Figure 24. SFDR vs TEMPERATURE and AVDD SFDR vs TEMPERATURE and DRVDD 95 DRVDD = 1.8 V fIN = 65 MHz AVDD = 3.6 V 91 93 AVDD = 3.3 V fIN = 65 MHz AVDD = 3.5 V 89 SFDR − dBc SFDR − dBc 2.05 Figure 23. 93 87 85 AVDD = 3.3 V AVDD = 3.4 V 81 AVDD = 3.2 V 79 75 −40 72 82 2.00 95 77 73 SNR 84 fIN = 65 MHz 0 55 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 83 74 86 60 Input Amplitude − dBFS 75 SFDR SFDR − dBc 80 90 SNR − dBFS 80 SFDR − dBc, dBFS 100 SNR − dBFS 120 AVDD = 3 V −20 DRVDD = 1.9 V 91 DRVDD = 2 V 89 87 DRVDD = 1.7 V AVDD = 3.1 V 0 20 DRVDD = 1.8 V 40 60 TA − Free-Air Temperature − °C 85 −40 80 −20 G013 Figure 25. 0 20 40 60 80 TA − Free-Air Temperature − °C G014 Figure 26. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 31 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS61B49 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SNR vs TEMPERATURE and AVDD SNR vs TEMPERATURE and DRVDD 73.0 74.0 AVDD = 3.6 V AVDD = 3.3 V, AVDD = 3.5 V AVDD = 3.3 V fIN = 65 MHz 73.5 SNR − dBFS SNR − dBFS 72.5 AVDD = 3 V 72.0 AVDD = 3.1 V DRVDD = 1.7 V 73.0 DRVDD = 1.8 V 72.5 72.0 71.5 AVDD = 3.2 V, AVDD = 3.4 V DRVDD = 1.8 V fIN = 65 MHz 71.0 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 71.0 −40 80 G015 20 40 60 PERFORMANCE vs INPUT CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK DUTY CYCLE 78 fIN = 65 MHz 80 G016 96 74 fIN = 65 MHz 77 92 73 SFDR 86 74 84 73 SNR 82 72 80 71 0.5 1.0 1.5 88 72 84 71 SNR 80 70 76 69 72 70 2.0 Input Clock Amplitude − VPP SFDR − dBc 75 SNR − dBFS 88 SNR − dBFS 76 SFDR SFDR − dBc 0 TA − Free-Air Temperature − °C Figure 28. 90 78 0.0 −20 Figure 27. 94 92 DRVDD = 1.9 V, DRVDD = 2 V 71.5 68 35 40 G017 45 50 55 Input Clock Duty Cycle − % Figure 29. 60 65 G018 Figure 30. OUTPUT NOISE HISTOGRAM 40 RMS (LSB) = 1.179 35 Occurence − % 30 25 20 15 10 5 0 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 Output Code G019 Figure 31. 32 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS - ADS61B29 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 65 MHz INPUT SIGNAL 0 0 SFDR = 91.9 dBc SINAD = 70.3 dBFS SNR = 70.3 dBFS THD = 86.9 dBc −20 Amplitude − dB Amplitude − dB −20 SFDR = 88.7 dBc SINAD = 70 dBFS SNR = 70.1 dBFS THD = 84.8 dBc −40 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 f − Frequency − MHz 125 0 25 G020 Figure 32. FFT for 170 MHz INPUT SIGNAL 100 125 G021 FFT for 300 MHz INPUT SIGNAL 0 SFDR = 80.1 dBc SINAD = 68.8 dBFS SNR = 69.1 dBFS THD = 79 dBc SFDR = 75.7 dBc SINAD = 66.4 dBFS SNR = 67.4 dBFS THD = 72.3 dBc −20 Amplitude − dB −20 Amplitude − dB 75 Figure 33. 0 −40 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 f − Frequency − MHz 125 0 25 G022 75 100 125 G023 Figure 35. FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD) 0 0 fIN1 = 190.1 MHz, –7 dBFS fIN2 = 185.1 MHz, –7 dBFS 2-Tone IMD = –89.7 dBFS SFDR = –96 dBFS fIN1 = 190.1 MHz, –36 dBFS fIN2 = 185.1 MHz, –36 dBFS 2-Tone IMD = –110 dBFS SFDR = –99 dBFS −20 Amplitude − dB −20 50 f − Frequency − MHz Figure 34. Amplitude − dB 50 f − Frequency − MHz −40 −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 f − Frequency − MHz 100 125 0 25 G024 Figure 36. 50 75 100 f − Frequency − MHz 125 G025 Figure 37. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 33 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS61B29 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 100 Gain = 0 dB Gain = 0 dB 95 92 90 88 85 SNR − dBFS SFDR − dBc 96 84 80 76 80 75 70 72 65 68 60 64 55 60 50 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G026 Figure 38. Figure 39. SFDR vs INPUT FREQUENCY and INTERNAL GAIN SINAD vs INPUT FREQUENCY and INTERNAL GAIN 95 74 Input adjusted to get −1dBFS input Input adjusted to get −1dBFS input 2 dB 90 0 dB 72 5 dB 1 dB 3 dB SINAD − dBFS SFDR − dBc G027 6 dB 85 4 dB 80 0 dB 75 1 dB 2 dB 70 3 dB 68 66 4 dB 64 5 dB 6 dB 70 62 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 G028 Figure 40. 34 fIN − Input Frequency − MHz G029 Figure 41. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS - ADS61B29 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 120 92 85 74 fIN = 65 MHz External Reference Mode SFDR (dBFS) SNR (dBFS) 60 70 40 73 SFDR 88 SNR − dBFS 75 SFDR − dBc 80 90 SNR − dBFS 80 SFDR − dBc, dBFS 100 72 86 71 SNR 65 84 60 82 2.00 70 SFDR (dBc) 20 −60 fIN = 65 MHz −50 −40 −30 −20 −10 0 Input Amplitude − dBFS 2.15 2.20 2.25 2.30 2.35 69 2.40 VCM − Common-Mode Voltage − V G030 G031 Figure 43. SFDR vs TEMPERATURE and AVDD SFDR vs TEMPERATURE and DRVDD 95 AVDD = 3.5 V 91 DRVDD = 1.8 V AVDD = 3.4 Vf = 65 MHz IN 93 AVDD = 3.3 V fIN = 65 MHz AVDD = 3.6 V 89 DRVDD = 1.9 V SFDR − dBc SFDR − dBc 2.10 Figure 42. 95 93 2.05 87 85 83 AVDD = 3.3 V 91 DRVDD = 2 V 89 81 79 AVDD = 3.2 V 77 75 −40 87 AVDD = 3 V DRVDD = 1.7 V DRVDD = 1.8 V AVDD = 3.1 V −20 0 20 40 60 TA − Free-Air Temperature − °C 85 −40 80 −20 G032 Figure 44. 0 20 40 60 80 TA − Free-Air Temperature − °C G033 Figure 45. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 35 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS61B29 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) SNR vs TEMPERATURE and AVDD SNR vs TEMPERATURE and DRVDD 71.0 71.0 70.0 AVDD = 3 V AVDD = 3.2 V 69.5 DRVDD = 1.8 V 70.5 SNR − dBFS 70.5 SNR − dBFS AVDD = 3.3 V fIN = 65 MHz AVDD = 3.1 V, AVDD = 3.3 V, AVDD = 3.4 V, AVDD = 3.5 V, AVDD = 3.6 V 70.0 DRVDD = 1.7 V, DRVDD = 1.9 V 69.5 DRVDD = 2 V DRVDD = 1.8 V fIN = 65 MHz −20 0 20 40 60 TA − Free-Air Temperature − °C 20 40 60 PERFORMANCE vs INPUT CLOCK AMPLITUDE PERFORMANCE vs INPUT CLOCK DUTY CYCLE fIN = 65 MHz 92 72 SFDR 86 72 71 SNR 82 70 80 69 1.0 1.5 68 2.0 Input Clock Amplitude − VPP SFDR − dBc 73 84 73 74 88 G035 fIN = 65 MHz 75 SFDR 80 96 SNR − dBFS SFDR − dBc G034 76 0.5 0 TA − Free-Air Temperature − °C Figure 47. 90 78 0.0 −20 Figure 46. 94 92 69.0 −40 80 88 71 84 70 SNR 80 69 76 68 72 SNR − dBFS 69.0 −40 67 35 40 G036 45 50 55 Input Clock Duty Cycle − % Figure 48. 60 65 G037 Figure 49. OUTPUT NOISE HISTOGRAM 100 90 RMS (LSB) = 0.3 Occurence − % 80 70 60 50 40 30 20 10 0 2051 2052 2053 2054 2055 2056 2057 2058 2059 Output Code G038 Figure 50. 36 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS - COMMON PLOTS (Both ADS61B49/61B29) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) CMRR vs INPUT FREQUENCY FFT SHOWING EFFECTS OF COMMON-MODE SIGNAL 0 0 −10 fIN = 65 MHz fCM = 40 MHz, 140 mVpp HD3 = 86 dBc SNR = 68.1 dBFS −20 Amplitude − dB CMRR − dB −20 −30 −40 −50 SINAD = 67.8 dBFS THD = 82 dBc Amp (fCM) = 86.5 dBFS Amp (fIN + fCM) = 74.5 dBFS Amp (fIN − fCM) = 72.3 dBFS −40 fIN − fCM −60 fIN + fCM fCM HD3 −80 −60 −100 −70 −80 −120 0 50 100 150 200 250 300 0 50 75 100 125 f − Frequency − MHz fIN − Input Frequency − Hz G042 G039 Figure 51. Figure 52. TOTAL POWER vs SAMPLING FREQUENCY DRVDD CURRENT vs SAMPLING FREQUENCY 1.0 100 IDRVDD − DRVDD Current − mA 0.9 CMOS CL = 10 pF 0.8 P − Total Power − W 25 0.7 LVDS 0.6 0.5 0.4 CMOS CL = 0 pF 0.3 0.2 0.1 fIN = 3 MHz 90 80 CMOS CL = 10 pF 70 LVDS 60 50 40 30 20 CMOS CL = 0 pF 10 0.0 0 0 50 100 150 200 fS − Sampling Frequency − MSPS 250 0 50 G040 Figure 53. 100 150 200 250 fS − Sampling Frequency − MSPS G041 Figure 54. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 37 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com CONTOUR PLOTS - ADS61B49/ADS61B29 Plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) 250 74 240 90 82 74 200 180 66 86 220 fS - Sampling Frequency - MSPS 70 78 70 90 82 160 66 78 74 86 140 120 90 70 78 66 100 82 86 80 20 50 100 74 200 150 250 350 300 400 500 450 fIN - Input Frequency - MHz 70 65 75 80 85 90 SFDR - dBc M0049-22 Figure 55. SFDR Contour Plot (0-dB gain) 250 88 240 85 88 79 82 76 85 fS - Sampling Frequency - MSPS 220 200 76 85 180 73 85 88 82 160 88 79 85 76 140 82 120 79 91 88 100 85 80 20 50 100 150 200 250 73 76 300 350 400 450 500 fIN - Input Frequency - MHz 70 75 80 85 90 SFDR - dBc M0049-23 Figure 56. SFDR Contour Plot (6-dB gain) 38 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 CONTOUR PLOTS - ADS61B49 Plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) 250 240 72 220 fS - Sampling Frequency - MSPS 69 70 66 67 68 71 200 69 67 180 160 65 68 70 72 66 71 140 120 69 67 73 68 100 72 80 20 50 100 71 70 150 200 250 350 300 65 66 400 500 450 fIN - Input Frequency - MHz 64 62 66 68 70 72 74 SNR - dBFS M0048-22 Figure 57. SNR Contour Plot (0-dB gain) 250 240 66.5 66 fS - Sampling Frequency - MSPS 65 65.5 220 64 64.5 200 180 65.5 66 66.5 160 64 64.5 67 65 140 120 64 66.5 100 67 80 20 50 66 100 200 150 250 300 64.5 65 65.5 350 400 450 500 fIN - Input Frequency - MHz 62 63 64 65 66 SNR - dBFS 67 68 M0048-23 Figure 58. SNR Contour Plot (6-dB gain) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 39 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com CONTOUR PLOTS - ADS61B29 Plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sine wave input clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0-dB gain, LVDS output interface (unless otherwise noted) 250 240 69.5 69 67.5 68.5 70 65.5 65 68 220 fS - Sampling Frequency - MSPS 66 66.5 67 200 180 69.5 160 66 66.5 69 70.5 68.5 70 67.5 68 64.5 67 65 65.5 140 120 69.5 100 80 20 70.5 70 50 69 100 68 68.5 200 150 67.5 250 67 66.5 66 350 300 65 65.5 400 64.5 500 450 fIN - Input Frequency - MHz 65 64 66 68 67 69 70 71 SNR - dBFS M0048-24 Figure 59. SNR Contour Plot (0-dB gain) 250 240 65.5 65 64 66 64.5 fS - Sampling Frequency - MSPS 220 63.5 200 180 66 64 64.5 65 65.5 160 66.5 140 120 63.5 65.5 66 66.5 65 100 64 64.5 80 20 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz 62 63 65 64 66 SNR - dBFS 67 M0048-25 Figure 60. SNR Contour Plot (6-dB gain) 40 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 APPLICATION INFORMATION THEORY OF OPERATION The ADS61B49/29 are high performance, low power 14-bit and 12-bit A/D converters with maximum sampling rates up to 250 MSPS. The primary difference from the ADS6149/29 is the addition of an integrated analog buffer (hence B in the device name). The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline resulting in a data latency of 18 clock cycles. The output is available as 14-bit/12-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2s complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with 2-Vpp amplitude) and about 800MHz (with 1-Vpp amplitude) before the performance becomes ill-behaved. This is separate from the full power analog bandwidth of 750MHz, which is only an indicator of signal amplitude versus frequency. ANALOG INPUT The analog input consists of an integrated input buffer followed by a switched-capacitor based differential sample and hold architecture. The addition of a buffer provides isolation from the non-linear impedance and switching transients of the switched-capacitor circuit. With a constant input impedance, the ADC is easier to drive and to reproduce data sheet measurements. For wide-band applications, like power amplifier linearization, the signal gain across frequency is more consistent. Spectral performance variance across frequency is also reduced. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 2.3 V, available on the VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM+ 0.5 V and VCM – 0.5 V, resulting in a 2-Vpp differential input swing. Lpkg » 1 nH 5W Buffer INP Cbond » 1 pF Ceq Buf Resr » 100 W Req Buf 5 kW 2.3 V 5 kW Lpkg » 1 nH Sample and Hold Req Buf Ceq Buf 5W INM Cbond » 1 pF Buffer Resr » 100 W Ceq Buf (Equivalent Input Capacitance of the Buffer) = 3 pF Req Buf » 10 W No Capacitance Shown for Soldered-Down Package, Typically 1 pF–2 pF to Ground S0384-01 Figure 61. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 750 MHz (measured from the input pins to the sampled voltage). Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 41 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended to dampen out ringing caused by package parasitics. Due to the integrated high impedance buffer in the ADS61B49/29 family, the filtering of the glitches with an external R-C-R filter suggested for the ADS6149/29 family is not required. The drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 62 and Figure 63 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins. These figures compare the buffered ADS61B49 to the non-buffered ADS6149. RIN − Input Resistance − kΩ 100 10 ADS61B49 1 0.1 ADS6149 0.01 0 100 200 300 400 500 600 700 800 900 1000 f − Frequency − MHz G081 Figure 62. ADC Analog Input Resistance Across Frequency 4.5 CIN − Input Capacitance − pF 4.0 3.5 ADS6149 3.0 2.5 2.0 1.5 ADS61B49 1.0 0.5 0.0 0 100 200 300 400 500 600 700 800 900 1000 f − Frequency − MHz G082 Figure 63. ADC Analog Input Capacitance Across Frequency 42 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Driving Circuit Two example driving circuit configurations are shown in Figure 64 and Figure 65 – one optimized for low input frequencies and the other for high input frequencies. Notice in both cases that the board circuitry is simplified compared to the non-buffered ADS6149. In Figure 64, a single transformer is used and is suited for low input frequencies and works for some high frequency applications as well. To optimize even-harmonic performance at high input frequencies (> 2nd Nyquist), the use of back-to-back transformers is recommended (see Figure 65). Note that both drive circuits have been terminated by 50-Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. ADS61Bx9 0.1 mF 5W INP 0.1 mF 25 W 25 W INM 5W 1:1 S0381-01 Figure 64. Drive Circuit for Low Frequencies The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional termination resistor pair may be required between the two transformers as shown in the figures. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side have to be chosen to achieve an effective 50 Ω (in the case of 50-Ω source impedance). ADS61Bx9 0.1 mF 5W INP 50 W 0.1 mF 50 W 50 W 50 W INM 1:1 1:1 5W S0382-01 Figure 65. Drive Circuit for High Frequencies Input Common-Mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor connected to ground. The input common-mode voltage is nominally 2.3 V, which is 1.5 V for the ADS6149. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 43 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com REFERENCE The ADS61B49/29 have built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. External reference mode is not supported. The reference generates the VCM output (2.3 V). Internal Reference VCM REFM REFP S0165-10 Figure 66. Reference Section CLOCK INPUT The ADS61B49/29 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS) with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources. 44 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Clock Buffer Lpkg » 2 nH 20 W CLKP Cbond » 1 pF Ceq Resr » 100 W Ceq 5 kW VCM 2 pF 5 kW Lpkg » 2 nH 20 W CLKM Cbond » 1 pF Resr » 100 W Ceq » 1 to 3 pF, Equivalent Input Capacitance of Clock Buffer S0275-04 Figure 67. Internal Clock Buffer A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-µF capacitor, as shown in Figure 69. For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF 0.1 mF CMOS Clock Input CLKP Differential Sine-Wave or PECL or LVDS Clock Input CLKP 1.5 V 0.1 mF 0.1 mF CLKM CLKM S0168-16 S0167-10 Figure 68. Differential Clock Driving Circuit Figure 69. Single-Ended Clock Driving Circuit Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 45 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com FINE GAIN CONTROL The ADS61B49/29 include gain settings that can be used to get improved SFDR performance (compared to no gain) or to reduce the required full-scale input voltage. The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 9. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades about 0.5–1 dB. The SNR degradation is less at high input frequencies. As a result, the fine gain is useful at high input frequencies as the SFDR improvement is significant with marginal degradation in SNR. So, the fine gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB. Table 9. Full-Scale Range Across Gains GAIN, dB TYPE 0 Default after reset FULL-SCALE, VPP 2V 1 1.78 2 1.59 3 4 Fine, programmable 1.42 1.26 5 1.12 6 1.00 OFFSET CORRECTION The ADS61B49/29 have an internal offset correction algorithm that estimates and corrects the dc offset up to ±10 mV. The correction can be enabled using the serial register bit <ENABLE OFFSET CORR>. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using register bits <OFFSET CORR TIME CONSTANT> as described in Table 10. After the offset is estimated, the correction can be locked in by setting <OFFSET CORR TIME CONSTANT> = 0. Once locked, the last estimated value is used for offset correction every clock cycle. Note that offset correction is disabled by default after a reset. Figure 70 shows the time response of the offset correction algorithm, after it is enabled. Table 10. Time Constant of Offset Correction Algorithm <OFFSET CORR TIME CONSTANT> D3-D0 TIME CONSTANT (TCCLK), NUMBER OF CLOCK CYCLES TIME CONSTANT, sec (TCCLK x 1/Fs) (1) 0000 256 k 1 ms 0001 512 k 2 ms 0010 1M 4 ms 0011 2M 8 ms 0100 4M 17 ms 0101 8M 33 ms 0110 16 M 67 ms 0111 32 M 134 ms 1000 64 M 268 ms 1001 128 M 536 ms 1010 256 M 1.1 s 1011 512 M 2.2 s 1100 Reserved – 1101 Reserved – 1110 Reserved – (1) 46 Sampling frequency, Fs = 250 MSPS Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Table 10. Time Constant of Offset Correction Algorithm (continued) <OFFSET CORR TIME CONSTANT> D3-D0 TIME CONSTANT (TCCLK), NUMBER OF CLOCK CYCLES TIME CONSTANT, sec (TCCLK x 1/Fs) (1) 1111 Reserved – 8204 Offset Correction Disabled 8200 Offset Correction Enabled 8196 8192 8188 Code − LSB 8184 Output Data With Offset Corrected 8180 8176 8172 8168 Output Data With 36 LSB Offset 8164 8160 8156 8152 8148 0 4 8 12 16 20 24 28 32 36 40 44 48 52 t − Time − µs 56 G080 Figure 70. Output Code Time Response with Offset Correction Enabled POWER DOWN The ADS61B49/29 have three power-down modes – power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip including the A/D converter, the internal reference, and the output buffers are powered down resulting in reduced total power dissipation of about 20 mW. The output buffers are in a high impedance state. The wake-up time from global power down to data becoming valid in normal mode is typically 25 µs. This can be controlled using register bit <PDN GLOBAL> or using the SDATA pin (in parallel configuration mode). Standby Here, only the A/D converter is powered down and the internal references are active, resulting in a fast wake-up time of 300 ns. The total power dissipation in standby is about 120 mW. This can be controlled using register bit <STANDBY>. Output Buffer Disable The output buffers can be disabled and put in a high impedance state – wakeup time from this mode is fast, about 40 ns. This can be controlled using register bit <PDN OBUF>. Input Clock Stop In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is about 120 mW. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 47 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com POWER SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. DIGITAL OUTPUT INFORMATION The ADS61B49/29 provide 14-bit/12-bit data and an output clock synchronized with the data. Output Interface Two output interface options are available – double data rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit <ODI> or using the DFS pin in parallel configuration mode. DDR LVDS Outputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair. Pins 14 bit ADC data CLKOUTP CLKOUTM Output Clock D0_D1_P D0_D1_M Data bits D0, D1 D2_D3_P D2_D3_M Data bits D2, D3 D4_D5_P D4_D5_M Data bits D4, D5 CLKOUTP CLKOUTM D0_D1_P D0_D1_M LVDS Buffers LVDS Buffers Pins Output Clock Data bits D0, D1 P D2_D3_ D2_D3_M D4_D5_P D4_D5_M Data bits D2, D3 Data bits D4, D5 12 bit ADC data D6_D7_P D6_D7_P D6_D7_M Data bits D6, D7 D8_D9_P D8_D9_M Data bits D8, D9 D10_D11_P D10_D11_M Data bits D10, D11 D12_D13_P D12_D13_M Data bits D12, D13 D6_D7_M D8_D9_P D8_D9_M Data bits D6, D7 Data bits D8, D9 D10_D11_P D10_D11_M Data bits D10, D11 ADS612X ADS 614 X Figure 71. 14-Bit ADC LVDS Outputs Figure 72. 12-Bit ADC LVDS Outputs Even data bits D0, D2, D4… are output at the falling edge of CLKOUTP, and the odd data bits D1, D3, D5… are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all of the data bits (see Figure 73). 48 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 CLKOUTP CLKOUTM D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 D12_D13_P, D12_D13_M D12 D13 D12 D13 Sample N Sample N+1 T0110-01 Figure 73. DDR LVDS Interface LVDS Buffer The equivalent circuit of each LVDS output buffer is shown in Figure 74. The buffer is designed to present an output impedance of 100 Ω (Rout). The differential outputs can be terminated at the receive end by a 100-Ω termination. The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its value cannot be changed. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 49 ADS61B29 ADS61B49 + – Low 0.35 V High SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com OUTP + – –0.35 V + – Rout High 1.2 V Low External 100-W Load OUTM Switch impedance is nominally 50 W (±10%) When the High switches are closed, OUTP = 1.375 V, OUTM = 1.025 V When the Low switches are closed, OUTP = 1.025 V, OUTM = 1.375 V When the High (or Low) switches are closed, Rout = 100 W S0374-02 Figure 74. LVDS Buffer Equivalent Circuit Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as a CMOS voltage level, every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to approximately 150 MSPS). Up to 150 MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For sampling frequencies > 150 MSPS in CMOS mode, it is recommended to use an external clock to capture data. The input clock to output data delay and data valid times are specified for the higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture the data (see Figure 4). It is recommended to consider using the LVDS output mode at high sample rates due to device and board noise generated by the CMOS mode. 50 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 Pins OVR_SDOUT CLKOUT D0 14-Bit ADC Data CMOS Output Buffers D1 D2 • • • D11 D12 D13 ADS614x Figure 75. CMOS Output Interface Output Buffer Strength Programmability Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this, the CMOS output buffers are designed with a controlled drive strength to achieve the best SNR. The default drive strength also ensures a wide data stable window for load capacitances up to 5 pF. CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In an actual application, the DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG), where CL = load capacitance, N x FAVG = average number of output bits switching. Figure 54 shows the current across the sampling frequencies with a 3-MHz analog input frequency. Output Data Format Two output data formats are supported – 2s complement and offset binary. They can be selected using the serial interface register bit <DATA FORMAT> or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2s complement output format. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 51 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to achieve good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide for details on layout and grounding. Supply Decoupling As the ADS61B49/29 already include internal decoupling, minimal external decoupling can be used without a loss in performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. Exposed Pad In addition to providing a path for heat dissipation, the pad is also electrically connected to digital ground internally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see the application notes for QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). 52 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 ADS61B29 ADS61B49 www.ti.com ......................................................................................................................................... SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels. The maximum variation is specified as aperture delay variation (channel-channel). Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate – The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and EGCHAN. To a first order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1-0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error – The offset error is the difference, given in number of LSBs, between the actual average idle channel output code and the ideal average idle channel output code of the ADC. This quantity is often mapped into mV. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN. Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. P SNR = 10Log10 S PN (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD = 10Log10 PN + PD (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 53 ADS61B29 ADS61B49 SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com ENOB = SINAD - 1.76 6.02 (3) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD = 10Log10 S PN (4) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then DVOUT (Expressed in dBc) PSRR = 20Log 10 DVSUP (5) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from their expected values) is noted. Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resultant change of the ADC output code (referred to the input), then DVOUT (Expressed in dBc) CMRR = 20Log10 DVCM (6) Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. 54 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B29 ADS61B49 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS61B29IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS61B29IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS61B49IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS61B49IRGZT ACTIVE QFN RGZ 48 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS61B29IRGZR QFN RGZ 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS61B29IRGZT QFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS61B49IRGZR QFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS61B49IRGZT QFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS61B29IRGZR QFN RGZ 48 2500 333.2 345.9 28.6 ADS61B29IRGZT QFN RGZ 48 250 333.2 345.9 28.6 ADS61B49IRGZR QFN RGZ 48 2500 333.2 345.9 28.6 ADS61B49IRGZT QFN RGZ 48 250 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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