a FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLOPS Peak, 66 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 0.58 ms Divide (y/x): 180 ns Inverse Square Root (1/√x): 270 ns 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats 32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators IEEE Exception Handling with Interrupt on Exception Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations Multiply with Add & Subtract for FFT Butterfly Computation Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup Single-Cycle Register File Context Switch 15 (or 25) ns External RAM Access Time for Zero-WaitState, 30 (or 40) ns Instruction Execution IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry 223-Pin PGA Package (Ceramic) GENERAL DESCRIPTION 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FUNCTIONAL BLOCK DIAGRAM DATA ADDRESS GENERATORS DAG 1 The ADSP-21020 features: • Independent Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions. The units are architecturally arranged in parallel, maximizing computational throughput. A single multifunction instruction executes parallel ALU and PROGRAM SEQUENCER JTAG TEST & EMULATION PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA REGISTER FILE EXTERNAL ADDRESS BUSES EXTERNAL DATA BUSES TIMER ARITHMETIC UNITS ALU MULTIPLIER SHIFTER multiplier operations. These computation units support IEEE 32-bit single-precision floating-point, extended precision 40-bit floating-point, and 32-bit fixed-point data formats. • Data Register File • Single-Cycle Fetch of Instruction and Two Operands • Memory Interface The ADSP-21020 is the first member of Analog Devices’ family of single-chip IEEE floating-point processors optimized for digital signal processing applications. Its architecture is similar to that of Analog Devices’ ADSP-2100 family of fixed-point DSP processors. Fabricated in a high-speed, low-power CMOS process, the ADSP-21020 has a 30 ns instruction cycle time. With a highperformance on-chip instruction cache, the ADSP-21020 can execute every instruction in a single cycle. DAG 2 INSTRUCTION CACHE A general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. This 10-port (16-register) register file, combined with the ADSP-21020’s Harvard architecture, allows unconstrained data flow between computation units and off-chip memory. The ADSP-21020 uses a modified Harvard architecture in which data memory stores data and program memory stores both instructions and data. Because of its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch an operand from data memory, an operand from program memory, and an instruction from the cache, all in a single cycle. Addressing of external memory devices by the ADSP-21020 is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-21020 provides programmable memory wait states, and external memory acknowledge controls allow interfacing to peripheral devices with variable access times. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADSP-21020 • • • Instruction Cache The ADSP-21020 includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiplyaccumulates and FFT butterfly processing. • C Source Level Debugger • Numerical C Compiler • ADSP-21020 EZ-LAB® Evaluation Board • ADSP-21020 EZ-ICE® Emulator Hardware Circular Buffers The ADSP-21020 provides hardware to implement circular buffers in memory, which are common in digital filters and Fourier transform implementations. It handles address pointer wraparound, reducing overhead (thereby increasing performance) and simplifying implementation. Circular buffers can start and end at any location. Flexible Instruction Set The ADSP-21020’s 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21020 can conditionally execute a multiply, an add, a subtract and a branch in a single instruction. DEVELOPMENT SYSTEM The ADSP-21020 is supported with a complete set of software and hardware development tools. The ADSP-21000 Family Development System includes development software, an evaluation board and an in-circuit emulator. • Assembler Creates relocatable, COFF (Common Object File Format) object files from ADSP-21xxx assembly source code. It accepts standard C preprocessor directives for conditional assembly and macro processing. The algebraic syntax of the ADSP-21xxx assembly language facilitates coding and debugging of DSP algorithms. • Linker/Librarian • Simulator • • The Linker processes separately assembled object files and library files to create a single executable program. It assigns memory locations to code and to data in accordance with a user-defined architecture file that describes the memory and I/O configuration of the target system. The Librarian allows you to group frequently used object files into a single library file that can be linked with your main program. The Simulator performs interactive, instruction-level simulation of ADSP-21xxx code within the hardware configuration described by a system architecture file. It flags illegal operations and supports full symbolic disassembly. It provides an easy-to-use, window oriented, graphical user interface that is identical to the one used by the ADSP-21020 EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse. PROM Splitter Formats an executable file into files that can be used with an industry-standard PROM programmer. C Compiler and Runtime Library The C Compiler complies with ANSI specifications. It takes advantage of the ADSP-21020’s high-level language architectural features and incorporates optimizing algorithms to speed up the execution of code. It includes an extensive runtime library with over 100 standard and DSP-specific functions. A full-featured C source level debugger that works with the simulator or EZ-ICE emulator to allow debugging of assembler source, C source, or mixed assembler and C. Supports ANSI Standard (X3J11.1) Numerical C as defined by the Numeric C Extensions Group. The compiler accepts C source input containing Numerical C extensions for array selection, vector math operations, complex data types, circular pointers, and variably dimensioned arrays, and outputs ADSP-21xxx assembly language source code. The EZ-LAB Evaluation Board is a general-purpose, standalone ADSP-21020 system that includes 32K words of program memory and 32K words of data memory as well as analog I/O. A PC RS-232 download path enables the user to download and run programs directly on the EZ-LAB. In addition, it may be used in conjunction with the EZ-ICE Emulator to provide a powerful software debug environment. This in-circuit emulator provides the system designer with a PC-based development environment that allows nonintrusive access to the ADSP-21020’s internal registers through the processor’s 5-pin JTAG Test Access Port. This use of on-chip emulation circuitry enables reliable, full-speed performance in any target. The emulator uses the same graphical user interface as the ADSP-21020 Simulator, allowing an easy transition from software to hardware debug. (See “Target System Requirements for Use of EZ-ICE Emulator” on page 27.) ADDITIONAL INFORMATION This data sheet provides a general overview of ADSP-21020 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-21020 User’s Manual. For development system and programming reference information, refer to the ADSP-21000 Family Development Software Manuals and the ADSP-21020 Programmer’s Quick Reference. Applications code listings and benchmarks for key DSP algorithms are available on the DSP Applications BBS; call (617) 461-4258, 8 data bits, no parity, 1 stop bit, 300/1200/ 2400/9600 baud. ARCHITECTURE OVERVIEW Figure 1 shows a block diagram of the ADSP-21020. The processor features: • • • • • • Three Computation Units (ALU, Multiplier, and Shifter) with a Shared Data Register File Two Data Address Generators (DAG 1, DAG 2) Program Sequencer with Instruction Cache 32-Bit Timer Memory Buses and Interface JTAG Test Access Port and On-Chip Emulation Support Computation Units The ADSP-21020 contains three independent computation units: an ALU, a multiplier with fixed-point accumulator, and a shifter. In order to meet a wide variety of processing needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit floating-point and 40-bit floating-point. The floating-point operations are single-precision IEEE-compatible (IEEE Standard 754/854). The 32-bit floating-point format is EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc. –2– REV. C ADSP-21020 CACHE MEMORY 32 x 48 DAG 1 8 x 4 x 32 JTAG TEST & EMULATION FLAGS DAG 2 8 x 4 x 24 PROGRAM SEQUENCER PMA BUS 24 DMA BUS 32 TIMER PMA DMA PMD BUS 48 PMD BUS CONNECT DMD BUS 40 DMD FLOATING & FIXED-POINT MULTIPLIER, FIXED-POINT ACCUMULATOR REGISTER FILE 16 x 40 32-BIT BARREL SHIFTER FLOATING-POINT & FIXED-POINT ALU Figure 1. ADSP-21020 Block Diagram of the ADSP-21020 allow the following nine data transfers to be performed every cycle: the standard IEEE format, whereas the 40-bit IEEE extendedprecision format has eight additional LSBs of mantissa for greater accuracy. • • • • The multiplier performs floating-point and fixed-point multiplication as well as fixed-point multiply/add and multiply/ subtract operations. Integer products are 64 bits wide, and the accumulator is 80 bits wide. The ALU performs 45 standard arithmetic and logic operations, supporting both fixed-point and floating-point formats. The shifter performs 19 different operations on 32-bit operands. These operations include logical and arithmetic shifts, bit manipulation, field deposit, and extract and derive exponent operations. The processor’s 48-bit orthogonal instruction word supports fully parallel data transfer and arithmetic operations in the same instruction. Address Generators and Program Sequencer Two dedicated address generators and a program sequencer supply addresses for memory accesses. Because of this, the computation units need never be used to calculate addresses. Because of its instruction cache, the ADSP-21020 can simultaneously fetch an instruction and data values from both off-chip program memory and off-chip data memory in a single cycle. The computation units perform single-cycle operations; there is no computation pipeline. The three units are connected in parallel rather than serially, via multiple-bus connections with the 10-port data register file. The output of any computation unit may be used as the input of any unit on the next cycle. In a multifunction computation, the ALU and multiplier perform independent, simultaneous operations. The data address generators (DAGs) provide memory addresses when external memory data is transferred over the parallel memory ports to or from internal registers. Dual data address generators enable the processor to output two simultaneous addresses for dual operand reads and writes. DAG 1 supplies 32-bit addresses to data memory. DAG 2 supplies 24-bit addresses to program memory for program memory data accesses. Data Register File The ADSP-21020’s general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. The register file has two sets (primary and alternate) of sixteen 40-bit registers each, for fast context switching. With a large number of buses connecting the registers to the computation units, data flow between computation units and from/to off-chip memory is unconstrained and free from bottlenecks. The 10-port register file and Harvard architecture REV. C Off-chip read/write of two operands to or from the register file Two operands supplied to the ALU Two operands supplied to the multiplier Two results received from the ALU and multiplier (three, if the ALU operation is a combined addition/subtraction) Each DAG keeps track of up to eight address pointers, eight modifiers, eight buffer length values and eight base values. A pointer used for indirect addressing can be modified by a value –3– ADSP-21020 in a specified register, either before (premodify) or after (postmodify) the access. To implement automatic modulo addressing for circular buffers, the ADSP-21020 provides buffer length registers that can be associated with each pointer. Base values for pointers allow circular buffers to be placed at arbitrary locations. Each DAG register has an alternate register that can be activated for fast context switching. The program sequencer supplies instruction addresses to program memory. It controls loop iterations and evaluates conditional instructions. To execute looped code with zero overhead, the ADSP-21020 maintains an internal loop counter and loop stack. No explicit jump or decrement instructions are required to maintain the loop. The ADSP-21020 derives its high clock rate from pipelined fetch, decode and execute cycles. Approximately 70% of the machine cycle is available for memory accesses; consequently, ADSP-21020 systems can be built using slower and therefore less expensive memory chips. Instruction Cache The program sequencer includes a high performance, selective instruction cache that enables three-bus operation for fetching an instruction and two data values. This two-way, set-associative cache holds 32 instructions. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached, so the ADSP-21020 can perform a program memory data access and can execute the corresponding instruction in the same cycle. The program sequencer fetches the instruction from the cache instead of from program memory, enabling the ADSP-21020 to simultaneously access data in both program memory and data memory. Context Switching Many of the ADSP-21020’s registers have alternate register sets that can be activated during interrupt servicing to facilitate a fast context switch. The data registers in the register file, DAG registers and the multiplier result register all have alternate sets. Registers active at reset are called primary registers; the others are called alternate registers. Bits in the MODE1 control register determine which registers are active at any particular time. The primary/alternate select bits for each half of the register file (top eight or bottom eight registers) are independent. Likewise, the top four and bottom four register sets in each DAG have independent primary/ alternate select bits. This scheme allows passing of data between contexts. Interrupts The ADSP-21020 has four external hardware interrupts, nine internally generated interrupts, and eight software interrupts. For the external interrupts and the internal timer interrupt, the ADSP-21020 automatically stacks the arithmetic status and mode (MODE1) registers when servicing the interrupt, allowing five nesting levels of fast service for these interrupts. An interrupt can occur at any time while the ADSP-21020 is executing a program. Internal events that generate interrupts include arithmetic exceptions, which allow for fast trap handling and recovery. Timer The programmable interval timer provides periodic interrupt generation. When enabled, the timer decrements a 32-bit count register every cycle. When this count register reaches zero, the ADSP-21020 generates an interrupt and asserts its TIMEXP output. The count register is automatically reloaded from a 32-bit period register and the count resumes immediately. System Interface Figure 2 shows an ADSP-21020 basic system configuration. The external memory interface supports memory-mapped peripherals and slower memory with a user-defined combination of programmable wait states and hardware acknowledge signals. Both the program memory and data memory interfaces support addressing of page-mode DRAMs. The ADSP-21020’s internal functions are supported by four internal buses: the program memory address (PMA) and data memory address (DMA) buses are used for addresses associated with program and data memory. The program memory data (PMD) and data memory data (DMD) buses are used for data associated with the two memory spaces. These buses are extended off chip. Four data memory select (DMS) signals select one of four user-configurable banks of data memory. Similarly, two program memory select (PMS) signals select between two user-configurable banks of program memory. All banks are independently programmable for 0-7 wait states. The PX registers permit passing data between program memory and data memory spaces. They provide a bridge between the 48-bit PMD bus and the 40-bit DMD bus or between the 40-bit register file and the PMD bus. The PMA bus is 24 bits wide allowing direct access of up to 16M words of mixed instruction code and data. The PMD is 48 bits wide to accommodate the 48-bit instruction width. For access of 40-bit data the lower 8 bits are unused. For access of 32-bit data the lower 16 bits are ignored. The DMA bus is 32 bits wide allowing direct access of up to 4 Gigawords of data. The DMD bus is 40 bits wide. For 32-bit data, the lower 8 bits are unused. The DMD bus provides a path for the contents of any register in the processor to be transferred to any other register or to any external data memory location in a single cycle. The data memory address comes from one of two sources: an absolute value specified in the instruction code (direct addressing) or the output of a data address generator (indirect addressing). External devices can gain control of the processor’s memory buses from the ADSP-21020 by means of the bus request/grant signals (BR and BG). To grant its buses in response to a bus request, the ADSP-21020 halts internal operations and places its program and data memory interfaces in a high impedance state. In addition, three-state controls (DMTS and PMTS) allow an external device to place either the program or data memory interface in a high impedance state without affecting the other interface and without halting the ADSP-21020 unless it requires a memory access from the affected interface. The three-state controls make it easy for an external cache controller to hold the ADSP-21020 off the bus while it updates an external cache memory. JTAG Test and Emulation Support The ADSP-21020 implements the boundary scan testing provisions specified by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The ADSP-21020’s test access port and on-chip JTAG circuitry is fully compliant with the IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the ADSP-21020’s I/O pins. –4– REV. C ADSP-21020 1× CLOCK 4 CLKIN PROGRAM MEMORY RESET 2 SELECTS IRQ3-0 DMS3-0 PMS1-0 OE WE 24 ADDR PMRD DMRD PMWR PMA DMWR DMA 48 DMD PMD DATA 4 SELECTS OE DATA MEMORY WE 32 ADDR 32 DATA ADSP-21010 PMTS PMACK OE WE ACK 4 PERIPHERALS ADDR JTAG FLAG3-0 RCOMP TIMEXP DMACK BG BR SELECTS DMTS DMPAGE PMPAGE DATA 5 Figure 2. Basic System Configuration The ADSP-21020 also implements on-chip emulation through the JTAG test access port. The processor’s eight sets of breakpoint range registers enable program execution at full speed until reaching a desired break-point address range. The processor can then halt and allow reading/writing of all the processor’s internal registers and external memories through the JTAG port. Pin Name Type Function PMPAGE O PIN DESCRIPTIONS This section describes the pins of the ADSP-21020. When groups of pins are identified with subscripts, e.g. PMD47–0, the highest numbered pin is the MSB (in this case, PMD47). Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST). Those that are asynchronous (A) can be asserted asynchronously to CLKIN. PMTS I/S DMA31–0 O DMD39–0 I/O DMS3–0 O DMRD O DMWR O DMACK I/S O = Output; I = Input; S = Synchronous; A = Asynchronous; P = Power Supply; G = Ground. Pin Name Type PMA23–0 O PMD47–0 I/O PMS1–0 O PMRD O PMWR O PMACK I/S REV. C Function Program Memory Address. The ADSP-21020 outputs an address in program memory on these pins. Program Memory Data. The ADSP-21020 inputs and outputs data and instructions on these pins. 32-bit fixed-point data and 32-bit single-precision floating-point data is transferred over bits 47-16 of the PMD bus. Program Memory Select lines. These pins are asserted as chip selects for the corresponding banks of program memory. Memory banks must be defined in the memory control registers. These pins are decoded program memory address lines and provide an early indication of a possible bus cycle. Program Memory Read strobe. This pin is asserted when the ADSP-21020 reads from program memory. Program Memory Write strobe. This pin is asserted when the ADSP-21020 writes to program memory. Program Memory Acknowledge. An external device deasserts this input to add wait states to a memory access. –5– Program Memory Page Boundary. The ADSP-21020 asserts this pin to signal that a program memory page boundary has been crossed. Memory pages must be defined in the memory control registers. Program Memory Three-State Control. PMTS places the program memory address, data, selects, and strobes in a highimpedance state. If PMTS is asserted while a PM access is occurring, the processor will halt and the memory access will not be completed. PMACK must be asserted for at least one cycle when PMTS is deasserted to allow any pending memory access to complete properly. PMTS should only be asserted (low) during an active memory access cycle. Data Memory Address. The ADSP-21020 outputs an address in data memory on these pins. Data Memory Data. The ADSP-21020 inputs and outputs data on these pins. 32-bit fixed point data and 32-bit single-precision floating point data is transferred over bits 39-8 of the DMD bus. Data Memory Select lines. These pins are asserted as chip selects for the corresponding banks of data memory. Memory banks must be defined in the memory control registers. These pins are decoded data memory address lines and provide an early indication of a possible bus cycle. Data Memory Read strobe. This pin is asserted when the ADSP-21020 reads from data memory. Data Memory Write strobe. This pin is asserted when the ADSP-21020 writes to data memory. Data Memory Acknowledge. An external device deasserts this input to add wait states to a memory access. ADSP-21020 Pin Name Type Function DMPAGE O DMTS CLKIIN RESET IRQ3–0 FLAG3–0 BR BG TIMEXP RCOMP EVDD EGND Data Memory Page Boundary. The ADSP21020 asserts this pin to signal that a data memory page boundary has been crossed. Memory pages must be defined in the memory control registers. I/S Data Memory Three-State Control. DMTS places the data memory address, data, selects, and strobes in a high-impedance state. If DMTS is asserted while a DM access is occurring, the processor will halt and the memory access will not be completed. DMACK must be asserted for at least one cycle when DMTS is deasserted to allow any pending memory access to complete properly. DMTS should only be asserted (low) during an active memory access cycle. I External clock input to the ADSP-21020. The instruction cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. I/A Sets the ADSP-21020 to a known state and begins execution at the program memory location specified by the hardware reset vector (address). This input must be asserted (low) at power-up. I/A Interrupt request lines; may be either edge triggered or level-sensitive. I/O/A External Flags. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. I/A Bus Request. Used by an external device to request control of the memory interface. When BR is asserted, the processor halts execution after completion of the current cycle, places all memory data, addresses, selects, and strobes in a high-impedance state, and asserts BG. The processor continues normal operation when BR is released. O Bus Grant. Acknowledges a bus request (BR), indicating that the external device may take control of the memory interface. BG is asserted (held low) until BR is released. O Timer Expired. Asserted for four cycles when the value of TCOUNT is decremented to zero. Compensation Resistor input. Controls compensated output buffers. Connect RCOMP through a 1.8 kΩ ± 15% resistor to EVDD. Use of a capacitor (approximately 100 pF), placed in parallel with the 1.8 kΩ resistor is recommended. P Power supply (for output drivers), nominally +5 V dc (10 pins). G Power supply return (for output drivers); (16 pins). Pin Name Type Function IVDD P IGND G TCK I TMS I/S TDI VS TDO O TRST I/A Power supply (for internal circuitry), nominally +5 V dc (4 pins). Power supply return (for internal circuitry); (7 pins). Test Clock. Provides an asynchronous clock for JTAG boundary scan. Test Mode Select. Used to control the test state machine. TMS has a 20 kΩ internal pullup resistor. Test Data Input. Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pullup resistor. Test Data Output. Serial scan output of the boundary scan path. Test Reset. Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21020. TRST has a 20 kΩ internal pullup resistor. No Connect. No Connects are reserved pins that must be left open and unconnected. NC INSTRUCTION SET SUMMARY The ADSP-21020 instruction set provides a wide variety of programming capabilities. Every instruction assembles into a single word and can execute in a single processor cycle. Multifunction instructions enable simultaneous multiplier and ALU operations, as well as computations executed in parallel with data transfers. The addressing power of the ADSP-21020 gives you flexibility in moving data both internally and externally. The ADSP-21020 assembly language uses an algebraic syntax for ease of coding and readability. The instruction types are grouped into four categories: Compute and Move or Modify Program Flow Control Immediate Move Miscellaneous The instruction types are numbered; there are 22 types. Some instructions have more than one syntactical form; for example, Instruction 4 has four distinct forms. The instruction number itself has no bearing on programming, but corresponds to the opcode recognized by the ADSP-21020 device. Because of the width and orthogonality of the instruction word, there are many possible instructions. For example, the ALU supports 21 fixed-point operations and 24 floating-point operations; each of these operations can be the compute portion of an instruction. The following pages provide an overview and summary of the ADSP-21020 instruction set. For complete information, see the ADSP-21020 User’s Manual. For additional reference information, see the ADSP-21020 Programmer’s Quick Reference. This section also contains several reference tables for using the instruction set. • Table I describes the notation and abbreviations used. • Table II lists all condition and termination code mnemonics. • Table III lists all register mnemonics. • Tables IV through VII list the syntax for all compute (ALU, multiplier, shifter or multifunction) operations. • Table VIII lists interrupts and their vector addresses. –6– REV. C ADSP-21020 COMPUTE AND MOVE OR MODIFY INSTRUCTIONS 1. compute, |DM(Ia, Mb) = dreg1| |dreg1 = DM(Ia, Mb)| |PM(Ic, Md) = dreg2| |dreg2 = PM(Ic, Md)| , 2. IF condition compute; 3a. IF condition compute, 3b. IF condition compute, 3c. IF condition compute, 3d. IF condition compute, 4a. IF condition compute, 4b. IF condition compute, 4c. IF condition compute, 4d. IF condition compute, 5. IF condition compute, ureg1 = ureg2 ; 6a. IF condition shiftimm, 6b. IF condition shiftimm, 7. IF condition compute, 7. IF condition compute, |DM(Ia, Mb)| = dreg ; |PM(Ic, Md) | dreg = |DM(Ia, Mb)| ; |PM(Ic, Md) | MODIFY |(Ia, Mb) | ; MODIFY |(Ic, Md) | |DM(Ia, Mb)| = ureg ; |PM(Ic, Md) | |DM(Mb, Ia)| = ureg ; |PM(Md, Ic) | ureg = |DM(Ia, Mb) | ; |PM(Ic, Md) | ureg = |DM(Mb, Ia) | ; |PM(Md, Ic) | |DM(Ia, <data6>)| = dreg ; |PM(Ic, <data6>) | |DM(<data6>, Ia)| = dreg ; |PM(<data6>, Ic) | dreg = |DM(Ia, <data6>) | ; |PM(Ic, <data6>) | dreg = |DM(<data6>, Ia)| ; |PM(<data6>, Ic) | PROGRAM FLOW CONTROL INSTRUCTIONS 8. IF condition 9. IF condition 11. IF condition 12. LCNTR = 12. LCNTR = 13. LCNTR = 12. LCNTR = |JUMP | |CALL | |CALL| |JUMP | |CALL | |CALL| |<addr24> | |(PC, <reladdr6>) | |(PC, <reladdr6>) | |(Md, Ic) | |(PC, <reladdr6>) | |(PC, <reladdr6>) | (|DB (|LA, | ( DB, LA |) ; | | (|DB (|LA, | ( DB, LA |) | | |RTS | (|DB, |) , compute ; |RTI | (|LA, | | | |RTI | ( DB, LA |<data16> | , DO |<addr24> | |ureg | , DO |(<PC, <reladdr24>)( | |<data16> | , DO |<addr24> | |ureg | , DO |(|(PC, <reladdr24>) | (DB) Delayed branch (LA) Loop abort (pop loop PC stacks on branch) REV. C –7– , compute ; UNTIL LCE ; UNTIL LCE ; UNTIL termination ; ; ADSP-21020 IMMEDIATE MOVE INSTRUCTIONS Table II. Condition and Termination Codes 14a. DM(<addr32>) = ureg ; PM(<addr24>) Name Description 14b. ureg = eq ne ge lt le gt ac not ac av not av mv not mv ms not ms sv not sv sz not sz flag0_in not flag0_in flag1_in not flag1_in flag2_in not flag2_in flag3_in not flag3_in tf not tf lce not lce forever true ALU equal to zero ALU not equal to zero ALU greater than or equal to zero ALU less than zero ALU less than or equal to zero ALU greater than zero ALU carry Not ALU carry ALU overflow Not ALU overflow Multiplier overflow Not multiplier overflow Multiplier sign Not multiplier sign Shifter overflow Not shifter overflow Shifter zero Not shifter zero Flag 0 Not Flag 0 Flag 1 Not Flag l Flag 2 Not Flag 2 Flag 3 Not Flag 3 Bit test flag Not bit test flag Loop counter expired (DO UNTIL) Loop counter not expired (IF) Always False (DO UNTIL) Always True (IF) DM(<addr32>) ; PM(<addr24>) 15a. DM(<data32>, Ia) = ureg; PM(< data24>, Ic) 15b. ureg = DM(<data32>, Ia) ; PM(<data24>, Ic) 16. DM(Ia, Mb) = <data32>; PM(Ic, Md) 17. ureg = <data32>; MISCELLANEOUS INSTRUCTIONS 18. BIT SET CLR TGL TST XOR sreg <data32>; 19a. MODIFY (Ia, <data32>)|; (Ic, <data32>)| 19b. BITREV (Ia, <data32>) ; 20. |PUSH |POP LOOP , PUSH POP STS ; 21. NOP ; 22. IDLE ; Table I. Syntax Notation Conventions Notation UPPERCASE ; , italics | between lines | <datan> <addrn> <reladdrn> compute shiftimm condition termination ureg sreg dreg Ia Mb Ic Md Meaning Explicit syntax—assembler keyword (notation only; assembler is not case-sensitive and lowercase is the preferred programming convention) Instruction terminator Separates parallel operations in an instruction Optional part of instruction List of options (choose one) n-bit immediate data value n-bit immediate address value n-bit immediate PC-relative address value ALU, multiplier, shifter or multifunction operation (from Tables IV-VII) Shifter immediate operation (from Table VI) Status condition (from Table II) Termination condition (from Table II) Universal register (from Table III) System register (from Table III) R15-R0, F15-F0; register file location I7-I0; DAG1 index register M7-M0; DAG1 modify register I15-I8; DAG2 index register M15-M8; DAG2 modify register In a conditional instruction, the execution of the entire instruction is based on the specified condition. –8– REV. C ADSP-21020 Table III. Universal Registers Name Table IV. ALU Compute Operations Function Register File R15–R0 Register file locations Program Sequencer PC* Program counter; address of instruction currently executing PCSTK Top of PC stack PCSTKP PC stack pointer FADDR* Fetch address DADDR* Decode address LADDR Loop termination address, code; top of loop address stack CURLCNTR Current loop counter; top of loop count stack LCNTR Loop count for next nested counter-controlled loop Data Address Generators I7–I0 DAG1 index registers M7–M0 DAG1 modify registers L7–L0 DAG1 length registers B7–B0 DAG1 base registers I15–I8 DAG2 index registers M15–M8 DAG2 modify registers L15–L8 DAG2 length registers B15–B8 DAG2 base registers Bus Exchange PX1 PMD-DMD bus exchange 1 (16 bits) PX2 PMD-DMD bus exchange 2 (32 bits) PX 48-bit PX1 and PX2 combination Timer TPERIOD Timer period TCOUNT Timer counter Memory Interface DMWAIT Wait state and page size control for data memory DMBANK1 Data memory bank 1 upper boundary DMBANK2 Data memory bank 2 upper boundary DMBANK3 Data memory bank 3 upper boundary DMADR* Copy of last data memory address PMWAIT Wait state and page size control for program memory PMBANK1 Program memory bank 1 upper boundary PMADR* Copy of last program memory address System Registers MODE1 Mode control bits for bit-reverse, alternate registers, interrupt nesting and enable, ALU saturation, floating-point rounding mode and boundary MODE2 Mode control bits for interrupt sensitivity, cache disable and freeze, timer enable, and I/O flag configuration IRPTL Interrupt latch IMASK Interrupt mask IMASKP Interrupt mask pointer (for nesting) ASTAT Arithmetic status flags, bit test, I/O flag values, and compare accumulator STKY Sticky arithmetic status flags, circular buffer overflow flags, stack status flags (not sticky) USTAT1 User status register l USTAT2 User status register 2 Floating-Point Rn = Rx + Ry Rn = Rx – Ry Rn = Rx + Ry, Rm = Rx – Ry Rn = Rx + Ry + CI Rn = Rx – Ry + CI – l Rn = (Rx + Ry)/2 COMP(Rx, Ry) Rn = –Rx Rn = ABS Rx Rn = PASS Rx Rn = MIN(Rx, Ry) Rn = MAX(Rx, Ry) Rn = CLIP Rx BY Ry Rn = Rx + CI Rn = Rx + CI – 1 Rn = Rx + l Rn = Rx – l Rn = Rx AND Ry Rn = Rx OR Ry Rn = Rx XOR Ry Rn = NOT Rx Fn = Fx + Fy Fn = Fx – Fy Fn = Fx + Fy, Fm = Fx – Fy Fn = ABS (Fx + Fy) Fn = ABS (Fx – Fy) Fn = (Fx + Fy)/2 COMP(Fx, Fy) Fn = –Fx Fn = ABS Fx Fn = PASS Fx Fn = MIN(Fx, Fy) Fn = MAX(Fx, Fy) Fn = CLIP Fx BY Fy Fn = RND Fx Fn = SCALB Fx BY Ry Rn = MANT Fx Rn = LOGB Fx Rn = FIX Fx BY Ry Rn = FIX Fx Fn = FLOAT Rx BY Ry Fn = FLOAT Rx Fn = RECIPS Fx Fn = RSQRTS Fx Fn = Fx COPYSIGN Fy Rn, Rx, Ry R15–R0; register file location, fixed-point Fn, Fx, Fy F15–F0; register file location, floating point *read-only Refer to User’s Manual for bit-level definitions of each register. REV. C Fixed-Point –9– ADSP-21020 Table V. Multiplier Compute Operations Rn MRF MRB Rn Rn MRF MRB Rn Rn MRF MRB MRF MRB MRxF MRxB = Rx * Ry ( S S F = Rx * Ry ( U U I = Rx * Ry ( U U FR = MRF + Rx * Ry ( S = MRB + Rx * Ry ( U = MRF + Rx * Ry ( U = MRB = SAT MRF (SI) = SAT MRB (UI) = SAT MRF (SF) = SAT MRB (UF) =0 ) = Rn Fn S F ) U I U FR = Fx * Fy Rn Rn MRF MRB Rn Rn MRF MRB = MRF – Rx * Ry ( S S F ) = MRB= Rx * Ry ( U U I = MRF= Rx * Ry ( U U I FR = MRB = RND MRF (SF) = RND MRB (UF) = RND MRF = RND MRB Rn Rn = MRxF = MRxB Rn, Rx, Ry R15–R0; register file location, fixed-point Fn, Fx, Fy F15–F0; register file location, floating-point MRxF MR2F, MR1F; MR0F; multiplier result accumulators, foreground MRxB MR2B, MR1B, MR0B; multiplier result accumulators, background ( x-input y-input data format, ) ( x-input y-input rounding S Signed input U Unsigned input I Integer input(s) F Fractional input(s) FR Fractional inputs, Rounded output (SF) Default format for 1-input operations (SSF) Default format for 2-input operations Table VI. Shifter and Shifter Immediate Compute Operations Shifter Shifter Immediate Rn = LSHIFT Rx BY Ry Rn = Rn OR LSHIFT Rx BY Ry Rn = ASHIFT Rx BY Ry Rn = Rn OR ASHIFT Rx BY Ry Rn = ROT Rx BY RY Rn = BCLR Rx BY Ry Rn = BSET Rx BY Ry Rn = BTGL Rx BY Ry BTST Rx BY Ry Rn = FDEP Rx BY Ry Rn = Rn OR FDEP Rx BY Ry Rn = FDEP Rx BY Ry (SE) Rn = Rn OR FDEP Rx BY Ry (SE) Rn = FEXT Rx BY Ry Rn = FEXT Rx BY Ry (SE) Rn = EXP Rx Rn = EXP Rx (EX) Rn = LEFTZ Rx Rn = LEFTO Rx Rn = LSHIFT Rx BY<data8> Rn = Rn OR LSHIFT Rx BY<data8> Rn = ASHIFT Rx BY<data8> Rn = Rn OR ASHIFT Rx BY<data8> Rn = ROT Rx BY<data8> Rn = BCLR Rx BY<data8> Rn = BSET Rx BY<data8> Rn = BTGL Rx BY<data8> BTST Rx BY<data8> Rn = FDEP Rx BY <bit6>: <len6> Rn = Rn OR FDEP Rx BY <bit6>:<1en6> Rn = FDEP Rx BY <bit6>:<1en6> (SE) Rn = Rn OR FDEP Rx BY <bit6>:<1en6> (SE) Rn = FEXT Rx BY <bit6>:<1en6> Rn = FEXT Rx BY <bit6>:<1en6> (SE) Rn, Rx, Ry R15-R0; register file location, fixed-point <bit6>:<len6> 6-bit immediate bit position and length values (for shifter immediate operations) –10– REV. C ADSP-21020 Table Vll. Multifunction Compute Operations Table VIII. Interrupt Vector Addresses and Priorities Fixed-Point Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2 Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=MRF + R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12 MRF=MRF – R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2 Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=MRF – R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12, Rs=R11-8 – R15-12 Floating-Point Fm=F3-0 * F7-4, Fa=F11-8 + F15-12 Fm=F3-0 * F7-4, Fa=F11-8 – F15-12 Fm=F3-0 * F7-4, Fa=FLOAT R11-8 by R15-12 Fm=F3-0 * F7-4, Fa=FIX R11-8 by R15-12 Fm=F3-0 * F7-4, Fa=(F11-8 + F15-12)/2 Fm=F3-0 * F7-4, Fa=ABS F11-8 Fm=F3-0 * F7-4, Fa=MAX (F11-8, F15-12) Fm=F3-0 * F7-4, Fa=MIN (F11-8, F15-12) Fm=F3-0 * F7-4, Fa=F11-8 + F15-12, Fs=F11-8 – F15-12 Ra, Rm R3-0 R7-4 R11-8 R15-12 Fa, Fm F3-0 F7-4 F11-8 F15-12 (SSF) (SSFR) REV. C No. Vector Address (Hex) 0 1* 2 3 0x00 0x08 0xl0 0xl8 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19–23 24–31 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98-0xB8 0xC0–OxF8 *Nonmaskable Any register file location (fixed-point) R3, R2, R1, R0 R7, R6, R5, R4 R11, R10, R9, R8 R15, R14, R13, R12 Any register file location (floating-point) F3, F2, F1, F0 F7, F6, F5, F4 F11, F10, F9, F8 F15, F14, F13, F12 X-input signed, Y-input signed, fractional inputs X-input signed, Y-input signed, fractional inputs, rounded output –11– Function Reserved Reset Reserved Status stack or loop stack overflow or PC stack full Timer=0 (high priority option) IRQ3 asserted IRQ2 asserted IRQ1 asserted IRQ0 asserted Reserved Reserved DAG 1 circular buffer 7 overflow DAG 2 circular buffer 15 overflow Reserved Timer=0 (low priority option) Fixed-point overflow Floating-point overflow Floating-point underflow Floating-point invalid operation Reserved User software interrupts ADSP-21020–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter K Grade Min Max B Grade Min Max T Grade Min Max Unit VDD TAMB 4.50 0 4.50 –40 4.50 –55 V °C Supply Voltage Ambient Operating Temperature 5.50 +70 5.50 +85 5.50 +125 Refer to Environmental Conditions for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter VIH VIHCR VIL VILC VOH VOL IIH IIL IILT IOZH IOZL IDDIN Hi-Level Input Voltage1 Hi-Level Input Voltage2, 12 Lo-Level Input Voltage1, 12 Lo-Level Input Voltage2 Hi-Level Output Voltage3, 11 Lo-Level Output Voltage3, 11 Hi-Level Input Current4, 5 Lo-Level Input Current4 Lo-Level Input Current5 Tristate Leakage Current6 Tristate Leakage Current6 Supply Current (Internal)7 IDDIDLE CIN Supply Current (Idle)8 Input Capacitance9, 10 Test Conditions Min VDD = max VDD = max VDD = min VDD = max VDD = min, IOH = –1.0 mA VDD = min, IOL = 4.0 mA VDD = max, VIN = VDD max VDD = max, VIN = 0 V VDD = max, VIN = 0 V VDD = max, VIN = VDD max VDD = max, VIN = 0 V tCK = 30–33 ns, VDD = max, VIHCR = 3.0 V, VIH = 2.4 V, VIL = VILC = 0.4 V VDD = max, VIN = 0 V or VDD max fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 2.0 3.0 Max Unit 0.4 10 10 350 10 10 490 V V V V V V µA µA µA µA µA mA 150 10 mA pF 0.8 0.6 2.4 NOTES l Applies to: PMD47–0, PMACK, PMTS, DMD39–0, DMACK, DMTS, IRQ3–0. FLAG3–0, BR, TMS, TDI. 2 Applies to: CLKIN, TCK. 3 Applies to: PMA23–0, PMD47–0, PMS1–0, PMRD, PMWR, PMPAGE, DMA31–0, DMD39–0, DMS3–0, DMRD, DMWR, DMPAGE, FLAG3–0, TIMEXP, BG. 4 Applies to: PMACK, PMTS, DMACK, DMTS, IRQ3–0, BR, CLKIN, RESET, TCK. 5 Applies to: TMS, TDI, TRST. 6 Applies to: PMA23–0, PMD47–0, PMS1–0, PMRD, PMWR, PMPAGE, DMA31–0, DMD39–0, DMS3–0, DMRD, DMWR, DMPAGE, FLAG3–0, TDO. 7 Applies to IVDD pins. At t CK = 30–33 ns, I DDIN (typical) = 230 mA; at t CK = 40 ns, I DDIN (max) = 420 mA and I DDIN (typical) = 200 mA; at t CK = 50 ns, IDDIN (max) = 370 mA and I DDIN (typical) = 115 mA. See “Power Dissipation” for calculation of external (EVDD) supply current for total supply current. 8 Applies to IVDD pins. Idle refers to ADSP-21020 state of operation during execution of the IDLE instruction. 9 Guaranteed but not tested. 10 Applies to all signal pins. 11 Although specified for TTL outputs, all ADSP-21020 outputs are CMOS-compatible and will drive to V DD and GND assuming no dc loads. 12 Applies to RESET, TRST. ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Operating Temperature Range (Ambient) . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (10 seconds) CPGA . . . . . . . . . . . +300°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY The ADSP-21020 features proprietary input protection circuitry to dissipate high energy discharges (Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-21020 has been classified as a Class 3 device, with the ability to withstand up to 4000 V ESD. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual. –12– WARNING! ESD SENSITIVE DEVICE REV. C ADSP-21020 TIMING PARAMETERS General Notes See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive other specifications. Clock Signal K/B/T Grade K/B/T Grade B/T Grade K Grade Parameter 20 MHz Min Max 25 MHz Min Max 30 MHz Min Max 33.3 MHz Min Max Unit Timing Requirement: tCK CLKIN Period tCKH CLKIN Width High tCKL CLKIN Width Low 50 10 10 40 10 10 33 10 10 30 10 10 ns ns ns 150 150 150 150 t CK CLKIN t CKL t CKH Figure 3. Clock Reset K/B/T Grade K/B/T Grade B/T Grade 20 MHz Min Max Parameter Timing Requirement: tWRST1 RESET Width Low 200 tSRST2 RESET Setup before CLKIN High 29 50 K Grade 25 MHz Min Max 30 MHz Min Max 33.3 MHz Min Max Frequency Dependency* Min Max Unit 160 24 132 21 120 19 4tCK 29 + DT/2 40 33 30 30 ns ns NOTES DT = tCK –50 ns 1 Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles while RESET is low, assuming stable VDD and CLKIN (not including clock oscillator start-up time). 2 Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for reset sequence information. CLKIN tSRST t WRST RESET Figure 4. Reset REV. C –13– ADSP-21020 Interrupts K/B/T Grade K/B/T Grade B/T Grade 20 MHz Min Max Parameter Timing Requirement: tSIR IRQ3-0 Setup before CLKIN High 38 tHIR IRQ3-0 Hold after CLKIN High 0 tIPW IRQ3-0 Pulse Width 55 K Grade 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Min Max Min Max Min Max Min Max Unit 31 0 45 25 0 38 23 0 35 38 + 3DT/4 ns ns tCK + 5 ns NOTE *DT = tCK – 50 ns Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met. Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for interrupt servicing information. CLKIN t HIR t SIR IRQ3-0 t IPW Figure 5. Interrupts Timer K/B/T Grade K/B/T Grade Parameter 20 MHz Min Max Switching Characteristic: tDTEX CLKIN High to TIMEXP 24 25 MHz Min Max B/T Grade K Grade 30 MHz 33.3 MHz Frequency Dependency* Min Max Min Max Min Max Unit 24 24 24 ns NOTE *DT = tCK – 50 ns CLKIN t DTEX t DTEX TIMEXP Figure 6. TIMEXP –14– REV. C ADSP-21020 Flags K/B/T Grade K/B/T Grade B/T Grade 20 MHz Min Max Parameter Timing Requirement:1 tSFI FLAG3-0IN Setup before CLKIN High 19 0 tHFI FLAG3-0IN Hold after CLKIN High tDWRFI FLAG3-0IN Delay from xRD, xWR Low tHFIWR FLAG3-0IN Hold after xRD, xWR 0 Deasserted Switching Characteristic: tDFO FLAG3-0OUT Delay from CLKIN High tHFO FLAG3-0OUT Hold after CLKIN High 5 1 tDFOE CLKIN High to FLAG3-0OUT Enable tDFOD CLKIN High to FLAG3-0OUT Disable K Grade 25 MHz 30 MHz Min Max Min Max 33.3 MHz Frequency Dependency* Min Max Min Max Unit 16 0 13 0 14 0 12 8 0 5 0 24 3 24 5 1 24 ns ns 12 + 7DT/16 ns ns 0 24 5 1 19 + 5DT/16 24 ns ns ns ns 5 1 24 24 24 NOTES *DT = tCK – 50 ns 1 Flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for additional flag servicing information. x = PM or DM. CLKIN tDFO t DFO tDFOE tHFO FLAG3-0 OUT FLAG OUTPUT CLKIN tSFI tHFI FLAG3-0 IN t DWRFI t HFIWR xRD, xWR FLAG INPUT Figure 7. Flags REV. C –15– t DFOD ADSP-21020 Bus Request/Bus Grant K/B/T Grade K/B/T Grade B/T Grade K Grade Parameter 20 MHz Min Max 25 MHz 30 MHz Min Max Min Max 33.3 MHz Frequency Dependency* Min Max Min Max Unit Timing Requirement: tHBR BR Hold after CLKIN High BR Setup before CLKIN High tSBR 0 18 0 15 0 13 0 12 –2 –2 –2 Switching Characteristic: tDMDBGL Memory Interface Disable to BG Low –2 CLKIN High to Memory Interface tDME Enable 25 tDBGL CLKIN High to BG Low tDBGH CLKIN High to BG High 20 22 22 16 22 22 18 + 5DT/16 ns 15 22 22 ns ns 25 + DT/2 22 22 ns ns ns NOTES *DT = tCK – 50 ns. Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE. Buses are not granted until completion of current memory access. See the Memory Interface chapter of the ADSP-21020 User’s Manual for BG, BR cycle relationships. CLKIN t HBR t HBR tSBR tSBR BR t DME MEMORY INTERFACE t DMDBGL t DBGL t DBGH BG Figure 8. Bus Request/Bus Grant –16– REV. C ADSP-21020 External Memory Three-State Control K/B/T Grade K/B/T Grade B/T Grade Parameter Timing Requirement: tSTS xTS, Setup before CLKIN High tDADTS xTS Delay after Address, Select tDSTS xTS Delay after XRD, XWR Low Switching Characteristic: tDTSD Memory Interface Disable before CLKIN High tDTSAE xTS High to Address, Select Enable K Grade 20 MHz Min Max 25 MHz Min Max 30 MHz 33.3 MHz Frequency Dependency* Min Max Min Max Min Max Unit 14 12 10 50 28 16 0 0 40 19 11 –2 0 –4 0 33 13 7 9 –5 0 30 10 6 14 + DT/4 tCK ns 28 + 7DT/8 ns 16 + DT/2 ns DT/4 NOTES *DT = tCK – 50 ns. xTS should only be asserted (low) during an active memory access cycle. Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE. Address = PMA23-0, DMA31-0. Select = PMS1-0, DMS3-0. x = PM or DM. CLKIN tSTS tSTS PMTS, DMTS t DADTS t DSTS t DTSD xRD, xWR t DTSAE ADDRESS, SELECTS DATA Figure 9. External Memory Three-State Control REV. C –17– ns ns ADSP-21020 Memory Read Parameter Timing Requirement: tDAD Address, Select to Data Valid tDRLD xRD Low to Data Valid tHDA Data Hold from Address, Select tHDRH Data Hold from xRD High tDAAK xACK Delay from Address tDRAK xACK Delay from xRD Low tSAK xACK Setup before CLKIN High xACK Hold after CLKIN High tHAK Switching Characteristic: tDARL Address, Select to xRD Low xPAGE Delay from Address, Select tDAP tDCKRL CLKIN High to xRD Low tRW xRD Pulse Width tRWR xRD High to xRD, xWD Low K/B/T Grade K/B/T Grade B/T Grade 20 MHz Min Max 30 MHz 33.3 MHz Frequency Dependence* Min Max Min Max Min Max Unit 25 MHz Min Max 37 24 0 –1 27 18 0 –1 27 15 14 0 8 16 26 17 18 10 13 20 13 12 6 12 15 11 37 + DT 24 + 5DT/8 9 5 27 + 7DT/8 15 + DT/2 9 0 2 1 24 17 11 0 –1 10 0 4 1 26 20 13 0 –1 12 0 K Grade 14 + DT/4 0 1 22 11 13 9 8 + 3DT/8 1 21 16 + DT/4 26 + DT/4 26 + 5DT/8 17 + 3DT/8 ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES *DT = tCK – 50 ns x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0. –18– REV. C ADSP-21020 CLKIN ADDRESS, SELECT t DAP DMPAGE, PMPAGE t DCKRL t DARL t RW DMRD, PMRD t HDA t DRLD t HDRH t DAD DATA t DRAK t RWR tSAK t DAAK DMACK, PMACK DMWR, PMWR Figure 10. Memory Read REV. C –19– t HAK ADSP-21020 Memory Write Parameter Timing Requirement: tDAAK xACK Delay from Address, Select tDWAK xACK Delay from xWR Low xACK Setup before CLKIN High tSAK tHAK xACK Hold after CLKIN High Switching Characteristic: tDAWH Address, Select to xWR Deasserted tDAWL Address, Select to xWR Low xWR Pulse Width tWW tDDWH Data Setup before xWR High tDWHA Address, Select Hold after xWR Deasserted tHDWH Data Hold after xWR Deasserted1 tDAP xPAGE Delay from Address, Select tDCKWL CLKIN High to xWR Low tWWR xWR High to xWR or xRD Low tDDWR Data Disable before xWR or xRD Low tWDE xWR Low to Data Enabled K/B/T Grade K/B/T Grade B/T Grade 20 MHz Min Max 30 MHz 33.3 MHz Frequency Dependency* Min Max Min Max Min Max Unit 25 MHz Min Max 27 15 18 10 14 0 12 0 37 11 26 23 28 7 20 18 1 0 0 –1 16 17 13 0 1 26 13 13 1 24 9 –1 K Grade 12 6 9 0 27 + 7DT/8 ns 15 + DT/2 ns 14 + DT/4 ns ns 21 5 16 14 18 3 15 13 37+ 15DT/16 11 + 3DT/8 26 + 9DT/16 23 + DT/2 ns ns ns ns 0 –1 0 –1 1 + DT/16 DT/16 16 + DT/4 26 + DT/4 17 + 7DT/16 ns ns ns ns ns 13 + 3DT/8 DT/16 ns ns 10 0 12 10 7 –1 1 22 9 5 11 8 1 21 5 –1 NOTES *DT = tC – 50 ns See “System Hold Time Calculation” in “Test Conditions” section for calculating hold times given capacitive and DC loads. x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0. –20– REV. C ADSP-21020 CLKIN ADDRESS, SELECT t DAP DMPAGE, PMPAGE t DAWH t DAWL DMWR, PMWR t DWHA tWW tWWR t DCKWL tWDE t HDWH t DDWH DATA t DDWR t DWAK t DAAK tSAK DMACK, PMACK DMRD, PMRD Figure 11. Memory Write REV. C –21– t HAK ADSP-21020 IEEE 1149.1 Test Access Port K/B/T Grade K/B/T Grade B/T Grade K Grade Parameter 20 MHz Min Max 25 MHz Min Max 30 MHz 33.3 MHz Frequency Dependency* Min Max Min Max Min Max Unit Timing Requirement: tTCK TCK Period tSTAP TDI, TMS Setup before TCK High tHTAP TDI, TMS Hold after TCK High tSSYS System Inputs Setup before TCK High tHSYS System Inputs Hold after TCK High tTRSTW TRST Pulse Width 50 5 6 7 9 200 40 5 6 7 9 160 33 5 6 7 9 132 Switching Characteristic: tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay from TCK Low 15 26 15 26 30 5 6 7 9 120 15 26 tCK 15 26 ns ns ns ns ns ns ns ns NOTES *DT = tC – 50 ns System Inputs = PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, CLKIN, IRQ3 0, RESET, FLAG3-0, BR. System Outputs = PMA23-0, PMS1-0, PMRD, PMWR, PMD47-0, PMPAGE, DMA31-0, DMS1-0, DMRD, DMWR, DMD39-0, DMPAGE, FLAG3-0, BG, TIMEXP. See the IEEE 1149.1 Test Access Port chapter of the ADSP-21020 User’s Manual for further detail. –22– REV. C ADSP-21020 t TCK TCK tSTAP t HTAP TMS,TDI t DTDO TDO tSSYS t HSYS SYSTEM INPUTS t DSYS SYSTEM OUTPUTS Figure 12. IEEE 1149.1 Test Access Port REV. C –23– ADSP-21020 TEST CONDITIONS Output Disable Time IOL Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, CL, and the load current, IL. It can be approximated by the following equation: t DECAY = TO OUTPUT PIN CL ∆V IL +1.5V 50pF* IOH *AC TIMING SPECIFICATIONS ARE CALCULATED FOR 100pF DERATING ON THE FOLLOWING PINS: PMA23–0, PMS1–0, PMRD, PMWR, PMPAGE, DMA31–0, DMS3–0, DMRD, DMWR, DMPAGE The output disable time (tDIS) is the difference between tMEASURED and tDECAY as shown in Figure 13. The time tMEASURED) is the interval from when the reference signal switches to when the output voltage decays ∆V from the measured output high or output low voltage. tDECAY is calculated with ∆V equal to 0.5 V, and test loads CL and IL. Figure 14. Equivalent Device Loading For AC Measurements (Includes All Fixtures) INPUT OR OUTPUT Output Enable Time Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 1.5V 1.5V Figure 15. Voltage Reference Levels For AC Measurements (Except Output Enable/Disable) Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate tDECAY using the above equation. Choose ∆V to be the difference between the ADSP-21020’s output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e. tHDWD for the write cycle). REFERENCE SIGNAL t MEASURED t DIS t ENA VOH (MEASURED) 2.0V VOH (MEASURED) –∆V VOH (MEASURED) OUTPUT VOL (MEASURED) +∆V 1.0V VOL (MEASURED) VOL (MEASURED) t DECAY OUTPUT STOPS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5 V. OUTPUT STARTS DRIVING Figure 13. Output Enable/Disable –24– REV. C ADSP-21020 Capacitive Loading 12 OUTPUT DELAY OR HOLD – ns Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these timing parameters should be derated. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for further information on derating of timing specifications. Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18 and 19 show how output delays vary with capacitance. Note that the graphs may not be linear outside the ranges shown. 11.19 10 8 1 6 5.34 4 2 2 – 0.89 NOMINAL 10 9.18 9 –1.86 –2 25 50 1 75 100 125 175 150 200 LOAD CAPACITANCE – pF NOTES: (1) OUTPUT PINS BG, TIMEXP (2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0 7 6 5 Figure 18. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) 3.95 4 2 3 2 1.46 1.31 1 OUTPUT DELAY OR HOLD – ns RISE TIME – ns (0.8V – 2.0V) 8 0 25 50 75 100 125 150 LOAD CAPACITANCE – pF 175 200 NOTES: (1) OUTPUT PINS BG, TIMEXP (2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0 Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature) 2.99 3 1 2 2.27 2 1 NOMINAL –1 – 1.70 –2 RISE TIME – ns (0.8V – 2.0V) – 2.24 4 –3 3.59 25 1 1.33 1 0 50 75 100 125 150 175 200 π LOAD CAPACITANCE – pF NOTES: (1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO (2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR Figure 17. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature) REV. C 100 125 150 175 200 Figure 19. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) 0.85 25 75 NOTES: (1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO (2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR 3.00 2 2 50 LOAD CAPACITANCE – pF 3 –25– ADSP-21020 ENVIRONMENTAL CONDITIONS Example: The ADSP-21020 is available in a Ceramic Pin Grid Array (CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much of the die heat is dissipated. The slug provides a surface for mounting a heat sink (if required). Estimate PEXT with the following assumptions: The commercial grade (K grade) ADSP-21020 is specified for operation at TAMB of 0°C to +70°C. Maximum TCASE (case temperature) can be calculated from the following equation: T CASE = T AMB + ( PD × θCA ) where PD is power dissipation and θCA is the case-to-ambient thermal resistance. The value of PD depends on your application; the method for calculating PD is shown under “Power Dissipation” below. θCA varies with airflow and with the presence or absence of a heat sink. Table IX shows a range of θCA values. Table IX. Maximum θCA for Various Airflow Values Airflow (Linear ft./min.) 0 100 200 300 CPGA with No Heat Sink 12.8°C/W 9.2°C/W 6.6°C/W 5.5°C/W NOTES θJC is approximately 1°C/W. Maximum recommended T J is 130°C. As per method 1012 MIL-STD-883. Ambient temperature: 25 °C. Power: 3.5 W. Power Dissipation Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data values involved. Internal power dissipation is calculated in the following way: PINT = IDDIN 3 VDD The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: 1) the number of output pins that switch during each cycle (O), 2) the maximum frequency at which they can switch (f), 3) their load capacitance (C), and 4) their voltage swing (VDD). It is calculated by: PEXT = O 3 C 3 VDD2 3 f The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobes can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but 2 DM and 2 PM selects can switch on each cycle. If only one bank is accessed, no select line will switch. • A system with one RAM bank each of PM (48 bits) and DM (32 bits). • • 32K 3 8 RAM chips are used, each with a load of 10 pF. Single-precision mode is enabled so that only 32 data pins can switch at once. • PM and DM writes occur every other cycle, with 50% of the pins switching. • The instruction cycle rate is 20 MHz (tCK = 50 ns) and VDD = 5.0 V. The PEXT equation is calculated for each class of pins that can drive: Pin Type # % Pins Switch 3 C 3f 3 VDD2 PEXT PMA PMS PMWR PMD DMA DMS DMWR DMD 15 2 1 32 15 2 1 32 5 MHz 5 MHz 10 MHz 5 MHz 5 MHz 5 MHz 10 MHz 5 MHz 25 V 25 V 25 V 25 V 25 V 25 V 25 V 25 V 50 0 — 50 50 0 — 50 68 pF 68 pF 68 pF 18 pF 48 pF 48 pF 48 pF 18 pF 0.064 W 0.000 W 0.017 W 0.036 W 0.045 W 0.000 W 0.012 W 0.036 W PEXT =0.210 W A typical power consumption can now be calculated for this situation by adding a typical internal power dissipation: PTOTAL = PEXT + (5 V 3 IDDIN (typ)) = 0.210 + 1.15 = 1.36 W Note that the conditions causing a worst case PEXT are different from those causing a worst case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Also note that it is not common for a program to have 100% or even 50% of the outputs switching simultaneously. Power and Ground Guidelines To achieve its fast cycle time, including instruction fetch, data access, and execution, the ADSP-21020 is designed with high speed drivers on all output pins. Large peak currents may pass through a circuit board’s ground and power lines, especially when many output drivers are simultaneously charging or discharging their load capacitances. These transient currents can cause disturbances on the power and ground lines. To minimize these effects, the ADSP-21020 provides separate supply pins for its internal logic (IGND and IVDD) and for its external drivers (EGND and EVDD). To reduce system noise at low temperatures when transistors switch fastest, the ADSP-21020 employs compensated output drivers. These drivers equalize slew rate over temperature extremes and process variations. A 1.8 kΩ resistor placed between the RCOMP pin and EVDD (+5 V) provides a reference for the compensated drivers. Use of a capacitor (approximately 100 pF), placed in parallel with the 1.8 kΩ resistor, is recommended. –26– REV. C ADSP-21020 All GND pins should have a low impedance path to ground. A ground plane is required in ADSP-21020 systems to reduce this impedance, minimizing noise. 2.435 (61.9) 0.590 (15.0) The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.1 µF ceramic). Keep each capacitor’s lead and trace length to the pins as short as possible. This low inductive path provides the ADSP-21020 with the peak currents required when its output drivers switch. The capacitors’ ground leads should also be short and connect directly to the ground plane. This provides a low impedance return path for the load capacitance of the ADSP-21020’s output drivers. 0.128 (3.25) 0.408 (10.4) 0.92 (23.4) BOTTOM VIEW If a VDD plane is not used, the following recommendations apply. Traces from the +5 V supply to the 10 EVDD pins should be designed to satisfy the minimum VDD specification while carrying average dc currents of [IDDEX/10 3 (number of EVDD pins per trace)]. IDDEX is the calculated external supply current. A similar calculation should be made for the four IVDD pins using the IDDIN specification. The traces connecting +5 V to the IVDD pins should be separate from those connecting to the EVDD pins. The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG test access port of the ADSP-21020 to monitor and control the target board processor during emulation. The EZ-ICE probe requires that CLKIN, TMS, TCK, TRST, TDI, TDO, and GND be made accessible on the target system via a 12-pin connector (pin strip header) such as that shown in Figure 20. The EZ-ICE probe plugs directly onto this connector for chip-on-board emulation; you must add this connector to your target board design if you intend to use the ADSP-21020 EZ-ICE. Figure 21 shows the dimensions of the EZ-ICE probe; be sure to allow enough space in your system to fit the probe onto the 12-pin connector. KEY (NO PIN 1) X CLKIN BTMS TMS BTCK TCK BTRST Figure 21. EZ-ICE Probe The 12-pin, 2-row pin strip header is keyed at the Pin 1 location –you must clip Pin 1 off of the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing is 0.1 3 0.1 inches. The tip of the pins must be at least 0.10 inch higher than the tallest component under the probe to allow clearance for the bottom of the probe. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. The length of the traces between the EZ-ICE probe connector and the ADSP-21020 test access port pins should be less than 1 inch. Note that the EZ-ICE probe adds two TTL loads to the CKIN pin of the ADSP-21020. The BMTS, BTCK, BTRST, and BTDI signals are provided so that the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the BXXX pins and the XXX pins as shown in Figure 20. If you are not going to use the test access port for board test, tie BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power up (through BTRST on the connector) or held low for proper operation of the ADSP-21020. TDI GND TDO TOP VIEW Figure 20. Target Board Connector for EZ-ICE Emulator (Jumpers In Place) REV. C 2.435 (61.9) ALL DIMENSIONS IN INCHES AND (mm) TRST BTDI 0.6 (15.2) RIBBON CABLE A low frequency bypass capacitor (20 µF tantalum) located near the junction of the IVDD and EVDD traces is also recommended. Target System Requirements For Use Of EZ-ICE Emulator 0.2 (5.1) RIBBON CABLE LENGTH = 60.0 INCHES –27– ADSP-21020 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U PMA17 PMA20 TMS EGND TCK EVDD RCOMP EGND PMACK EVDD PMWR EGND PMD44 EGND PMD40 PMD39 PMD35 PMD31 U T EGND PMA19 PMA23 PMS1 TRST DMWR DMACK CLKIN NC NC PMTS PMD45 PMD42 NC PMD37 PMD32 PMD30 PMD27 T S PMA11 PMA14 PMA18 PMA22 PMPAGE TDI DMTS DMRD NC PMRD PMD47 PMD43 PMD41 PMD36 PMD34 PMD28 PMD26 PMD21 S R EGND PMA10 PMA15 PMA16 PMS0 TDO IGND RESET IVDD PMD46 IGND PMD38 PMD33 PMD29 PMD25 PMD23 EGND R P PMA8 PMA9 PMA13 PMA12 PMD24 PMD22 PMD19 PMD18 P N EVDD PMA5 PMA6 PMA7 PMD20 PMD17 PMD16 EVDD N M PMA1 PMA4 PMA3 PMA2 PMD15 PMD14 PMD13 PMD12 M L EGND PMA0 TIMEXP IGND IGND PMD10 PMD11 EGND L K EVDD NC IRQ2 IRQ3 PMD6 PMD7 PMD8 PMD9 K IVDD PMD2 PMD5 EVDD J PMA21 ADSP-21020 TOP VIEW (PINS DOWN) J EVDD IRQ0 IRQ1 IVDD H EGND FLAG2 FLAG0 FLAG1 DMD1 DMD0 PMD3 PMD4 H G FLAG3 DMA1 DMA0 IGND IGND DMD3 NC EGND G F DMA2 DMA3 DMA4 DMA5 DMD9 DMD6 PMD0 PMD1 F E DMA6 DMA7 DMA8 DMA10 DMD13 DMD10 DMD2 EGND E D DMA9 DMA11 DMA12 DMA15 DMA19 DMA23 DMA27 IGND DMS0 IVDD DMD36 DMD31 DMD27 DMD22 DMD17 DMD11 DMD5 DMD4 D C DMA13 DMA14 DMA18 DMA20 DMA24 DMA28 DMA31 DMS1 NC DMD38 DMD35 DMD30 DMD28 DMD24 DMD20 DMD15 DMD8 DMD7 C B DMA16 DMA17 DMA21 DMA25 DMA26 DMA30 DMPAGE DMS3 DMD39 DMD37 DMD33 DMD32 DMD26 DMD25 DMD21 DMD18 DMD14 DMD12 B A BR BG DMA22 EGND DMA29 EVDD DMS2 EGND DMD34 EVDD DMD29 EGND DMD23 EVDD DMD19 EGND DMD16 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 –28– A 1 REV. C ADSP-21020 1 2 3 4 5 6 7 8 9 10 11 12 U PMD31 PMD35 PMD39 PMD40 EGND PMD44 EGND PMWR EVDD PMACK EGND RCOMP T PMD27 PMD30 PMD32 PMD37 NC PMD42 PMD45 PMTS NC NC CLKIN S PMD21 PMD26 PMD28 PMD34 PMD36 PMD41 PMD43 PMD47 PMRD NC R EGND PMD23 PMD25 PMD29 PMD33 PMD38 IGND PMD46 IVDD RESET P PMD18 PMD19 PMD22 N EVDD PMD16 M PMD12 L 14 15 EVDD TCK EGND TMS PMA20 PMA17 U DMACK DMWR TRST PMS1 PMA23 PMA19 EGND T DMRD DMTS TDI PMPAGE PMA22 PMA18 PMA14 PMA11 S IGND TDO PMS0 PMA21 PMA16 PMA15 PMA10 EGND R PMD24 PMA12 PMA13 PMA9 PMA8 P PMD17 PMD20 PMA7 PMA6 PMA5 EVDD N PMD13 PMD14 PMD15 PMA2 PMA3 PMA4 PMA1 M EGND PMD11 PMD10 IGND IGND TIMEXP PMA0 EGND L K PMD9 PMD8 PMD7 PMD6 ADSP-21020 IRQ3 IRQ2 NC EVDD K J EVDD PMD5 PMD2 IVDD BOTTOM VIEW (PINS UP) IVDD IRQ1 IRQ0 EVDD J H PMD4 PMD3 DMD0 DMD1 FLAG1 FLAG0 FLAG2 EGND H G EGND NC DMD3 IGND IGND DMA0 DMA1 FLAG3 G F PMD1 PMD0 DMD6 DMD9 DMA5 DMA4 DMA3 DMA2 F E EGND DMD2 DMD10 DMD13 DMA10 DMA8 DMA7 DMA6 E D DMD4 DMD5 DMD11 DMD17 DMD22 DMD27 DMD31 DMD36 IVDD DMS0 IGND DMA27 DMA23 DMA19 DMA15 DMA12 DMA11 DMA9 D C DMD7 DMD8 DMD15 DMD20 DMD24 DMD28 DMD30 DMD35 DMD38 NC DMS1 DMA31 DMA28 DMA24 DMA20 DMA18 DMA14 DMA13 C B DMD12 DMD14 DMD18 DMD21 DMD25 DMD26 DMD32 DMD33 DMD37 DMD39 DMS3 DMPAGE DMA30 DMA26 DMA25 DMA21 DMA17 DMA16 B DMD16 EGND DMD19 EVDD DMD23 EGND DMD29 EVDD DMD34 EGND DMS2 EVDD DMA29 EGND DMA22 BG BR A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A 1 REV. C –29– 13 16 17 18 ADSP-21020 PGA LOCATION G16 G17 F18 F17 F16 F15 E18 E17 E16 D18 E15 D17 D16 C18 C17 D15 B18 B17 C16 D14 C15 B16 A16 D13 C14 B15 B14 D12 C13 A14 B13 C12 H3 H4 E2 G3 D1 D2 F3 C1 C2 F4 E3 D3 B1 E4 B2 C3 A2 D4 B3 A4 C4 B4 D5 A6 C5 PIN NAME DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 DMA10 DMA11 DMA12 DMA13 DMA14 DMA15 DMA16 DMA17 DMA18 DMA19 DMA20 DMA21 DMA22 DMA23 DMA24 DMA25 DMA26 DMA27 DMA28 DMA29 DMA30 DMA31 DMD0 DMD1 DMD2 DMD3 DMD4 DMD5 DMD6 DMD7 DMD8 DMD9 DMD10 DMD11 DMD12 DMD13 DMD14 DMD15 DMD16 DMD17 DMD18 DMDl9 DMD20 DMD21 DMD22 DMD23 DMD24 PGA LOCATION B5 B6 D6 C6 A8 C7 D7 B7 B8 A10 C8 D8 B9 C9 B10 D10 C11 A12 B11 T13 S11 B12 S12 T12 L17 M18 M15 M16 M17 N17 N16 N15 P18 P17 R17 S18 P15 P16 S17 R16 R15 U18 S16 T17 U17 R14 S15 T16 F2 F1 J3 H2 H1 J2 K4 K3 K2 PIN NAME DMD25 DMD26 DMD27 DMD28 DMD29 DMD30 DMD31 DMD32 DMD33 DMD34 DMD35 DMD36 DMD37 DMD38 DMD39 DMS0 DMS1 DMS2 DMS3 DMWR DMRD DMPAGE DMTS DMACK PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMA16 PMA17 PMA18 PMA19 PMA20 PMA21 PMA22 PMA23 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PGA LOCATION K1 L3 L2 M1 M2 M3 M4 N2 N3 P1 P2 N4 S1 P3 R2 P4 R3 S2 T1 S3 R4 T2 U1 T3 R5 S4 U2 S5 T4 R6 U3 U4 S6 T6 S7 U6 T7 R8 S8 R13 T15 U8 S9 S14 T8 U10 A17 A18 H16 H15 H17 G18 J17 J16 K16 K15 R10 –30– PIN NAME PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMD16 PMD17 PMD18 PMD19 PMD20 PMD21 PMD22 PMD23 PMD24 PMD25 PMD26 PMD27 PMD28 PMD29 PMD30 PMD31 PMD32 PMD33 PMD34 PMD35 PMD36 PMD37 PMD38 PMD39 PMD40 PMD41 PMD42 PMD43 PMD44 PMD45 PMD46 PMD47 PMS0 PMS1 PMWR PMRD PMPAGE PMTS PMACK BG BR FLAG0 FLAG1 FLAG2 FLAG3 IRQ0 IRQ1 IRQ2 IRQ3 RESET PGA LOCATION L16 U12 T11 T14 R12 S13 U16 U14 H18 A3 A7 A11 A15 E1 G1 L1 L18 R1 R18 T18 U5 U7 U11 U15 D11 G4 G15 L4 L15 R7 R11 A5 A9 A13 J1 J18 N1 N18 U9 U13 K18 D9 J4 J15 R9 C10 S10 T10 T9 K17 T5 G2 PIN NAME TIMEXP RCOMP CLKIN TRST TD0 TDI TMS TCK EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND EGND IGND IGND IGND IGND IGND IGND IGND EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD IVDD IVDD IVDD IVDD NC NC NC NC NC NC NC REV. C ADSP-21020 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 223-Pin Ceramic Pin Grid Array e1 e1 j2 D TOP VIEW j1 h A B C D E F G H J K L M N P R S T U D A1 A L3 φb φ b1 e INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.084 0.102 2.11 2.59 A1 0.40 0.60 1.02 1.52 φb 0.018 TYP 0.46 TYP φb1 0.050 TYP 1.27 TYP D 1.844 1.876 46.84 47.64 e1 1.700 TYP 43.18 TYP e 0.100 TYP 2.54 TYP L3 h 0.172 0.188 0.020 TYP 4.37 4.77 0.500 TYP j1 1.125 1.147 28.56 29.14 j2 1.065 1.186 27.05 27.61 NOTE When socketing the CPGA package, use of a low insertion force socket is recommended. REV. C –31– 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ADSP-21020 Part Number* Ambient Temperature Range Instruction Rate (MHz) Cycle Time (ns) Package ADSP-21020KG-80 ADSP-21020KG-100 ADSP-21020KG-133 ADSP-21020BG-80 ADSP-21020BG-100 ADSP-21020BG-120 ADSP-21020TG-80 ADSP-21020TG-100 ADSP-21020TG-120 ADSP-21020TG-80/883B ADSP-21020TG-100/883B ADSP-21020TG-120/883B 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C 20 25 33.3 20 25 30 20 25 30 20 25 30 50 40 30 50 40 33.3 50 40 33.3 50 40 33.3 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array 223-Lead Ceramic Pin Grid Array C1601c–5–8/94 ORDERING GUIDE PRINTED IN U.S.A. *G = Ceramic Pin Grid Array. –32– REV. C