TI AFE4110B000YS

AFE4110
SLLSE48 – JANUARY 2012
www.ti.com
MIXED SIGNAL MICROCONTROLLER
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FEATURES
1
•
•
•
•
•
•
•
Ultra Low Supply-Voltage (ULV) Range
– 1.1V - 1.55V Unregulated Single Cell Battery
Operation (CPU, System Core, and Timers)
– 3mA 1.85V Internal Charge Pump for
External EEPROM (R/W), VDDIO, and
Internal LCD Controller
– 60µA 3.3V Regulated Charge Pump for LCD
Drive Pads
Low Power Consumption
– Active Mode (AM): 45µA/MHz (1.55V)
– Standby Mode (LPM3, LCD): < 25μA
– Deep Sleep Mode (LPM5):<0.4μA
– 8-Bytes Battery Backed RAM for Calibration
Retention
– Wakeup From Periodic Timer or External
Interrupt
– Wake-Up from LPM5 in 10ms, Wake-Up
from LPM4 in 5μs
16-Bit RISC Architecture
– Extended Instructions
– 125ns Instruction Cycle Time
Compact Clock System
– Internal Trimmable High Frequency Clock
Oscillator with Discrete Frequency
Selections Between 1MHz and 5.4MHz
– 20kHz Internal low Frequency Clock
Oscillator
– External Clock Input (Upto 8MHz)
– 32kHz Crystal Oscillator
Internal High Frequency Oscillator Frequency
Correction
– Facilitates Generation and Measurement of
Real Time Intervals Without a Clock Crystal
– Utilizes Factory Calibration (E-Fuse), S/W,
and a Single External 1MΩ Resistor
Integrated LCD Controller
– Drives 4-Mux, 3-Mux, 2-Mux, or Static Mode
LCDs
– Up to 48 (4x12) LCD Segments
Two 16-Bit Timer0_A3 with Three
Capture/Compare Registers
•
•
•
•
•
•
•
– Extended Input Multiplexer for High
Accuracy RC Discharge Measurement
ULV Analog Pool
– 8-Bit Analog-to-Digital Converter (ADC)
– 8-Bit Digital-to-Analog Converter (DAC)
– Programmable Comparator (COMP)
– Supply-Voltage-Monitoring (SVM)
– Internal Temperature Sensor
– Internal Voltage Reference
– 1V Regulated (LDO) Outputs
32-Bit Watch-Dog-Timer (WDT-A)
21-Configurable Analog I/O or Digital GPIO
Pads,
– 2-Power GPIO for 10mA VDD/1.85/3.6V
Buzzer Load
– 10-GPIO for VDDIO Operation with
VDD/1.85/3.6V Internal Level Shifting
– 11-GPIO for VDD Operation (1.1V - 1.55V)
– 4-Regulated 1V (LDO) Analog Outputs
– 1-250mV DAC Analog Output
– 6-Analog Comparator/ADC Inputs
SPI EEPROM Bootstrap Loader (AFE4110A)
Full Four Wire JTAG Debug Interface
Family Members Include:
– AFE4110B:
– 512B RAM Memory
– 16KB ROM (TI PSUC, Custom)
AFE4110A:
– 14KB RAM + 512B RAM
– 16KB ROM (TI DSUC,TI Bootloader)
55-Bonding Pads Available as Tested Wafers,
See the Ordering Information for Other
Options
APPLICATIONS
•
For any application requiring a full analog
signal chain and an LCD display driver such
as digital thermometers, pedometers,
thermostats, and other portable single alkaline
battery devices.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
AFE4110
SLLSE48 – JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The Texas Instruments MSP430 family of low-power mixed signal ASSPs consists of many devices featuring
different sets of peripherals targeted for various consumer medical applications. The AFE4110 CPU architecture
is based on the popular ultra low power Texas Instruments MSP430 RISC processor.
The AFE4110 configuration with two 16-bit timers, integrated 48-segment LCD driver, programmable Analog
Pool, supply voltage monitor and internal reference voltage source is particularly well suited for implementation of
low cost digital thermometers operating from a single cell SR60 battery. The capability to correct the on chip high
frequency oscillator output facilitates the generation and measurement of real time intervals. For many
applications, this capability allows system designers to eliminate a clock crystal from the system BOM.
ORDERING INFORMATION (1)
(1)
TA
ORDERABLE PART
0ºC to 70ºC
AFE4110B000YS
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
FUNCTIONAL BLOCK DIAGRAM, AFE4110
RST/NMI/SVMOUT
GND/Vss
VBAT
ACTIV
P3.6,P3.7
P1.0...P1.6,
P3.0...P3.5 VDDIO P2.0-P2.3
P4.0-P4.3
1.8V 1.0V
LF-OSC
P3.0
CLKIN,
XTIN
P3.1
XTOUT
HF-OSC
32XTL
ACLK
Clock
System
Power
Activation,
Reset
16KB
Int-Logic
ROM
Timer0_A3
ULV
Watchdog
WDTA
3 CC
3 CC
32/16-bit
Registers
Registers
I/O Port
VCC
SMCLK
I/O Port
Vcc/1.8V/
3.3V
JTAG,
SPI,
BUZZER
1V
LDO,
1.8V
Charge
Pump
MCLK
CPU &
Working
Registers
TMS, TCK,
TDI, TDO
4W-JTAG
Debug
Support
Brownout
Timer1_A3
CORE
Analog-Pool
ULV-Ref,
8-bit ADC,
8-Bit DAC,
Comparator
SVS
LCD
48
Segments
Vref
4COM X
12SEG
2
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ABSOLUTE MAXIMUM RATINGS (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VALUE
MIN
Voltage applied at VDD referenced to VSS (VAMR)
Voltage applied to any pin (references to VSS)
Diode current at any device pin
MAX
–0.3
1.8
V
–0.3
VDD + 0.3
V
–0.3
1.8
V
± 2.5
mA
150
°C
2000
V
(2)
Storage temparature range (3)
–55
ESD tolerance HBM
(1)
(2)
(3)
UNIT
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
RECOMMENDED OPERATING CONDITIONS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
VDD
Supply voltage during program execution
VSS
Supply voltage (GND reference)
TA
Operating free-air temperature
CVDD
Capacitor on VDD
fSYSTEM (1) (2)
(1)
(2)
TYP
1.1
MAX
UNIT
1.55
V
70
°C
0
0
V
470
VDD > 1.1 V
1
VDD > 1.5 V
4
nF
MHz
The AFE4110 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulsewidth of the
specified maximum frequency.
Modules may have a different maximum input clock specification.See the specification of the respective module in this data sheet.
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Active Mode Supply Current (Into VCC)
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IAM,1MHz
IAM,125kHz
IAM/MHz
(1)
(2)
TEST CONDITIONS
VDD
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz,
Program executes in RAM,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz,
Program executes in RAM,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz
Program executes in RAM
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz,
Program executes in RAM,
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fMCLK = fSMCLK : 1 to 5 MHz, fACLK = 20 kHz
Program executes in RAM, CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
TA
MIN
1.3 V
1.55 V
1.3 V
µA
74
70°C
µA
88
33
30°C
µA
37
1.3 V
1.55 V
UNIT
86
1.3 V
1.55 V
MAX
72
30°C
1.3 V
1.55 V
TYP
35
70°C
µA
40
30°C
µA/ MHz
45
All inputs are tied to 0 V or to VDD. Outputs do not source or sink any current.
Characterized with program executing typical data processing "Type2".
Low-Power Mode Supply Current (Into VCC)
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD
1.3 V
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0
ILPM0
1.55 V
1.3 V
1.55 V
1.3 V
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz
CPUOFF = 1, SCG0 = 1, SCG1 = 0, OSCOFF = 0
ILPM1
1.55 V
1.3 V
1.55 V
1.3 V
ILPM2,1MHz
fMCLK = fSMCLK = 1MHz, fACLK = 1MHz
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0
1.55 V
1.3 V
1.55 V
1.3 V
ILPM2,20kHz
fMCLK = fSMCLK = fACLK = 20 kHz
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0
1.55 V
1.3 V
1.55 V
1.3 V
ILPM3
fMCLK = fSMCLK = fACLK = 20 kHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0
1.55 V
1.3 V
1.55 V
1.3 V
ILPM4
fMCLK = fSMCLK = fACLK = 20 kHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1
1.55 V
1.3 V
1.55 V
(1)
(2)
4
TA
MIN
30°C
70°C
30°C
70°C
30°C
70°C
30°C
70°C
30°C
70°C
30°C
70°C
TYP
MAX
8.3
11
9.5
12
11
14
12
17
8.3
11
9.5
12
11
14
12
17
28
32
29
33
30
35
32
38
8.3
12
9.5
13
11
15
12
17
8.3
11
9.5
12
11
14
12
17
6
7.9
7.8
10
8.6
12
11
16
UNIT
µA
µA
µA
µA
µA
µA
Current for WDT clocked by ACLK included.
Current for Brownout included.
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Ports P1, P3 (except for P3.6, P3.7), RST, NMI, SVMOUT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
VOL
VIL
VIH
VHYS
CONDITIONS
MIN
VDD = 1.1 V, IOH = –1 mA (1) for ports P1, P3
VDD-0.25
VDD = 1.55 V, IOH = –1 mA (1) for ports P1, P3
VDD-0.15
VDD = 1.1 V, IOH = –300 µA (1) for ports P1, P3
VDD-0.15
UNIT
V
0.2
VDD = 1.55 V, IOL = 2.5 mA (2) for ports P1, P3
0.15
VDD = 1.1 V, IOL = 300 µA (2) for ports P1, P3
0.07
V
VDD = 1.55 V
0.3 x VDD
V
VDD = 1.1 V
0.25 x VDD
V
VDD = 1.55 V
0.7 x VDD
V
VDD = 1.55 V
0.75 x VDD
V
150
mV
VDD = 1.1V, CL = 15 pF || RL = 750Ω to Vss on VOH for ports P1, P3
75
VDD = 1.1 V, CL = 15 pF || RL = 320Ω to Vcc on VOL for ports P1, P3
75
VDD = 1.55 V, CL = 25 pF || RL= 1600Ω to Vss on VOH for ports P1, P3
75
VDD = 1.55 V, CL = 25 pF || RL= 600Ω to Vss on VOL for ports P1, P3
ns/V
75
IOH
VDD = 1.1 V – 1.55 V for ports P1, P3
–1
IOL
VDD = 1.1 V – 1.55 V for ports P1, P3
2.5
ILKG
VDD = 1.1 V – 1.55 V
tINT
P0.x; VDD = 1.1 V – 1.55 V
RPULL
For pullup:VIN = VSS; For pulldown: VIN = VDD for ports P1, P3
RRST
Pullup on RST, NMI, SVMOUT
REXT
External pull up resistor on RST terminal (optional)
CI
VIN = VSS or VDD
(1)
(2)
MAX
VDD = 1.1 V, IOL = 2.5 mA (2) for ports P1, P3
Intrinsic Hysteresis
Δt/Δv
TYP
mA
mA
±100
nA
200
ns
30
35
40
kΩ
30
35
40
kΩ
680
kΩ
7
pF
The maximum total current IOH, for all outputs combined should not exceed 5mA to hold the maximum voltage drop specified
The maximum total current IOL, for all outputs combined should not exceed 15mA to hold the maximum voltage drop specified
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Ports P2, P4 and Port 3.7, Port 3.6
1.1V < VDDIO < 3.3V over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)
PARAMETER
VOH
VOL
VIL
VIH
CONDITIONS
VDDIO - 0.25
VDDIO = 3.3 V, IOH = –1 mA (1)
VDDIO - 0.15
VDDIO = 1.1 V, IOH = –300 µA (1)
VDDIO - 0.15
TYP
UNIT
V
0.2
VDDIO = 3.3 V, IOL = 2.5 mA (2)
0.15
VDDIO = 1.1 V, IOL = 300 µA (2)
0.07
V
VDDIO = 3.3 V
0.3 x VDDIO
V
VDDIO = 1.1 V
0.25 x
VDDIO
V
VDDIO = 3.3 V
0.7 x VDDIO
VDDIO = 1.1 V
0.75 x VDDIO
VDDIO = 1.1 V – 3.3 V (positive going input threshold)
VIT–
VDDIO = 1.1 V – 3.3 V (negative going input threshold)
VHYS
Intrinsic Hysteresis
V
V
VILmax+VHYS
VIHmin
VILmax
VIHmin- VHYS
150
75
VDDIO = 1.1 V, CL = 15 pF || RL = 320Ω to VDD on VOL for ports P1,P2,P3
75
VDDIO = 3.3 V, CL = 25 pF || RL= 1600Ω to VSS on VOH for ports P1,P2,P3
75
VDDIO = 3.3 V, CL = 25 pF || RL= 600Ω to VSS on VOL for ports P1,P2,P3
V
V
mV
VDDIO = 1.1 V, CL = 15 pF || RL = 750Ω to VSS on VOH for ports P1,P2,P3
ns/V
75
IOH
VDDIO = 1.1 V – 3.3 V for ports P1,P2,P3
–1
IOL
VDDIO = 1.1 V – 3.3 V for ports P1,P2,P3
2.5
ILKG
VDDIO = 1.1 V – 3.3 V
tINT
P0.x; VDD = 1.1 V – 3.3 V
RPULL
For pullup:VIN = VSS; For pulldown: VIN = VDDIO for ports P1,P2,P3
30
RRST
Pullup on RST/NMI/SVMOUT
30
CI
VIN = VSS or VDDIO
(1)
(2)
MAX
VDDIO = 1.1 V, IOL = 2.5 mA (2)
VIT+
Δt/Δv
MIN
VDDIO = 1.1 V, IOH = –1 mA (1)
mA
mA
±100
nA
200
ns
35
40
kΩ
35
40
kΩ
7
pF
The maximum total current IOH, for all outputs combined should not exceed 5mA to hold the maximum voltage drop specified
The maximum total current IOL, for all outputs combined should not exceed 15mA to hold the maximum voltage drop specified
Ports P3.6, P3.7 (High Current Buzzer)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
VOL
Δt/Δv
CONDITIONS
MIN
VDDIO = 1.1 V, IOH = –10 mA
VDDIO-0.15
VDDIO = 3.3 V, IOH = –10 mA
VDDIO-0.15
MAX
0.2
VDDIO = 3.3 V, IOL = 10 mA
0.15
VDDIO = 1.1V, CL = 15 pF || RL = 750Ω to VSS on VOH
75
VDDIO = 1.1 V, CL = 15 pF || RL = 320Ω to VDD on VOL
75
VDDIO = 1.55 V, CL = 25 pF || RL= 1600Ω to VSS on
75
VDDIO = 1.55 V, CL = 25 pF || RL= 600Ω to VSS on
75
VDDIO = 1.1 V – 3.3 V
–10
IOL
VDDIO = 1.1 V – 3.3 V
10
ILKG
VDDIO = 1.1 V – 3.3 V
tINT
P0.x; VDD = 1.1 V – 3.3 V
RPULL
Only pulldown implemented: VIN = VDDIO
CI
VIN = VSS or VDD
ns/V
mA
35
7
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V
mA
±100
nA
40
kΩ
200
30
UNIT
V
VDDIO = 1.1 V, IOL = 10 mA
IOH
6
TYP
ns
pF
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High Frequency – OSCILLATOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
fHFOSC
VDD = 1.1 V – 1.55 V (untrimmed)
fHFOSC
VDD = 1.1 V – 1.55 V (trimmed)
Duty Cycle
VDD = 1.1 V – 1.55 V
tSTART
VDDC = 1.1 V – 1.55 V
ΔfDCO/ΔT
VDD = 1.1 V – 1.55 V; fDCO = 4 MHz
±0.07
ΔfDCO/VDD
VDD = 1.1 V – 1.55 V; fDCO = 4 MHz
±1
ΔfDCO/CALSTEP
VDD = 1.1 V – 1.55 V; fDCO = 4 MHz; ±64 calibration steps
IOP
VDD = 1.1 V – 1.55 V; fDCO = 4 MHz
25
µA
IOP
VDD = 1.1 V – 1.55 V; fDCO = 1 MHz
22
µA
4
5
7
MHz
4.1
4.5
4.8
MHz
45%
50%
55%
µs
20
0.1
%/°C
%/V
1
4
%/Step
Low Frequency – OSCILLATOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
TYP
MAX
UNIT
fLFO
PARAMETER
VDD = 1.1 V – 1.55 V
CONDITIONS
6
20
45
kHz
Duty Cycle
VDD = 1.1 V – 1.55 V
45%
50%
55%
tSTART
VDD = 1.1 V – 1.55 V
IOP
VDDC = 1.1 V – 1.55 V; fLFO = 20 kHz
µs
500
600
nA
32 kHz Crystal – OSCILLATOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
fLFO
VDD = 1.1 V – 1.55 V
Duty Cycle
VDD = 1.1 V – 1.55 V
tSTART
VDDC = 1.1 V – 1.55 V
IOP
VDD = 1.1 V – 1.55 V
MIN
TYP
45%
50%
MAX
UNIT
32
kHz
55%
200
mS
2
µA
CP_1P8 Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Start-up time
TYP
MAX
UNIT
1.55
V
3
V
3
mA
5mS
Supply voltage battery input
1.1
Output voltage, VO
1.8 x VBAT
No load voltage
VBAT = 1.55 V
Max load voltage
VBAT = 1.2 V
1.85
Max load
CP18 = 10 nF
0.01
Charge pump efficiency
V
70%
Clocking frequency
4
MHz
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Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
VBOR(Start)
MIN
TYP
MAX
490
UNIT
mV
V(BOR_IT+)
VDD rising; dVDD / dt < 3V/s
1095
1150
mV
V(BOR_IT–)
VDD falling; dVDD / dt < 3V/s
860
900
mV
Vhys(BOR)
VMARGIN
200
VMARGIN = V(BOR-IT-) – VCRIT; T = 0-70°C
40
mV
3000 (1)
tdBOR
VDD = 1.1 V – 1.55 V
IOP
(1)
mV
500
µs
nA
Depends on the voltage ramp in the system (actually a maximum typical value).
A-POOL, External Reference Source
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF
CONDITIONS
MIN
VDD = 1.1 V – 1.55 V for ADC / DAC operation
100
VDD = 1.1 V – 1.55 V ADC / DAC not operational
IREF
VDD = 1.1 V – 1.55 V
CREF
REFON = 0
TYP
0
MAX
UNIT
475
mV
VDD
20
V
µA
3
50
pF
A-POOL, Built-In Reference Source
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
VREF
VDD = 1.1 V – 1.55 V (±1.5%; overall 3%)
IREF
VDD = 1.1 V – 1.55 V
CREF
REFON = 1
TREF
VDD = 1.1 V – 1.55 V ( ΔV/ΔT×VREF referenced to 25°C)
tsettle
VDD = 1.1 V – 1.55 V; REFON = 1; CREF = CREF(max)
IOP
VDD = 1.1 V – 1.55 V; REFON = 1; CREF = CREF(max)
MIN
TYP
MAX
256 ±3%
mV
µA
10
20
UNIT
50
pF
±250
ppm/°C
900
µs
µA
50
A-POOL, Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ISENSOR
VCC = 1.1 V – 1.55 V
TCSENSOR
VCC = 1.1 V – 1.55 V; 0-70°C ( ΔV/ΔT referenced to 30°C)
464
µV/°C
VOFFSET25
VCC = 1.1 V – 1.55 V at TA = 30°C
179
mV
tSETTLE
VCC = 1.1 V – 1.55 V (before start of conversion)
VSENSOR (1)
VCC = 1.1 V – 1.55 V; 0-70°C
(1)
8
µA
2
15
179
µs
mV
The following formula can be used to calculate the temperature sensor output voltage
VSENSOR = VOFFSET25 + TCSENSOR × (TA = 30°C)
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A-POOL, Input Voltage Dividers
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
±2%
any Rx across switches and internal supply voltage divider (by 4, by 8)
on A0/A1 ; VA0/VA1 = 0.5 V; ADIV0/ADIV1 = 1 (500 mV range)
RIN
ΔIVDD
UNIT
±1.5%
any Rx in dividers
ΔRx/Rx
MAX
120
200
300
on A2/A3 ; VA2/VA3 = 0.5 V; ADIV2/ADIV4 = 1 (1 V range)
80
133
190
on A2/A3 ; VA2/VA3 = 0.5 V; ADIV2 + ADIV3/ADIV4 + ADIV5 = 1 (2 V range)
70
114
150
ADIV7 = 1 (supply voltage divider on)
kΩ
µA
2
A-POOL, DAC-8
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
VREFEXT
VDD = 1.1 V – 1.55 V
tSETTLE
On ±1 LSB steps (6τ); VDD = 1.1 V – 1.55 V; VREFEXT(typ); CVREF(min)
MIN
TYP
mV
µs
14
µs
VDD = 1.1 V – 1.55 V; VREFEXT(typ); CVREF(min); (add ±7 mV
for VOUT offset (1))
ED
(1)
UNIT
2
Between all codes >20 on AOUT (6τ); VDD = 1.1 V – 1.55 V; VREFEXT(typ);
CVREF(min)
EI
MAX
256
±3
LSB
±1
LSB
MAX
UNIT
275
mV
This offset can be compensated using proper software.
A-POOL, Comparator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
VDD = 1.1 V – 1.55 V
VIN
tpd
TYP
0
Overdrive = 20 mV
0.5
Overdrive = 5 mV
0.5
Overdrive = 1 mV
1
µs
A-POOL, AOUT Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
| ILOAD |
VDD = 1.1 V – 1.55 V; CLOAD = 25 pF; VOUT >50mV
5
| ILOAD |
VDD = 1.1 V – 1.55 V; CLOAD = 25 pF; VOUT >20mV
2
tSETTLE
VDD = 1.1 V – 1.55 V; CLOAD = 25 pF; ±1% (6τ) (for AOUT 20-256 mV)
TYP
MAX
UNIT
µA
µA
µs
4
A-POOL, ADC-8 Counter
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fCNT
VDD = 1.1 V – 1.55 V
tCONV
Full conversion (all codes) at fCNT = 1MHz
MIN
TYP
MAX
UNIT
1
MHz
µs
256
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOP
Operating temperature 0-70°C, fCPU = 1MHz
1.1
V
VRET
Operating temperature 0-70°C (tracks BOL level)
700
mV
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PIN DESIGNATION, AFE4110
PAD#
PAD X [µ]
PAD Y [µ]
PAD#
PAD X [µ]
PAD Y [µ]
1
2108.3
987.3
28
96.0
23.6
2
1994.6
987.3
29
171.0
23.6
3
1908.6
987.3
30
246.0
23.6
4
1824.2
987.3
31
321.0
23.6
5
1749.2
987.3
32
396.0
23.6
6
1674.2
987.3
33
471.0
23.6
7
1599.2
987.3
34
546.0
23.6
8
1521.8
987.3
35
621.0
23.6
9
1446.8
987.3
36
696.0
23.6
10
1371.8
987.3
37
771.0
23.6
11
1296.8
987.3
38
846.0
23.6
12
1221.8
987.3
39
921.0
23.6
13
1146.8
987.3
40
996.0
23.6
14
1071.8
987.3
41
1071.0
23.6
15
996.8
987.3
42
1146.0
23.6
16
921.8
987.3
43
1221.0
23.6
17
846.8
987.3
44
1296.0
23.6
18
771.8
987.3
45
1371.0
23.6
19
696.8
987.3
46
1446.0
23.6
20
621.8
987.3
47
1521.0
23.6
21
546.8
987.3
48
1596.0
23.6
22
471.8
987.3
49
1671.0
23.6
23
396.8
987.3
50
1746.0
23.6
24
321.8
987.3
51
1821.0
23.6
25
246.8
987.3
52
1896.0
23.6
26
171.8
987.3
53
1971.0
23.6
27
96.8
987.3
54
2046.0
23.6
55
2121.0
23.6
10
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PIN FUNCTIONS
PIN
NAME
NO.
I/O (1)
DESCRIPTION
P3.0/XTI/EXCLK/TA1.CCI1A1
1
I/O
General-purpose digital I/O
32 kHz Crystal Input
External Clock Input
Timer1_A3 CCR1A1 capture: CCI1A1 input, compare
P3.1/XTO/TSCLK/TA1.CCI1A2/
ACTSEN/CMP
2
I/O
General-purpose digital I/O
32 kHz Crystal Out
Test Clock Input
Timer1_A3 CCR1A2 capture: CCI1A2 input, compare
Activation Sense Output
Comparator Out
VSS/GND
3
Power
Analog and Digital Power Supply Ground Reference
P3.4/TA0.1/TA1.1/TA1.0/TA1.CCI2A2
4
I/O
General-purpose digital I/O
Timer0_A3 Out1 output
Timer1_A3 Out1 output
Timer1_A3 Out0 output
Timer1_A3 CCR2A2 capture: CCI2A2 input, compare
P3.5/TA0.1/TA1.1/TA1.0/TA1.CCI2A3
5
I/O
General-purpose digital I/O
Timer0_A3 Out1 output
Timer1_A3 Out1 output
Timer1_A3 Out0 output
Timer1_A3 CCR2A3 capture: CCI2A3 input, compare
RST/NMI/SVMOUT
6
I/O
Reset input active low
Non-maskable interrupt input
SVM Output
P3.6/
TA0.0/TA0.1/TA0.2/TA0.0N/TA0.1N/TA0.2N/
TA1.CCI1A3/
TA1.1/BOR/ACTSEN/LFOSC/CP18OK
7
I/O
10mA General-purpose digital I/O
Timer0_A3 Out0 output
Timer0_A3 Out1 output
Timer0_A3 Out2 output
Timer0_A3 Out0# output
Timer0_A3 Out1# output
Timer0_A3 Out2# output
Timer1_A3 CCR1A3 capture: CCI1A3 input, compare
Timer1_A3 Out1 output
BOR Out
Activation Sense Output
LFOSC Out
CP 1.8V OK Out
P3.7/
TA0.0/TA0.1/TA0.2/TA0.0N/TA0.1N/TA0.2N/
TA1.CCI2A1/HFOSC/LCDCPCLK/
LCDFCLK/ 1KCLK/LCDCMP
8
I/O
10mA General-purpose digital I/O
Timer0_A3 Out0 output
Timer0_A3 Out1 output
Timer0_A3 Out2 output
Timer0_A3 Out0# output
Timer0_A3 Out1# output
Timer0_A3 Out2# output
Timer1_A3 CCR2A1 capture: CCI2A1 input, compare
LCD Charge Pump Clock Out
LCD Frame Clock Out
1 kHz Activation Clock Out
LCD Voltage Comparator Out
VDDIO
9
Power
TCK/P2.0/TA1.2/TA1.1/CxOUT
10
I/O
(1)
Port2.x, Port4.x, Port3.6 and Port3.7 Positive Power supply 1.1V-3.3V
JTAG Test clock
General-purpose digital I/O
Timer1_A3 Out2 output
Timer1_A3 Out1 output
CxOUT digital out from A-Pool
I = input, O = output, N/A = not available on this package offering.
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O (1)
DESCRIPTION
TMS/P2.1/ EXT_CLK/TA0.1/TA0.2
11
I/O
JTAG Test mode selec1
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
XTAL_CLK or EXT_CLK monitor out
TDI/P2.2/HF_CLK/CxOUT/TA1.0/
12
I/O
JTAG Test data input
General-purpose digital I/O
Timer1_A3 Out0 output
CxOUT digital out from A-Pool
HF_CLK out
TDO/P2.3/LF_CLK/TA0.2
13
I/O
JTAG Test data output
General-purpose digital I/O
Timer0_A3 Out2 output
LF_CLK Out
P4.0/TA0.2/TA1.2/ACLK/ATEST/SPI_CS
14
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
ACLK output
Analog Test Multiplexer Out
SPI Chip Select
P4.1/TA0.2/TA1.2/SMCLK/SPI_MOSI
15
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
SMCLK output
SPI Serial IN
P4.2/ TA0.2/TA1.2/MCLK/SPI_CLK
16
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
MCLK output
SPI Clock Out
P4.3/ TA0.2/TA1.2/1KOSC//SPI_MISO
17
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
1 kHz Activation Oscillator Out
SPI Serial Out
GNDIO
18
Power
PX.X GND
LCD_ECOM.0
19
Analog
LCD_E Common-0 , 0V – 3.4V
LCD_ECOM.1
20
Analog
LCD_E Common-1 , 0V – 3.4V
LCD_ECOM.2
21
Analog
LCD_E Common-2 , 0V – 3.4V
LCD_ECOM.3
22
Analog
LCD_E Common-3 , 0V – 3.4V
LCD_ESEG.0
23
Analog
LCD_E Segment-0 , 0V – 3.4V
LCD_ESEG.1
24
Analog
LCD_E Segment-1 , 0V – 3.4V
LCD_ESEG.2
25
Analog
LCD_E Segment-2 , 0V – 3.4V
LCD_ESEG.3
26
Analog
LCD_E Segment-3 , 0V – 3.4V
LCD_ESEG.4
27
Analog
LCD_E Segment-4 , 0V – 3.4V
VSS/GND
28
Power
Analog and Digital Power Supply Ground Reference
LCD_ESEG.5
29
Analog
LCD_E Segment-5 , 0V – 3.4V
LCD_ESEG.6
30
Analog
LCD_E Segment-6 , 0V – 3.4V
LCD_ESEG.7
31
Analog
LCD_E Segment-7 , 0V – 3.4V
LCD_ESEG.8
32
Analog
LCD_E Segment-8 , 0V – 3.4V
LCD_ESEG.9
33
Analog
LCD_E Segment-9 , 0V – 3.4V
LCD_ESEG.10
34
Analog
LCD_E Segment-10 , 0V – 3.4V
LCD_ESEG.11
35
Analog
LCD_E Segment-11 , 0V – 3.4V
12
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O (1)
DESCRIPTION
LCD_EHVCAP
36
Analog
LCD_E HV Charge Pump Ext Capacitor to GND, 3.4V
CP18CAP
37
Analog
Minimum 1.8V Charge pump Ext capacitor C to VSS
CP1P8_C2_IN
38
Analog
1.8V Charge pump Ext capacitor B for 2mA drive
CP1P8_C2_OUT
39
Analog
1.8V Charge pump Ext capacitor B for 2mA drive
CP1P8_C1_IN
40
Analog
1.8V Charge pump Ext capacitor A for 2mA drive
CP1P8_C1_OUT
41
Analog
1.8V Charge pump Ext capacitor A for 2mA drive
VPP
42
Power
Factory programming voltage. VPP must be tied to VDD in normal use
mode.
P1.0/TA0.2/TA0.1/TA1.2/LDO1/TA0.CCI1B0/
TA0.CCI2B0/A2
43
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
LDO 1V Out
Timer0_A3 CCR1B0 capture: CCI1B0 input, compare
Timer0_A3 CCR2B0 capture: CCI2B0 input, compare
Analog input A2 – A-Pool
P1.1/TA0.2/TA0.1/TA1.2/LDO1/TA0.CCI1A1/
TA0.CCI2A1/A1
44
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
LDO 1V Out
Timer0_A3 CCR1A1 capture: CCI1A1 input, compare
Timer0_A3 CCR2A1 capture: CCI2A1 input, compare
Analog input A1 – A-Pool
P1.2/TA0.2/TA0.1/TA1.2/AOUT/
TA0.CCI1A2/TA0.CCI2A2/A3
45
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
Analog Out - A-Pool
Timer0_A3 CCR1A2 capture: CCI1A2 input, compare
Timer0_A3 CCR2A2 capture: CCI2A2 input, compare
Analog input A3 – A-Pool
P1.3/TA0.2/TA0.1/TA1.2/REFOUT/
TA0.CCI1A3/TA0.CCI2A3/A3
46
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
Vref Out – A-Pool
Timer0_A3 CCR1A3 capture: CCI1A3 input, compare
Timer0_A3 CCR2A3 capture: CCI2A3 input, compare
Analog input A3 – A-Pool
P1.4/TA0.2/TA0.1/TA1.2/LDO1/
TA0.CCI1B1/TA0.CCI2B1/A0
47
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
LDO 1V Out
Timer0_A3 CCR1B1 capture: CCI1B1 input, compare
Timer0_A3 CCR2B1 capture: CCI2B1 input, compare
Analog input A0 – A-Pool
P1.5/TA0.2/TA0.1/TA1.2/LDO1/TA0.CCI1B2/
TA0.CCI2B2
48
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
Timer0_A3 CCR1B2 capture: CCI1B2 input, compare
Timer0_A3 CCR2B2 capture: CCI2B2 input, compare
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O (1)
DESCRIPTION
P1.6/TA0.2/TA0.1/TA1.2/TA1.CCI1B0/
TA1.CCI2B0
49
I/O
General-purpose digital I/O
Timer0_A3 Out2 output
Timer0_A3 Out1 output
Timer1_A3 Out2 output
Timer1_A3 CCR1B0 capture: CCI1B0 input, compare
Timer1_A3 CCR2B0 capture: CCI2B0 input, compare
P3.3/ TA0.1/TA1.1/TA1.0/A0/LDO1
50
I/O
General-purpose digital I/O
Timer0_A3 Out1 output
Timer1_A3 Out1 output
Timer1_A3 Out0 output
LDO 1V Out
Analog input A0 – A-Pool
P3.2/ TA0.1/TA1.1/TA1.0
51
I/O
General-purpose digital I/O
Timer0_A3 Out1 output
Timer1_A3 Out1 output
Timer1_A3 Out0 output
ACTIVE
52
I
Sleep Mode (LPM5) activation pin
VBAT
53
Power
Battery Power, Switched from VDD
VSS/GND
54
Power
Analog and Digital Power Supply Ground Reference
VDD
55
Power
Analog and Digital Power Supply
14
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Memory Organization
•
•
•
AFE4110 manufactured in 2 memory configurations
AFE4110A – Application Development Device
– 14KB Development RAM
– 512B Application RAM
– 2KB Development Start Up Code ROM
– 14KB Boot Loader ROM
AFE4110B – Custom Masked ROM Device
– 512B Application RAM
– 2KB Production Start Up Code ROM
– 14KB Custom Masked ROM
AFE4110A
0xFFFF
Development
RAM
14KB
0xC800
0xC000
TI ROM
(DSUC + APIs)
2KB
AFE4110B
0xFFFF IVECS
0xFFDF
Custom ROM
14KB
0xC800
0xC000
32B
TI ROM
(PSUC + APIs)
2KB
0x55FF Loader
TI Loader
0x1E00
14KB
14KB
0x1DFF App RAM
App RAM
256B
0x1D00
0x1C80
App LRAM
0x1C00 Cal-RAM
256B
0x1D00
App LRAM
128B
0x1C80
128B
0x1C00 Cal-RAM 128B
128B
0x1000
0x1000
0x0 Peripherals
0x0 Peripherals
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INSTRUCTION SET
SHORT-FORM DESCRIPTION
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 1 shows examples of the three
types of instruction formats; the address modes are
listed in Table 2.
CPU
The AFE4110 is based on an MSP430 CPU core with
a 16-bit RISC architecture that is highly transparent to
the application. All operations, other than
program-flow instructions, are performed as register
operations in conjunction with seven addressing
modes for source operand and four addressing
modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD
R4, R5
R4 + R5 → R5
Single operands, destination only
e.g. CALL
R8
PC → (TOS), R8 → PC
Relative jump, un/conditional
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
D (2)
SYNTAX
EXAMPLE
Register
●
●
MOV Rs,Rd
MOV R10, R11
R10 → R11
Indexed
●
●
MOV X(Rn), Y(Rm)
MOV 2(R5), 6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
●
●
MOV EDE, TONI
Absolute
●
●
MOV & MEM, and TCDAT
Indirect
●
MOV at Rn, Y(Rm)
MOV at R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
●
MOV at Rn+,Rm
MOV at R10+, R11
M(R10) → R11
R10 + 2 → R10
Immediate
●
MOV at 45,TONI
MOV #45, TONI
#45 → M(TONI)
(1)
(2)
16
S
(1)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source
D = destination
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Operation Modes
The AFE4110 has one active mode and six software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode AM;
– All clocks are active
• Low-power mode 0 (LPM0);
– CPU is disabled
– ACLK and SMCLK remain active for all sources
– MCLK is disabled
• Low-power mode 1 (LPM1);
– CPU is disabled
– ACLK and SMCLK remain active (for LF-Osc and CLKIN as source; HF-Osc is mapped to LF-Osc as
source)
– MCLK is disabled
• Low-power mode 2 (LPM2);
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK remains active for all sources
• Low-power mode 3 (LPM3);
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK remains active (for LF-Osc and CLKIN as source; HF-Osc is mapped to LF-Osc as source)
• Low-power mode 4 (LPM4);
– CPU is disabled
– ACLK is disabled
– MCLK is disabled
– Oscillators are stopped (exclude Activation Block 1kHz local oscillator)
• Low-power mode 5 (LPM5);
– CPU core and peripherials are powered off (Application and Calibration RAM contents are not retained.)
– Activation Block, 1kHz local oscillator, and 8 bytes RAM remain active
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh – 0FFE0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
System Reset
Power-Up
External Reset
Watchdog
WDTIFG(1)
Reset
0x0FFFE
14, highest
System NMI
Vacant memory access
SVMIFG, VMAIFG (1)
(Non)maskable
0x0FFFC
13
User NMI
NMI
NMIIFG (1)
(Non)maskable
0x0FFFA
12
Timer1_A3
Timer1_A3
TA1CCR0 CCIFG (3)
TA1CCR1 CCIFG
TA1CCR2 CCIFG
TA1IFG (1) (3)
Maskable
Maskable
0x0FFF8
0x0FFF6
11
10
Watchdog Timer_A Interval Timer Mode
WDTIFG
Maskable
0x0FFF4
9
A-Pool
CxIFG
Maskable
0x0FFF2
8
I/O Port P1
P1IFG.0 to P1IFG.6 (1)
Maskable
0x0FFF0
7
Timer0_A3
TA0CCR0 CCIFG (3)
Maskable
0x0FFEE
6
Timer0_A3
TA0CCR1 CCIFG
TA0CCR1 CCIFG
TA0IFG (1) (3)
Maskable
0x0FFEC
5
I/O Port P2
P2IFG.0 to P2IFG.3 (1)
(2)
(3)
(3)
Maskable
0x0FFEA
4
P3IFG.0 to P3IFG.7
(1) (3)
Maskable
0x0FFE8
3
I/O Port P4
P4IFG.0 to P4IFG.3
(1) (3)
Maskable
0x0FFE6
2
LCD Controller
LCDFRMIFG,
LCDBLKOFFIFG,
LCDBLKONIFG,
LCDNOCAPIFG
Maskable
0x0FFE4
1
Muxed with P3.6
Maskable
0x0FFE8
3
Muxed with P3.7
Maskable
0x0FFE8
3
Muxed with P3.4
Maskable
0x0FFE8
3
Muxed with P3.5
Maskable
0x0FFE8
3
Muxed with P3.2
Maskable
0x0FFE8
3
Muxed with P3.3
Maskable
0x0FFE8
3
I/O Port P3
The Following Interrupts are multiplexed on I/O Port P3 interrupts
Activation Sense (4)
CP 1p8 Valid (4)
(5)
(5)
Activation sleep counter timeout
(4) (5)
CP 1p8 comparator out (4) (5)
LCD CP comparator out
APOOL comparator out
(1)
(2)
(3)
(4)
(5)
18
(4) (5)
(4)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the
individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
No additional synchronization mechanisms beyond standard MSP430 interrupt synchronization
Interrupt Signal is directly connoted without a de-glitcher mechanism.
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Special Function Registers (SFRs)
The AFE4110 SFRs are located in the lowest address space and can be accessed via word or byte formats.
Other SFR registers documented in Texas Instruments MSP430x5xx "Compact SYS Module User's Guide"
(SLAU321).
Legend
rw:
Bit can be read and written.
rw-0,1:
Bit can be read and written. It is reset or set by PUC
rw-(0,1):
Bit can be read and written. It is reset or set by POR.
rw-[0,1]:
Bit can be read and written. It is reset or set by BOR.
SFR bit is not present in device
SFRIE1, SFRIE1_L, SFRIE1_H, Interrupt Enable Register
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
SVMIE
r0
r0
r0
r0
r0
r0
r0
rw-0
7
6
5
4
3
2
1
0
JMBOUTIE
JMBINIE
–
NMIIE
VMAIE
–
OFIE
WDTIE
rw-0
rw-0
r0
rw-0
rw-0
r0
rw-0
rw-0
Reserved
Bits 15 – 9
Reserved. Read back as 0
SVMIE
Bit 8
SVM interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
JMBOUTIE
Bit 7
JTAG mailbox output interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
JMBINIE
Bit 6
JTAG mailbox input interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
Reserved
Bit 5
Reserved. Reads back as 0
NMIIE
Bit 4
NMI pin interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
VMAIE
Bit 3
Vacant memory access interrupt enable flag.
0 interrupts disabled
1 interrupts enabled
Reserved
Bit 2
Reserved. Reads back as 0
OFIE
Bit 1
Oscillator fault interrupt enable flag. 0 interrupts disabled 1 interrupts enabled
WDTIE
Bit 0
Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is
not necessary to set this bit for watchdog mode. Because other bits in ~IE1 may be used for other
modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than
MOV.B or CLR.B instruction
0 interrupts disabled
1 interrupts enabled
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SFRIFG1, SFRIFG1_L, SFRIFG1_H, Interrupt Flag Register
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
SVMIFG
r0
r0
r0
r0
r0
r0
r0
rw-0
7
6
5
4
3
2
1
0
JMBOUTIFG
JMBINIFG
–
NMIIFG
VMAIFG
–
OFIFG
WDTIFG
rw-0
rw-0
r0
rw-0
rw-0
r0
rw-0
rw-0
Reserved
Bits 15 – 9
Reserved. Read back as 0
SVMIFG
Bit 8
SVM interrupt flag. This bit signals that the A-POOL comparator signaled an SVM event either
low voltage or high voltage depending on setup
0 no interrupt pending
1 interrupt pending
JMBOUTIFG
Bit 7
JTAG mailbox output interrupt flag
0 no interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically
when JMBO0 has been written by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is
cleared automatically when both JMBO0 and JMBO1 have been written by the CPU. This bit is
also cleared when the associated vector in SYSSNIV has been read
1 interrupt pending, JMBO registers are ready for new messages. In 16-bit mode
(JMBMODE=0) JMBO0 has been received by JTAG. In 32-bit mode (JMBMODE=1) , JMBO0
and JMBO1 have been received by JTAG
JMBINIFG
Bit 6
JTAG mailbox input interrupt flag
0 no interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically
when JMBI0 is read by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared
automatically when both JMBI0 and JMBI1 have been read by the CPU. This bit is also cleared
when the associated vector in SYSSNIV has been read
1 interrupt pending, a message is waiting in the JMBIN registers. In 16-bit mode (JMBMODE =
0) when JMBI0 has been written by JTAG. In 32 bit mode (JMBMODE = 1) when JMBI0 and
JMBI1 have been written by JTAG
Reserved
Bit 5
Reserved. Reads back as 0
NMIIFG
Bit 4
NMI pin interrupt flag
0 no interrupt pending
1 interrupt pending
VMAIFG
Bit 3
Vacant memory access interrupt flag
0 no interrupt pending
1 interrupt pending
Reserved
Bit 2
Reserved. Reads back as 0
OFIFG
Oscillator fault interrupt flag
0 no interrupt pending
1 interrupt pending
WDTIFG
20
Bit 0
Watchdog timer interrupt flag. In watchdog mode, WDTIFG remains set until reset by software.
In interval mode, WDTIFG is reset automatically by servicing the interrupt, or can be reset by
software.
Because other bits in ~IFG1 may be used for other modules, it is recommended to clear
WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
0 no interrupt pending
1 interrupt pending
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SFRRPCR, SFRRPCR_H, SFRRPCR_L, Reset Pin Control Register
15
14
13
12
11
10
9
–
–
–
–
–
–
–
8
–
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
–
–
–
–
SYSRSTRE
SYSRSTUP
SYSNMIES
SYSNMI
r0
r0
r0
r0
r1
r1
r1
rw-0
Reserved
Bits 15–9
Reserved. Read back as 0
SYSRSTRE
Bit 3
Reset Pin resistor enable
0 Pullup / pulldown resistor at the RST/NMI pin is disabled
1 Pullup / pulldown resistor at the RST/NMI pin is enabled
SYSRSTUP
Bit 2
Reset resistor pin pullup / pulldown
0 Pulldown is selected
1 Pullup is selected
SYSNMIES
Bit 1
NMI edge select. This bit selects the interrupt edge for the NMI interrupt when SYSNMI = 1.
Modifying this bit can trigger an NMI. Modify this bit when SYSNMI = 0 to avoid triggering an
accidental NMI
0 NMI on rising edge
1 NMI on falling edge
SYSNMI
Bit 0
NMI select. This bit selects the function for the RST/NMI pin
0 Reset function
1 NMI function
Table 4. Memory Organization
TYPE
AFE4110A (Dev RAM)
Type
AFE4110B (Custom ROM)
Interrupt Vectors
RAM
32 B
0xFFE0 (1) – 0xFFFF
ROM
32 B
0xFFE0 (1) – 0xFFFF
Development RAM
RAM
14KB
0xC800 – 0xFFFF
—
—
Application ROM
—
—
ROM
14KB
0xC800 – 0xFFFF
TI Start Up Code (DSUC/PSUC)
ROM
2KB
0xC000 – 0xC7FF
ROM
2KB
0xC000 – 0xC7FF
TI Boot Loader Code
ROM
14KB
0x1E0 – 0x55FF
—
—
Application RAM
RAM
256B
0x1D00 – 0x1DFF
RAM
256B
0x1D00 – 0x1DFF
Application LRAM (lockable)
RAM
128B
0x1C80 – 0x1CFF
RAM
128B
0x1C80 – 0x1CFF
Calibration RAM (lockable)
RAM
128B
0x1C00 – 0x1C7F
RAM
128B
0x1C00 – 0x1C7F
Peripherals
Registers
4 kB
0x0000 – 0x0FFF
Registers
4 kB
0x0000 – 0x0FFF
(1)
not the whole interrupt vector range of CSYS is used on AFE4110 devices
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Start-Up Code (SUC)
The AFE4110A Development Start-Up Code (DSUC) supports system debug via a JTAG connection to an
external emulator. After the release of RST/NMI, the DSUC checks for the presence of a JTAG emulator by
reading the contents of the JTAG Mailbox Register. If the emulation password is present in the JTAG Mailbox,
the DSUC unlocks full access to the on chip emulation features, then enters LPM4 while waiting for to enter the
debug session. If the emulation password is not present in the JTAG Mailbox, the DSUC initiates execution of
the Loader Code.
The AFE4110B Production Start-Up Code (PSUC) also supports system debug via a JTAG connection to an
external emulator. The difference is that the PSUC checks for the contents of the JTAG Mailbox Register for a
confidential password. If the confidential password is present in the JTAG Mailbox, the PSUC unlocks full access
to the on chip emulation features, then enters LPM4 while waiting for to enter the debug session. If the
confidential password is not present in the JTAG Mailbox when RST/NMI is released, the PSUC initates
execution of the custom ROM code.
Loader Code (Loader)
The AFE4110A Loader checks for the presence of an external SPI memory device containing a valid data/code
package. The Loader transfers a validated data/code package into Development RAM. During validation and
transfer, the on chip 1.85V charge pump is enabled to supply power to VDDIO and the external SPI memory
device. (PCB level connections are required.) Once the transfer of the data/code package is complete, the
charge pump is disabled, the AFE4110 registers are returned to their default contents, and execution of the code
loaded in Development RAM is initiated.
RAM Memory
The RAM memory is split into three ranges for different purposes: Application memory, lockable application
memory and calibration memory.
Lockable application memory and calibration memory can be protected against accidental erasure by setting a
dedicated lock bit in the special functions register (System Maintenance Register).
Note: The lockable memory is locked by default after release of RST/NMI or exit from LPM5. The user code must
clear the lock bits in the Special Function Register after release of RST/NMI or exit from LPM5 to enable writing
lockable memory.
Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide (SLAU208) and the
MSP430x09x Family User's Guide (SLAU321).
Digital I/O
There are 4 I/O ports implemented: P1 (7 I/O lines), P2 (4 I/O lines), P3 (6 I/O lines) and P4 (4 I/O lines)
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on P1 and P3(0-5) ports.
• Programmable pullup on P2, P4 and P3(6,7) ports.
• External VDD (VDDIO) supply (1.1-3.3V range) to P2, P4 and P3(6,7) ports.
• Edge-selectable interrupt input capability for all ports.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1, P2, P3 and P4) or word-wise in pairs (P1/P2 combo).
22
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Oscillator and System Clock
The clock system in the AFE4110 family of devices is supported by the Compact Clock System (CCS) module
that includes an internal 20kHz current controlled low frequency oscillator (LF-OSC), an internal adjustable
(1-5.4MHz) current controlled high frequency oscillator (HF-OSC), a 1KHz ultra low power oscillator for the
activation block, an external clock input from CLKIN, and a 32kHz crystal oscillator. The CCS module is designed
to meet the requirements of both low system cost and low-power consumption. The CCS provides a fast turn-on
of the oscillators in less than 1 ms.
The CCS module provides the following clock signals:
• Auxiliary clock (ACLK) is software selectable for individual peripheral modules. ACLK is sourced from the
internal LF-OSC, the internal HF-OSC, an external source via CLKIN, or the crystal oscillator.
• Main clock (MCLK) is the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem master clock is software selectable by the peripheral modules.
SMCLK can be sourced by same sources made available to ACLK.
• VLOCLK this is a low frequency clock sourced by LF-OSC that is constantly available.
SELAx
OSCOFF
ACLK enable logic
DIVAx
3
00
HF – OSC
Divider
/1/2/4/8/16/32
01
10
0
1 1
11
ACLK
SCG0
SELMx
PORT_3.0 + PORT_3.1
CPUOFF
MCLK enable logic
LF-OSC/
VLOCLK
P3REN.0
xt_byp
DIVMx
00
P3OUT.0
DIVCLK
EN
01
10
3
Divider
/1/2/4/8/16/32
0
/2
MCLK
SCG1
SELSx
1
0
1 1
11
SMCLK enable logic
DIVSx
1
CLKIN/XIN/P3.0
XOUT/P3.1
32KHz
XTAL
0
00
01
10
EN#
3
Divider
/1/2/4/8/16/32
0
1 1
11
SMCLK
EN
P3IN.4
xt_byp
disable_p3_1
EN
VLOCLK
P3OUT.1
P3REN.1
Figure 1. Block Diagram of Compact Clock System (CCS)
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Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals. For a complete description of WDT_A, see the Watchdog Timer (WDT_A)
section of the MSP430x09x Family Users Guide (SLAU321).
Table 5. WDT_A Signal Connections
DEVICE CLOCK SIGNAL
MODULE CLOCK SIGNAL
ACLK
ACLK
SMCLK
SMCLK
LF-OSC-CLK
VLOCLK
HF-OSC-CLK
X-CLK
Compact System Module (C-SYS)
The Compact SYS module handles many of the system functions within the device. These include power on
reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, as
well as, configuration management. It also includes a data exchange mechanism via JTAG called a JTAG
mailbox that can be used in the application. For a complete description of C-SYS, see the Compact System
chapter of the MSP430x09x Family Users Guide (SLAU321).
Reset/NMI/SVMOUT System
The Reset system of the MSP430x09x family features the function Reset input, Reset output, NMI input, SVM
output and SVS input.
Interrupt
signals
maskable/
unmaskable
...
Interrupt
Logic
irq
CPU
nmi
Resetsignals
and
violations
PUC
...
Reset
Logic
POR
BOR
SWBOR
RST/NMI/
SVMOUT
SWPOR
RSTNMI
Brownout
Circuit
& Delay
from SVM logic
clr
SVMOE
PortsOn
SVSEN
SVMPD
set
SVMPO
Figure 2. Block Diagram of Reset/NMI/SVM and PortsOn logic
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Table 6. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
SYSBERRIV, Bus Error
INTERRUPT VECTOR
WORD
ADDRESS
OFFSET
No interrupt pending
00h
Brownout (BOR)
02h
SVMBOR (BOR)
04h
RST/NMI (BOR)
06h
DoBOR (BOR)
08h
Security violation (BOR)
0Ah
DoPOR(POR)
019Eh
WDT timeout (PUC)
0Eh
10h
CCS key violation
12h
PMM key violation
14h
Peripheral area fetch (PUC)
16h
Reserved
18h-3Eh
No interrupt pending
00h
SVMIFG
02h
VMAIFG
04h
019Ch
08h
Reserved
0Ah-3Eh
No interrupt pending
00h
NMIFG
02h
019Ah
06h
Reserved
08h-3Eh
Reserved
0198h
Highest
Lowest
Highest
04h
BERR
No interrupt pending
Lowest
06h
JMBOUTIFG
OFIFG
Highest
0Ch
WDT key violation (PUC)
JMBINIFG
PRIORITY
Lowest
00h
02h-3Eh
Lowest
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Activation Block
The AFE4110 Activation Block controls entry and exit from "deep-sleep" (LPM5) mode. When the device is in
LPM5, power is disconnected from AFE4110 CPU and all peripherals (including RAM, LCD and I/O) other than
the Activation block. When exiting LPM5, power is reapplied to the CPU core and peripherals. Exiting
"deep-sleep" (LPM5) mode is termed "wake up". The Activation block wakes up the CPU core and peripherals
based on how it was configured prior to entering LPM5. Wake up takes place based either on a transition on the
Activation Sense (ACTIVE) input or after a number of Activation Clock cycles have been counted. The ACTIVE
input can be configured to respond to either LOW-to-HIGH or HIGH-to-LOW transitions. The number of
Activation clock cycles to be counted prior to exiting LPM5 is configurable.
3 Ohm
VBAT
VCC
600
DISCHRG_Vbat
1.1v – 1.55v
In_mod_sel
In_mod_sel
1
0
Inv_mode
1
1
0
0
1
ACTIVE
Switch_sample_mode_SW
D
SET
CLR
450K
POR
Q
0
1
Q
1
C
Always sample
Q
Sleep_start
DFF
POR
50K
D
SET
CLR
Q
1
D
0
1KHz
DFF
acknowledge
BAT
POR
C
Q
0
1
Sleep_mode_sel
Q
PD_sel
Q
DFF
Q
Sense_sample_mode
1
DISCHRG_VCC
D
D
1200
8B
RAM
C
1KHz
Res_sel
VCC
C
Sense_interrupt
Q
Digital
interface
Isolation
Q
16
VCC Core
POR
16 bit compare
1KHz
Timer_mode
Clk System
On time – 3 bits 0.5ms to 4ms
Off time – 13 bits (1mS to 64s)
CLK
POR
Clk Period
C
Sleep_mode_sel
CLR
Clk Width
POR
26
Sleep_start
16 bits up counter
1Khz
29 bits shelf up counter
CLR
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Activation Block Hardware Status and Control Registers:
The Activation Block hardware registers control the method of entry and exit from deep sleep (LPM5) mode.
Additional features of the Activation Block registers include the following:
• VBAT Power On Reset (POR) Circuit – The VBAT POR is designed to reset the Activation block during initial
system power up that is typical of installation of a battery into the final product.
• 4-16bit words (8B) RAM – This RAM is implemented in hardware registers. The contents of these registers is
cleared at inital system power up by VBAT POR. The fact that these registers are cleared at initial system
power up allow them to be used to determine whether the CPU is being powered up by battery insertion or
exit from LPM5.
• 16bit Sleep Counter – The Activation block can be configured to exit LPM5 after the number of Activation
clock cycles that are selected. The counter can also be used as a general purpose down counter without
entering LPM5.
• 28bit Shelf Counter – This counter starts incrementing after the first time the device enters LPM5. After the
first exit from LPM5 this counter stops and its outputs remain static until VBAT power is removed. The intent
is for this counter to record number of Activation clock periods between initial insertion of a battery in to the
final product and the first usage of the final product. In other words, this counter indicates the length of time
that the final product is on the shelf prior to being used by a consumer.
• ACTIVE Sample Clock – To minimize the power required for determining transitions on the ACTIVE pad, the
state of the ACTIVE pad is sampled only at intervals which are set by the duty cycle of the ACTIVE Sample
Clock. The period between samples and the duration of the sample interval are configurable.
The Activation Block 'strobe' registers are not memory mapped and require a multi-step procedure for Reads and
Writes of their contents from the CPU. The Activation register strobe refers to the hardware signal used to
capture data into the bank of hardware registers. The strobe number (strobe address) indicates the bank of
16-hardware registers to be accessed. Only 16-bit (word) accesses are supported.
Activation Strobe Register Read Procedure:
The steps to Read a particular Activation strobe register follows:
1. Write the strobe address of the Activation register to be Read to the ACTIVATION_RD_ADDR register
2. Wait 10-MCLK clock cycles for the transfer of selected data to the ACTIVATION_DATAIN register
3. Read to contents of the ACTIVATION_DATAIN register
Activation Strobe Register Write Procedure:
The steps to Write Activation strobe registers follows:
1. Write to data value to be transferred to the Activation hardware register to the ACTIVATION_DATAOUT
register
2. Wait 10-MCLK clock cycles for data to transfer to the Activation block
3. Write a '1' to the bit corresponding to the Activation hardware register to be written into the
ACTIVATION_STROBES register.
Note: If multiple bits are written in the ACTIVATION_STROBES register, multiple Activation hardware
registers will be written
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The table below describes the function of the Activation strobe registers.
Table 7. Activation Strobe Register Function Table
data in #
strobe0
strobe1
strobe2
strobe3
strobe4
strobe5
data in 0
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Res_sel
Sample Clk Period
strobe6
strobe 7
data in 1
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
PD_sel
Sample Clk Period
data in 2
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Always_sample
Sample Clk Period
data in 3
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Inv_mode
Sample Clk Period
Reserved
data in 4
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Switch_sample_mode_SW
Sample Clk Period
Reserved
data in 5
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Switch_sample_mode
Sample Clk Period
Reserved
data in 6
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
In_mod_sel
Sample Clk Period
Reserved
data in 7
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Sleep_mode_sel
Sample Clk Period
Reserved
data in 8
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Reserved
Sample Clk Period
Reserved
data in 9
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Sleep_start
Sample Clk Period
Reserved
data in 10
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Timer_mode
Sample Clk Period
Reserved
data in 11
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Reserved
Sample Clk Period
Reserved
data in 12
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Reserved
Sample Clk Period
Reserved
data in 13
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Sample Clk Width
DISCHRG_Vbat
Reserved
data in 14
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Sample Clk Width
DISCHRG_VCC
Reserved
data in 15
RAM
reg 0
RAM
reg 1
RAM
reg 2
RAM
reg 3
sleep
counter
ACTIVE
Sample Clk Width
Reserved
Reserved
ACTCLK_Freq_Sel<2:0>
Strobe0 - Strobe3: Activation Block RAM Registers
RAM Reg0 - RAM Reg3 - Bits 15 - 0 - Constantly powered registers for used as RAM (Cleared by assertion of
VBAT POR)
Strobe4: Sleep Counter Register
Sleep_counter - Bits 15 - 0 - Sleep counter output value
Strobe5: ACTIVE Sample Clock Configuration Register
ACTIVE_Sample_Clock_Period - Bits 12 - 0 - Number of ACTCLK cycles per period of the ACTIVE sample
clock
0x0000 sets the sampling period to ~8192ms
0x0001 sets the sampling period to ~1ms...
0x0009 sets the sampling period to ~9ms ...
0x1FFF sets the sampling frequency to ~8192ms
ACTIVE_Sample_Clock_Width - Bits 15 - 13 - Number of ACTCLK half-cycles per sample interval of the
ACTIVE sample clock
Strobe6: LPM5 Configuration Register
Res_sel - Bit 0 - PU/PD Resistor Select
1 - 500KΩ resister selected
0 - 50KΩ resister selected
28
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PD_sel - Bit 1 - Pull Down Select
1 - PMOS sensing - internal PU is connected
0 - NMOS sensing – internal PD is connected
Always_sample - Bit 1 ACTIVE Sampling Select
1 - Continuous ACTIVE input sensing
0 - ACTIVE input sensing at sampled intervals
Inv_mode - Bit 3 - Inverted Mode
1 - Low to high transition sensing
0 - High to low transition sensing
Switch_sample_mode_SW - Bit 4 - Switch Sample Mode Switch
1 - Edge sensing for external switch closure selected
0 - Level sensing for external switch closure selected
Switch_sample_mode - Bit 5 - Switch Sample Mode
1 - Edge sensing for the sense_interrupt
0 - Level sensing for the sense_interrupt
In_mod_sel - Bit 6 - Input Mode Select
1 - Low current hysteresis sense inverter selected
0 - Standard input selected
Sleep_mode_sel - Bit 7 - Sense Mode Select
1 - high selects power down with counter;
0 - low selects power down without counter
Sleep_start - Bit 9 - Sleep Start
1 - Start power down
0 - Normal operating mode (This bit must be cleared by TI start up code.)
Timer_mode - Bit 10 - Timer Mode
1- Start sleep counter without entering LPM5
0 - Sleep counter is starting when entering LPM5 if sleep counter mode is selected
DISCHRG_Vbat - Bit 13 - Dischanrge VBAT Power
1 - Discharge Vbat voltage through 600 Ω resister
0 - No VBAT discharing selected
DISCHRG_VCC - Bit 14 - Discharge VCC Core
1- Discharge Vcc voltage through 1200 Ω resister
0 - No discharge of VCC Core voltage select
Strobe7: Activation Clock Frequency Select Register
ACTCLK_Freq_Sel - Bits 2 - 0 - Trims the ACT oscillator to set the frequency
Table 8. ACTIVE Sample Clock Width
SETTING
ACTIVE Sample Clock Interval
000
0.5 ACTCLK Period
001
1 ACTCLK Period
010
1.5 Clock Period
011
2 Clock Period
100
2.5 Clock Period
101
3 Clock Period
110
3.5 Clock Period
111
4 Clock Period
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Table 9. Activation Clock Frequency Selections
SETTING
CAP SETTING
FREQUENCY
000
60 fF
1 kHz
001
120 fF
0.75 kHz
010
180 fF
0.35 kHz
011
240 fF
250 Hz
100
150 fF
400 kHz
101
210 fF
280 Hz
110
270 fF
220 Hz
Activation Registers
SHELF_CNT_LO: Shelf counter low
15
14
13
12
11
10
9
8
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
r0
r0
r0
r0
r0
r0
r0
11
10
9
8
s_cnt_low (cont.)
s_cnt_low
r0
s_cnt_low
Bits 0-15
Lower 16 bits of Shelf counter
This is a read only Register
SHELF_CNT_HI: Shelf counter high
15
14
13
12
–
–
–
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
r0
r0
r0
r0
r0
r0
r0
10
9
8
2
1
0
s_cnt_high (cont.)
s_cnt_high
r0
s_cnt_high
Bits 0-12
Upper 13 bits of Shelf counter
This is a read only Register
ACTIVATION_DATAIN: Activation data in
15
14
13
12
11
act_d_in (cont.)
7
6
5
4
3
act_d_in
act_d_in
30
Bits 0-15
Activation Data In - Value of the
Strobe7-0 register which is
selected by the
ACTIVATION_RD_ADDR
register
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This is a read only Register
ACTIVATION_DATAOUT: Activation data out
15
14
13
12
11
10
9
8
rw-0
rw-0
rw-0
rw-0
3
2
1
0
rw-0
rw-0
rw-0
rw-0
act_d_out (cont.)
rw-0
rw-0
rw-0
rw-0
7
6
5
4
act_d_out
rw-0
rw-0
act_d_out
rw-0
Bits 0-15
rw-0
Activation Data Out - The data value to be written into the Strob1-0 register which is
selected by the ACTIVATION_STROBES register
ACTIVATION_STROBES: Activation strobes
15
14
13
12
11
10
9
8
rw-0
rw-1
rw-1
rw-0
Password
rw-1
rw-0
rw-0
rw-1
7
6
5
4
3
2
1
0
strb7
strb6
strb5
strb4
strb3
strb2
strb1
strb0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
strbx
strb0
strb1
strb2
strb3
strb4
strb5
strb6
strb7
Password
rw-0
Bits 0-15
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bits 8-15
Activation Strobe - These bits are 'one-hot' coded to select the Strob7-0 register to be
written with the contents of the ACTIVATION_DATAOUT register
Activation strobe 0
Activation strobe 1
Activation strobe 2
Activation strobe 3
Activation strobe 4
Activation strobe 5
Activation strobe 6
Activation strobe 7
Write 0xA5 to initiate Strobex register Write - Always reads back 0x96
Strb0-7 are self clearing bits
ACTIVATION_RD_ADDR: Activation read address
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
7
6
5
4
3
2
1
0
–
–
–
–
–
r-0
r-0
r-0
r-0
rw-0
rw-0
rw-0
read_add
Bits 0-2
read_add
rw-0
Register Read Address - Decimal coded index of Strobe7-0 register to be read back in
ACTIVATION_DATAIN register
ACTIVATION_STATUS: Activation Status
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
7
6
5
4
3
2
1
0
–
–
–
–
–
act_test
act_sleep
act_sense
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
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This is a read only register.
act_sense
act_sleep
Bit 0
Bit 1
act_test
Bit 2
Logic high signal indicate sense button changed state (pushed)
Sleep Comparator OUT. Can be configured like MSP Timer_0 out (INT_rise, INT fall, Level Latch High, Level latch
Low)
Counter out for testing
ACTIVATION_SENSE: Activation Sense
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
Act_sense_cir
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
This is a self clearing register
activation_sense_cir Bit 0
Acknowledge for clearing the sense_interrupt signal (should be a high pulse that can comes from SW or
HW)
Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers. AFE4110 Timer-0 has different Clocks Sources and CCx input multiplexing, compared to MSP430x5
documentation. Timer-0 Clock sources and the CCx input signals described in this document.
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Timer0_A3 Signal Connections and Block Diagrams
TIMER_0
LCD_CP_CLK
ACLK
SMCLK
ACTIVATION _CLK
Set
TA0CTL
TAIFG
CCR0
CxOUT (Apool)
P2.1
CCI0A
CCI0B
TA0CCR0
GND
VCC
Comparator 0
EQU0
Set
TA0CCR0
CCIFG
OUT0 Signal
Figure 3. Timer0_CCR0 Block Diagram
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TIMER_0
LCD_CP_CLK
ACLK
SMCLK
ACTIVATION _CLK
Set
TA0CTL
TAIFG
sel_timer0_cci1
CxOUT (Apool)
P1.1
P1.2
P1.3
P1.0
P1.4
P1.5
ACTIVATION _CLK
CCR1
2
00
01
10
11
00
01
10
11
CCI1A
CCI1B
TA0CCR1
GND
VCC
Comparator 1
EQU1
Set
TA0CCR1
CCIFG
OUT1 Signal
Figure 4. Timer0_CCR1 Block Diagram
34
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TIMER_0
LCD_CP_CLK
ACLK
SMCLK
ACTIVATION _CLK
Set
TA0CTL
TAIFG
sel_timer0_cci2
CxOUT (Apool)
P1_DIR.1
P1_DIR.2
P1_DIR.3
P1_DIR.0
P1_DIR.4
P1_DIR.5
SMCLK
CCR2
2
00
01
10
11
00
01
10
11
CCI2A
CCI2B
TA0CCR2
GND
VCC
Comparator 2
EQU2
Set
TA0CCR2
CCIFG
OUT2 Signal
Figure 5. Timer0_CCR2 Block Diagram
Timer1_A3
Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers. AFE4110 Timer-1 has different Clocks Sources and CCx input multiplexing, compared to MSP430x5
documentation. Timer-1 Clock sources and the CCx input signals described in this document.
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Timer1_A3 Signal Connections and Block Diagrams
TIMER_1
P2.3
ACLK
SMCLK
LFCLK
Set
TA1CTL
TAIFG
CCR0
CxOUT (Apool)
P2.0
CCI0A
CCI0B
TA1CCR0
GND
VCC
Comparator 0
EQU0
Set
TA1CCR0
CCIFG
OUT0 Signal
Figure 6. Timer1_CCR0 Block Diagram
36
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TIMER_1
P2.3
ACLK
SMCLK
LFCLK
Set
TA1CTL
TAIFG
sel_timer1_cci1
CxOUT (Apool)
P3.0
P3.1
P3.6
P1.6
ACTIVATION _CLK
ACLK
SMCLK
CCR1
2
00
01
10
11
00
01
10
11
CCI1A
CCI1B
TA1CCR1
GND
VCC
Comparator 1
EQU1
Set
TA1CCR1
CCIFG
OUT1 Signal
Figure 7. Timer1_CCR1 Block Diagram
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TIMER_1
P2.3
ACLK
SMCLK
LFCLK
Set
TA1CTL
TAIFG
sel_timer1_cci2
CxOUT (Apool)
P3.7
P3.4
P3.5
P1_DIR.6
ACTIVATION _CLK
ACLK
SMCLK
CCR2
2
00
01
10
11
00
01
10
11
CCI2A
CCI2B
TA1CCR2
GND
VCC
Comparator 2
EQU2
Set
TA1CCR2
CCIFG
OUT2 Signal
Figure 8. Timer1_CCR2 Block Diagram
LCD_E
The LCD_E is equivalent to TI LCD-B (MSP430x4 family) driver that generates the segment and common signals
required to drive an LCD display. The LCD_E controller has dedicated data memory to hold segment drive
information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and
4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply
voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.
The LCD_E operating voltage is minimum 2V, therefore the user must verify a 2V voltage is available on pin
37 either by activating the CP_1P8 or using external power supply.
The LCD_CP is using the CP_OSC as the reference oscillator for boosting the 2V to LCD operating voltage. The
CP_OSC is working from battery voltage (minimum 1.1V) and is shared with CP_1P8 which also using it for
generating the 2V from the battery voltage internally.
38
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A-Pool
The analog functions pool (A-Pool) provides a series of function that can be configured to a Digital to Analog
converter (DAC), multi channel Analog to Digital converter (ADC), Supply voltage supervisor SVS and
Comparator, input voltage dividers and an internal reference source allow wide range of combined analog
functions. For a complete description of A-Pool, see the Analog Pool chapter of the MSP430x09x Family Users
Guide (SLAU321)
PSELx
4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
REFON
Reference
256mV
VREF
+
OSEL
NSELx
Vcc
Vcc
6R
DFSETx
CxIFG logic
0
DeGlitching
1
xCLK
from AZ-logic
DBON
ODEN
Aout
1
CLKSEL
EOCIFG logic
2
VLOCLK
MCLK
SMCLK
00
01
10
11
CBSTP
SBSTP
TBSTP
TA0.1
Pre-Scaler
J
by 1/2/4/8/16/32
R
D/A-8
R
CxOUT
SVMIFG logic
SLOPE
0
4
0000
0001
0010
0011
0100
0101
0110
0111
A0
A1
A2
A3
OSWP
CMPON
AZ
EN
CT
VREFEN
CLKDIVx
TA0.0
TA0EN
TA1EN
TA1.0
clr
Run/
Stop set
xCLK
8
Clock
Logic
ADC-DAC-SAR-REG
Up-Dn Counter sEOC
Start Stop Logic
APVDIV Register
CONVON
SLOPE SAREN
MDB and buffer register
Figure 9. Block Diagram of A-Pool
Table 10. A-Pool Analog inputs Connection Table
A-POOL ANALOG INPUT
PAD
PSEL
NSEL
A3PSEL
A0_port_sel
A3a
P1.2
0011
0011
0
X
A3b
P1.3
0011
0011
1
X
A2
P1.0
0010
0010
X
X
A1
P1.1
0001
0001
X
X
A0a
P1.4
0000
0000
X
0
A0b
P3.3
0000
0000
X
1
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Versatile I/O Port P1, P2, P3, P4
The versatile I/O ports P1, P2, P3 and P4 feature device dependent reset values. The reset values for the
AFE4110 devices are shown in below.
Table 11. Versatile Port Reset Values
PORT
NUMBER
PxOUT
PxDIR
PxREN
PxSEL0
PxSEL1
RESET
Ports ON
COMMENT
I/O POWER
DOMAIN
P1.0
0
0
0
0
0
PUC
yes
P1.0, input
VDD
P1.1
0
0
0
0
0
PUC
yes
P1.1, input
VDD
P1.2
0
0
0
0
0
PUC
yes
P1.2, input
VDD
P1.3
0
0
0
0
0
PUC
yes
P1.3, input
VDD
P1.4
0
0
0
0
0
PUC
yes
P1.4, input
VDD
P1.5
0
0
0
0
0
PUC
yes
P1.5, input
VDD
P1.6
0
0
0
0
0
PUC
yes
P1.6, input
VDD
P1.7
–
–
–
–
–
–
–
–
P2.0
1
0
1
1
1
BOR
no
JTAG TCK
VDDIO
P2.1
1
0
1
1
1
BOR
no
JTAG TMS
VDDIO
P2.2
1
0
1
1
1
BOR
no
JTAG TDI
VDDIO
P2.3
0
1
0
1
1
BOR
no
JTAG TDO
VDDIO
P3.0
0
0
0
0
0
PUC
yes
P3.0, input
VDD
P3.1
0
0
0
0
0
PUC
yes
P3.1, input
VDD
P3.2
0
0
0
0
0
PUC
yes
P3.2, input
VDD
P3.3
0
0
0
0
0
PUC
yes
P3.3, input
VDD
P3.4
0
0
0
0
0
PUC
yes
P3.4, input
VDD
P3.5
0
0
0
0
0
PUC
yes
P3.5, input
VDD
P3.6
0
0
0
0
0
PUC
yes
P3.6, input
VDDIO
P3.7
0
0
0
0
0
PUC
yes
P3.7, input
VDDIO
P4.0
0
0
0
0
0
PUC
Yes
P4.0, input
VDDIO
P4.1
0
0
0
0
0
PUC
Yes
P4.1, input
VDDIO
P4.2
0
0
0
0
0
PUC
Yes
P4.2, input
VDDIO
P4.3
0
1
0
0
0
PUC
yes
P4.3, input
VDDIO
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Table 12. Peripherals
MODULE NAME
AREGS
Activation
LCD
REGISTER DESCRIPTION
REGISTER
BASE ADDRESS
ANALOG_FUSETRIM
Analog timer control
ANALOG_TIMERCTL
14h
Analog port control 2
ANALOG_PORTCTL2
12h
Analog port control 1
ANALOG_PORTCTL1
10h
Analog ana control
ANALOG_ANACTL
0Eh
Analog bias current control
ANALOG_IBIASCTL
0Ch
Analog LDO control
ANALOG_LDOCTL
0Ah
Analog LDO configuration
ANALOG_LDOCFG
08h
Analog LCDP control
ANALOG_LCDPCTL
06h
Analog LCD charge pump control
ANALOG_LCDCPCFG
04h
Analog charge pump 1.8V control
ANALOG_CP1P8CTL
02h
Analog charge pump 1.8V configuration
ANALOG_CP1P8CFG
Activation Sense
ACTIVATION_SENSE
Activation Status
ACTIVATION_STATUS
0Ch
Activation read address
ACTIVATION_RD_ADDR
0Ah
Activation strobes
ACTIVATION_STROBES
08h
Activation data out
ACTIVATION_DATAOUT
06h
Activation data in
ACTIVATION_DATAIN
04h
Shelf counter high
SHELF_CNT_HI
02h
Shelf counter low
SHELF_CNT_LO
Reserved
04A0h
00h
0480h
0Eh
00h
0400h
46h-5Fh
LCDB1-6
LCD memory 1–6 (1)
LCDM1-6
20h-25h
LCD_B interrupt vector
LCDBIV
1Eh
40h-45h
Reserved
26h-3Fh
Reserved
LCD_B charge pump control
14h-1Ch
LCDBCPCTL
12h
Reserved
(1)
16h
(1)
LCD Blinking 1–6
Timer1_A3
OFFSET
Analog e-fuse
0Ah-11h
LCD_B voltage control register
LCDBVCTL
08h
LCD_B memory control register
LCDBMEMCTL
06h
LCD_B blinking control register
LCDBBLKCTL
04h
LCD B control register 1
LCDBCTL1
02h
LCD B control register 0
LCDBCTL0
Timer1_A interrupt vector
TA1IV
Capture/compare register 2
TA1CCR2
16h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 0
TA1CCR0
12h
Timer1_A register
TA1R
10h
Capture/compare control 2
TA1CCTL2
06h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 0
TA1CCTL0
02h
Timer1_A control
TA1CTL
00h
00h
0380h
2Eh
Six 8 bit registers, but the LCD blinking and memory registers can also be accessed as word
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Table 12. Peripherals (continued)
MODULE NAME
Timer0_A3
Port P4
Port P3
Port P2
Port P1
42
REGISTER DESCRIPTION
REGISTER
BASE ADDRESS
TA0IV
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 0
TA0CCR0
12h
Timer1_A register
TA0R
10h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 0
TA0CCTL0
02h
Timer1_A control
TA0CTL
Port P4 interrupt Flag
P4IFG
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt vector word
P4IV
1Eh
Port P4 selection 1
P4SEL1
0Dh
Port P4 selection 0
P4SEL0
0Bh
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 direction
P4DIR
05h
Port P4 outout
P4OUT
03h
Port P4 input
P4IN
Port P3 interrupt Flag
P3IFG
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt vector word
P3IV
0Eh
Port P3 selection 1
P3SEL1
0Ch
Port P3 selection 0
P3SEL0
0Ah
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 direction
P3DIR
04h
Port P3 outout
P3OUT
02h
Port P3 input
P3IN
Port P2 interrupt Flag
P2IFG
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt vector word
P2IV
0Eh
Port P2 selection 1
P2SEL1
0Dh
Port P2 selection 0
P2SEL0
0Bh
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 direction
P2DIR
05h
Port P2 outout
P2OUT
03h
Port P2 input
P2IN
Port P1 interrupt Flag
P1IFG
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt vector word
P1IV
0Eh
Port P1 selection 1
P1SEL1
0Ch
Port P1 selection 0
P1SEL0
0Ah
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 direction
P1DIR
04h
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0340h
OFFSET
Timer0_A interrupt vector
2Eh
00h
0220h
1Dh
01h
0220h
1Ch
00h
0200h
1Dh
01h
0200h
1Ch
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Table 12. Peripherals (continued)
MODULE NAME
A-POOL
CSYS
CCS
REGISTER DESCRIPTION
REGISTER
BASE ADDRESS
OFFSET
Port P1 outout
P1OUT
02h
Port P1 input
P1IN
Analog pool interrupt vector register
APIV
Analog pool interrupt enable register register
APIE
1Ch
Analog pool interrupt flag register
APIFG
1Ah
Analog pool fractional value buffer
APFRACTB
16h
Analog pool fractional value register
APFRACT
14h
Analog pool integer value buffer
APINTB
12h
Analog pool integer value register
APINT
10h
Analog pool voltage divider register
APVDIV
06h
Analog pool operation mode register
APOMR
04h
Analog pool control register
APCTL
02h
Analog pool configuration register
APCNF
Reset vector generator
SYSRSTIV
System NMI vector generator
SYSSNIV
1Ch
User NMI vector generator
SYSUNIV
1Ah
Bus error vector generator
SYSBERRIV
18h
System Configuration register
SYSCNF
10h
JTAG mailbox output register #1
SYSJMBO1
0Eh
JTAG mailbox output register #0
SYSJMBO0
0Ch
JTAG mailbox input register #1
SYSJMBI1
0Ah
JTAG mailbox input register #0
SYSJMBI0
08h
JTAG mailbox control register
SYSJMBC
06h
System control register
SYSCTL
00h
CCS control 8 register
CCSCTL8
CCS control 7 register
CCSCTL7
0Eh
CCS control 6 register
CCSCTL6
0Ch
CCS control 5 register
CCSCTL5
0Ah
CCS control 4 register
CCSCTL4
08h
CCS control 2 register
CCSCTL2
04h
CCS control 1 register
CCSCTL1
02h
00h
01A0h
1Eh
00h
0180h
0160h
1Eh
10h
CCS control 0 register
CCSCTL0
WDT_A
WDT_A Watchdog timer control
WDTCTL
0150h
00h
0Ch
PMM
PMM PMM control 0
PMMCTL0
0120h
00h
ET-WRAPPER
ET-Wrapper ET Key and select
ETKEYSEL
0110h
00h
Special
Functions
Special Functions SFR Reset pin control register
SFRRPCR
0100h
04h
SFR interrupt flag register
SFRIFG1
02h
SFR interrupt enable register
SFRIE1
00h
Legend
rw:
Bit can be read and written.
rw-0,1: Bit can be read and written. It is reset or set by PUC. (1)
rw-(0,1): Bit can be read and written. It is reset or set by POR (2)
rw-[0,1]: Bit can be read and written. It is reset or set by BOR. (3)
–
bit is not present in device
(1)
(2)
(3)
PUC is for "normal" registers which should be reset at all time
POR is used for registers, which should not be reset by a WDT event (like status information)
BOR is used for registers, which are configured during boot code execution and should not be reset during normal reset events
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Analog Control Registers
ANALOG_CP1P8CFG: Analog charge pump 1.8V configuration
15
14
13
12
11
10
9
8
–
–
–
1p8_valid
clk_sel
force_clk
mode_sel
cp_1p8_pd
r-0
r-0
r-0
r-0
rw-0
rw-0
rw-0
rw-1
7
6
5
4
3
2
1
0
cp_1p8_hyst_set
rw-0
cp_1p8_out_level
rw-0
rw-0
cp_1p8_clk_div
cp_1p8_out_level
cp_1p8_hyst_set
Bits 2-0
Bits 5-3
Bits 7-6
cp_1p8_pd
cp_1p8_clk_mode_sel
cp_1p8_force_clk
cp_1p8_clk_sel
cp_1p8_valid
Bit
Bit
Bit
Bit
Bit
cp_1p8_clk_div
rw-0
rw-0
rw-0
rw-0
rw-0
Select the clock divider (see table below)
Set the CP valid threshold voltage (see table below)
Set the comparator hysteresis (inside the CP loop) – 000 means close hysteresis, and 111
means wide hysteresis. When using fast clock (high current) the user must use close
hysteresis 000.
Powers Down the charge pump circuitries
Test mode of the CP loop, break the loop to control by the signal fram_force_clk
Force a continuous clock to the Charge Pump (in test mode)
Select which clock to use (internal or external)
Valid 1.8v indication output
8
9
10
11
12
ANALOG_CP1P8CTL: Analog charge pump 1.8V control
15
14
13
12
11
10
9
8
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
7
6
5
4
Reserved
cp_1p8_valid_level
rw-0
clk_refresh_freq
rw-0
rw-0
cp_1p8_quiet_mode
cp_1p8_force_out_clamp_en
Bit 0
Bit 1
cp_1p8_force_out_clamp
cp_1p8_ext_cap_en
cp_1p8_clk_refresh_freq
cp_1p8_valid_level
Reserved
Bit 2
Bit 3
Bits 4-5
Bits 6-7
Bits 8 - 15
rw-0
3
2
1
0
ext_cap_en
clamp
clamp_en
quiet_mode
rw-0
rw-0
rw-1
rw-0
Inhibits charge pump clocking
Controls the output clamp switch to AVDD_BAT (0 - clamp according to control; 1clamp according to PD control)
Force the output clamp to AVDD_BAT
Set to high when high current is required
Set the frequency for refreshing the rdiv cap (see table below)
Set the CP valid threshold voltage (see table below)
cp_1p8_out_level
44
cp_1p8_clk_div table:
Setting
Freq
Setting
Freq
000
2.075 V
000
FS (4MHz)
001
2.05 V
001
001 FS/2
010
2.025 V
010
FS/4
011
2V
011
FS/8
100
1.975 V
100
FS/16
101
1.95 V
101
FS/32
110
1.925 V
110
FS/64
111
1.9 V
111
FS/128
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cp_1p8_clk_refresh_freq table:
cp_1p8_clk_valid_level table:
Setting
Freq
Setting
Freq
00
156.25 Hz
00
1.75 V
01
312.5 Hz
01
1.8 V
10
312.5 Hz
10
1.85 V
11
625 Hz
11
1.9 V
The clock output is a single 50 µs pulse
ANALOG_LCDCPCFG: Analog LCD charge pump controlR
15
14
13
12
11
10
9
–
–
–
–
–
–
–
–
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
7
6
5
4
3
2
1
0
–
–
–
Force_clk
–
–
–
clk_sel
r-0
r-0
r-0
rw-0
r-0
r-0
r-0
rw-0
lcd_cp_clk_sel
lcd_cp_force_clk
Bit 0
Bit 4
8
NC (Not connected)
NC
ANALOG_LCDPCTL: Analog LCDP control
15
14
13
12
11
10
9
8
seg11_en
seg10_en
seg9_en
seg8_en
seg7_en
seg6_en
seg5_en
seg4_en
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
7
6
5
4
3
2
1
0
seg3_en
seg2_en
seg1_en
seg0_en
com3_en
com2_en
com1_en
com0_en
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
rw-1
com0_en
com1_en
com2_en
com3_en
seg0_en
seg1_en
seg2_en
seg3_en
seg4_en
seg5_en
seg6_en
seg7_en
seg8_en
seg9_en
seg10_en
seg11_en
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Enable LCD pin common 0. "1" – enable, "0" – disable
Enable LCD pin common 1. "1" – enable, "0" – disable
Enable LCD pin common 2. "1" – enable, "0" – disable
Enable LCD pin common 3. "1" – enable, "0" – disable
Enable LCD pin segment 0. "1" – enable, "0" – disable
Enable LCD pin segment 1. "1" – enable, "0" – disable
Enable LCD pin segment 2. "1" – enable, "0" – disable
Enable LCD pin segment 3. "1" – enable, "0" – disable
Enable LCD pin segment 4. "1" – enable, "0" – disable
Enable LCD pin segment 5. "1" – enable, "0" – disable
Enable LCD pin segment 6. "1" – enable, "0" – disable
Enable LCD pin segment 7. "1" – enable, "0" – disable
Enable LCD pin segment 8. "1" – enable, "0" – disable
Enable LCD pin segment 9. "1" – enable, "0" – disable
Enable LCD pin segment 10. "1" – enable, "0" – disable
Enable LCD pin segment 11. "1" – enable, "0" – disable
To enable the LCD both the relevant ANALOG_LCDPCTL bit should be set to 1 and the LCDON bit in LCD
register LCDBCTL0 should be set to 1.
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ANALOG_LDOCFG: Analog LDO configuration
15
14
–
–
r-0
r-0
13
12
11
10
9
–
–
cap_sw_general
rw-0
r-0
r-0
2
ldo_out_mux
rw-0
7
6
5
4
3
high_cap_sw
low_cap_sw
ldo_bypass
ldo_pd
–
rw-0
rw-0
rw-0
rw-1
r-0
ldo_trim_bits
ldo_pd
ldo_bypass
low_cap_sw
high_cap_sw
cap_sw_general
ldo_out_mux
Bits 0-2
Bit 4
Bits 5
Bit 6
Bit 7
Bit 8-9
Bit 12-13
8
rw-0
rw-0
1
0
ldo_trim_bits
rw-0
rw-0
rw-0
LDO voltage trimming (see table below)
"1" LDO Shut down. Vout=open
"1" Bypass the LDO, shorts LDO Vout to VDD
"1" Connect the low calibration capacitor (20pF)
"1" Connect the high calibration capacitor (40pF)
NC
"00" set the LDO output switch to "off". "11" set LDO output switch to "on"
ldo_trim_bits table:
Setting
Vout[V]
000
1.045
001
10.72
010
1.1
011
1.125
100
0.96
101
0.98
110
1
111
1.02
ANALOG_LDOCTL Analog LDO control
15
14
13
12
11
10
9
8
rw-0
rw-0
rw-0
rw-0
rw-0
4
3
2
1
0
rw-0
rw-0
ldo_ctl (cont.)
rw-0
7
rw-0
rw-0
6
5
ldo_ctl
rw-0
a0_port_sel
rw-0
rw-0
LDO_IO_sel
Bit 0-3
a0_port_sel
ldo_ctl
Bit 4
Bits 5-15
Used to mux the LDO to IOs in the following order:
<0> – port 1.0;
<1> – port 1.1;
<2> – port 1.4;
<3> – port 3.3;
Select which IO goes to A0 input of the A-Pool – ,0. selects port 1.4
NC
46
rw-1
LDO_IO_sel
r-0
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rw-0
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ANALOG_IBIASCTL: Analog bias current control
15
14
spare
13
12
lf_force_mode
hfos_current
11
10
osc_6m current
9
8
ctl_ref_current
rw-0
rw-0
rw-0
rw-1
rw-0
rw-0
rw-0
rw-0
7
6
5
4
3
2
1
0
rw-0
rw-0
rw-0
rw-0
ibias_pd
rw-0
rw-0
rw-0
Ibias_pd
ctl_ref_current
Bits 0-7
Bits 8-9
osc_6m current
Bits 10-11
hfos_current
lf_mode_force
Bit 12
Bit 13
spare
Bits 14-15
rw-0
Powering down the bias currents Not used
Select main reference current:
00 – 10nA (Deafult)
01 – 6nA
10 – 12nA
11 – 8nA
Controls the HF_OSC current setting:
00 – 1 µA
01 – 3 µA
10 – 2 µA
11 – 4 µA
1 – Setting the HF_OSC to low frequency/low current mode (1MHz/10µA)
0 – lf_mode is forced on hf_osc ;
1 – lf_mode is working only of I_trim is 00
Not Used
HF_OSC LF Mode - Typical frequency after HF-OSC calibrated to 4.4MHz
hfos_current<12>
lf_mode_force<13>
osc_6m current<11,10>
HF-OSC Frq [MHz]
0
x
00
1.87
01
4.44
10
3.27
11
5.4
00
1
1
0
01
10
11
1
1
00
1
01
3.9
10
2.6
11
5
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ANALOG_ANACTL: Analog ana control
15
14
13
12
11
10
ana_ctl (not used)
9
lpm5_en_lcd_ana_shell
rw-0
rw-0
rw-0
rw-0
7
6
5
4
8
Cp_osc_trim
rw-0
rw-1
rw-0
rw-0
3
2
1
0
Reserved
rw-0
rw-0
rw-0
rw-0
Reserved
Ana_ctl_cp_osc_trim
Bits 0-7
Bits 8-9
lpm5_lcd_ana_shell
Bit 10
ana_ctl
Bits 11-15
rw-0
rw-0
rw-0
rw-0
Course trimming of the 2 charge
pumps oscillator (current
trimming)
"1" powers down (~40nA) the
max_detect block inside the LCD
Block
Not used
ANALOG_PORTCTL1: Analog Analog port control 1
15
14
bp_dir_sync
13
12
11
10
9
8
irq_on_p3_7
irq_on_p3_6
irq_on_p3_5
irq_on_p3_4
irq_on_p3_3
irq_on_p3_2
rw-0
rw-0
rw-0
rw-0
rw-0
4
3
2
1
–
–
r-0
r-0
rw-0
r-0
rw-0
7
6
5
sel_port3_7
r-0
r-0
rw-0
rw-0
0
sel_port3_6
rw-0
rw-0
sel_port3_6, sel_port3_7: PORT3.6 and PORT3.7 Input multiplexer control
sel_port3_6
sel_port3_7
sel_irq_on_p3_2
sel_irq_on_p3_3
sel_irq_on_p3_4
sel_irq_on_p3_5
sel_irq_on_p3_6
sel_irq_on_p3_7
bypass_dir_sync
(1)
48
Bits 1,0
P3SEL1/0 = 01
P3SEL1/0 = 10
P3SEL1/0 = 11
Bits 5,4
P3SEL1/0 = 01
P3SEL1/0 = 10
P3SEL1/0 = 11
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
0,0
0,1
TA0.0
TA0.1
NEG(TA0.0)
NEG(TA0.1)
BROWNOUT
ACTIVATION_SENSE
0,0
0,1
TA0.0
TA0.1
NEG(TA0.0)
NEG(TA0.1)
LCD_CP_CLK
LCD_FCLK
force '0' when test_atpg_en_i = '1'
1,0
TA0.2
NEG(TA0.2)
LFCLK
1,0
TA0.2
NEG(TA0.2)
HFCLK
1,1
TA1.1
NEG(TA1.1)
CP_1P8_COMP
1,1
LCD_COMP
NEG(LCD_COMP)
ACTIVATION_OSC_1KHZ
"1" Enable Portx.y direct DIR signal connection to TiIMERx CCx (No Dithering). "0" Enable
Portx.y DIR signal (sync to LFCLK) connection to TiIMERx CCx .Dithering enabled when
HF-CLK or EXCLK selected as Timer Clock source. (1)
force '1' when test_atpg_en_i = '1'
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ANALOG_PORTCTL2: Analog Analog port control 2
15
14
13
12
11
10
9
–
–
–
–
–
–
–
–
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
7
6
5
4
3
2
1
0
dp1_6
dp1_5
dp3_5
dp3_4
dp3_3
dp3_2
dp3_1
dp3_0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
disable_p3_0
Bit 0
disable_p3_1
Bit 1
disable_p3_2
Bit 2
disable_p3_3
Bit 3
disable_p3_4
Bit 4
disable_p3_5
Bit 5
disable_p1_5
Bit 6
disable_p1_6
Bit 7
(1)
8
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
"1" disables input driver. Use to enable
input driver stage (1)
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
connection analog voltage input w/o feed through current at PORTx.y
force '0' when test_atpg_en_i = '1'
ANALOG_TIMERCTL: Analog timer CCx input mux control
15
14
–
–
r-0
r-0
rw-0
7
6
5
–
–
r-0
r-0
13
12
11
10
–
–
rw-0
r-0
r-0
rw-0
rw-0
4
3
2
1
0
sel_timer1_cci2
sel_timer0_cci2
rw-0
rw-0
9
8
sel_timer1_cci1
–
–
r-0
r-0
sel_timer0_cci1
rw-0
rw-0
sel_port3_6, sel_port3_7: PORT3.6 and PORT3.7 Input multiplexer control
sel_timer0_cci1
sel_timer0_cci2
sel_timer1_cci1
sel_timer1_cci2
Bits 1,0
Timer0 CCI1A
Input Select
Timer0 CCI1B
Input Select
Bits 5,4
Timer0 CCI2A
Input Select
Timer0 CCI2B
Input Select
Bits 9,8
Timer1 CCI1A
Input Select
Timer1 CCI1B
Input Select
Bits 13,12
Timer1 CCI2A
Input Select
Timer1 CCI2B
Input Select
0,0
CxOUT from
APOOL
Port P1.0
0,1
Port P1.1
1,0
Port P1.2
1,1
Port P1.3
Port P1.4
Port P1.5
ACTIVATION_OSC_1KHZ
0,0
CxOUT from
APOOL
Port P1.0DIR
0,1
Port P1.1DIR
1,0
Port P1.2DIR
1,1
Port P1.3DIR
Port P1.4DIR
Port P1.5DIR
SMCLK
0,0
CxOUT from
APOOL
Port P1.6
0,1
Port P3.0
1,0
Port P3.1
1,1
Port P3.6
ACTIVATION_OSC_1KHZ
ACLK
SMCLK
0,1
Port P3.7
1,0
Port P3.4
1,1
Port P3.5
ACTIVATION_OSC_1KHZ
ACLK
SMCLK
0,0
CxOUT from
APOOL
Port P1.6DIR
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ANALOG_FUSETRIM: Analog e-fuse
15
14
13
–
–
–
12
11
10
r-0
r-0
r-0
r-f*
r-f*
r-f*
7
6
5
4
3
2
cal-fact
r-f*
r-f*
HF-Osc_trim
cal_fact
r-f*
Bits 2-0
Bits 12-3
9
8
r-f*
r-f*
1
0
cal-fact (cont.)
HF-Osc_trim
r-f*
r-f*
r-f*
r-f*
r-f*
HF-Oscillator trimming. Bits 7-9 of effuse module.
Discharge calibration factor. Bits 10-19 of e-fuse module.
● Bits 6-0 of e-fuse module can be read via bits 0-6 of APOOL APTRIM register.
● Some e-fuse bits can also be read via top level register ETTOPCTL0
● This is a read only register.
Additional LCD Registers
LCD registers are described in the LCD_B chapter of the CC430 Family Users Guide (slau259b). The only
exceptions:
1. Bit 15 of register LCDBCPCTL (LCDCPCLKEXT bit ) has a new functionality as described below.
2. Bit 10 of register ANALOG_ANACTL (lpm5_lcd_ana_shell bit) has a new functionality as described below.
1. LCDBCPCTL, LCD_B Charge Pump Control Register
LCDCPCLKEXT
Selects between internal and external clock source for the LCD '0' – internal clock source
Charge Pump
'1' – external clock source
Bit 15
Default value of this bit is rw-0
2. ANALOG_ANACTL
lpm5_lcd_ana_shell
Bit 10
"1" powers down (~40nA) the max_detect block inside the LCD Block
Default value of this bit is rw-1
Additional Timer Registers
Timer registers are described in Timer_A chapter of the MSP430x09x Family Users Guide (SLAU321).
Additional Ports Registers
Port registers are described in Versatile I/O Port chapter of the MSP430x09x Family Users Guide (SLAU321)
Additional APOOL Registers
Analog Functions Pool Module chapter of the MSP430x09x Family Users Guide (SLAU321).
Additional CSYS Registers
Compact System Control Module chapter of the MSP430x09x Family Users Guide (SLAU321). The only
exceptions are:
MEMSWP BIT 11
1 - Selects the EMU/Loader memory configuration
0 - Selects the custom ROM memory configuration
50
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CCS Registers
Compact Clock System chapter of the MSP430x09x Family Users Guide (SLAU321). The only exception is
different functionality of register CCSCTL6 as described below:
CCSCTL6: CCS control 6
15
14
13
–
–
–
r-0
r-0
r-0
rw-0
rw-0
rw-0
rw-0
rw-1
7
6
5
4
3
2
1
0
xt_byp
xt_clken2
xt_clken1
rw-1
r-0
rw-1
rw-1
rw-1
r-0
r-0
–
r-0
xt_clken1
xt_clken2
xt_byp
xt_sw
xt_off
Reserved
12
11
10
xt_sw
Bit 0
Bit 1
Bit 2
Bits 3-6
Bit 8
Bits 9-12
9
8
Reserved
xt_off
Enable 1 of 32Khz XTAL clock synchronization sequence
Enable 2 of 32Khz XTAL clock synchronization sequence
32Khz XTAL Bypass
32Khz XTAL switch See table below for recommended switch values
32Khz XTAL off
Recommended control switch settings:
XTL Oscillator Performance
SW4
SW3
SW2
SW1
Least current
1
0
0
0
Fast startup
1
0
1
1
CCS CTL6 enables the external clock/XTAL clock:
xt_clken1, bit 0 and xt_clken2, bit 1
1. Enable EXT/XTL Clock by setting the xt_clken2 and xt_clken1 bits.
2. After sufficient delay for XTAL or external clock source to become stable, the user can switch the CCS clock
source to EXT/XTL Clock
3. To stop the clock, clear the two bits in the following sequence:
(a) Switch the CCS clock source to other clock source
(b) Clear bit xt_clken2
(c) Wait for at least 3 period of XTAL (or external clock)
(d) Clear bit xt_clken1
CCSCTL2, Compact Clock System Control 2 Register
15
14
13
12
11
10
9
8
r-0
r-0
r-0
r-0
3
2
1
0
rw-0
rw-0
rw-0
Reserved
r-0
r-0
r-0
r-0
7
6
5
4
Reserved
r-0
Reserved
FSELx
FSELx
rw-0
Bits 15 – 7
Bits 6 – 0
rw-1
rw-0
rw-1
Reserved. Read back as 0.
Frequency trimming of the HF-OSC
Value HF-OSC
0000000 highest adjustable frequency
……
0101000 center frequency
……
1111111 lowest adjustable frequency
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WDT_A Registers
WDT_A registers are described in the Watch Dog Timer (WDT_A) chapter of the MSP430x09x Family Users
Guide (SLAU321).
PMM Registers
Compact System Control chapter of the MSP430x09x Family Users Guide (SLAU321).
Peripherals Continued
LDO1V
The Low Droop Out (LDO) is 1Volt (200µA max) voltage regulator that capable to drive 4 GPIO ports. The
regulated 1V output is recommended to use for external RC charge, in order to minimize the effect of battery
voltage changes between consecutive RC charges, durring Termistor and reference Resistor discharge time
measurement.
ldo_out_mux
900 mV
+
-
1V
EN
1
200
LDO1V
0
ldo_low_cap_sw
1
Ldo_1v_pd_i
20pF
0
ldo_high_cap_sw
1
20pF
20pF
0
Figure 10. LDO1V Block Diagram
CP_1P8
The CP_1P8 is an internal charge pump module which is used to boost the battery voltage to ~2V. The voltage
boost is mandatory for the LCD operation.
The CP_1P8 is sharing the CP_OSC with the LCD_CP as the reference clock for the boosting and also using the
LF_clk for voltage feedback sensing.
The CP_1P8 requires 3 external capacitors for operation which are connected as following:
• 1nF capacitor connected between pads 41 (C1_out) and 40 (C1_in)
• 1nF capacitor connected between pads 39 (C2_out) and 38 (C2_in)
• 4.7nF capacitor connected between pads 37 and ground – load capacitor.
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The CP_1P8 has a valid signal which indicates when the voltage of the CP_1P8 has reached a 1.8V
(Configurable) to allow operation of the LCD_CP or of other peripherals.
reset / PD / manual control
AVDD BAT
Clk_sel_i
External cap
Cp1p8_cap
Ibias 20nA
Charge
pump
315 Kohm
Ibias 20nA
20KHz
Cp1p8_
comp_out
2:1
Cp_valid_level
<1:0>
Hyst_set<1:0>
10pF
Vref 0.9V
DFF
20KHz
285 Kohm
20KHz
Clk_refersh_pulse<1:0>
Rdiv_cap_force
Force
clk
High current load
Test mode
2:1
Mux
Switch
control
Refresh
pulse
Rdiv_cap_mod_sel
Mux
Vref 0.9V
DFF
valid
Rdiv_current_force
2:1
CLK non
overlap
CLK
divider
Clk_div<2:0>
Ext Clk
Mux
Cp_out_level
<2:0>
Rdiv_current_mod_ sel
Clk in
Force quiet mod
Figure 11. CP_1P8 Block Diagram
CP18 MAXIMUM CHARGE PUMP CURRENT
vs
CHARGE CAPACITORS
1.E-01
Vbat = 1.3 V,
Vload = 1.8 V,
f = 4 MHz
BAT_Current
Current - A
1.E-02
Load_Current
1.E-03
1.E-04
5.0E-11
1.0E-10 1.0E-09 1.0E-08
ext_cap_size - F
5.0E-08
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PARAMETER MEASUREMENT INFORMATION
Pad Logic
to A- Pool
From Apool Register
from LDO1V
from LDO_IO_sel
P1DIR.x (to CCRx.y)
P1REN.x
Vss
P1DIR.x
0
Vcc 1
1
D
Q
D
0
Q
bypass_dir_sync
00
01
10
11
PortsOn
LFCLK
P1OUT. x
from Module
from Module
from Module
P1SEL0.x
30K
00
01
10
11
P1.x
P1SEL1.x
P1IN. x
EN1
# EN
2
Module X IN
D
P1IES. x
Set
Q
P1IFG. x
P1IE.x
P1IRQ. x
Figure 12. Port P1, P1.0, P1.1, P1.4 Input/Output
Table 13. Port P1 (P1.0, P1.1, P1.4) Functions
CONTROL BITS/SIGNALS (1)
PIN NAME (P1.x)
x
P1.0/TA0.2/TA0.1/TA1.2/LDO1/T
A0.CCI1B0/TA0.CCI2B0/A2
0
FUNCTION
General-purpose digital I/O
1
(1)
54
4
P1SEL0.x
NSELx/PSELx
LDO_IO_sel
<3-0>
In:0; Out:1
0
0
0
XXX0
1
0
1
0
XXX0
Timer1_A3 Out2 output
1
1
0
0
XXX0
Timer0_A3 Out1 output
1
1
1
0
XXX0
Analog in A2 or
Atest1 Out – A Pool
X
X
X
2
XXXX
1
X
X
X
XXX1
In:0; Out:1
0
0
0
XX0X
Timer0_A3 Out2 output
1
0
1
0
XX0X
Timer1_A3 Out2 output
1
1
0
0
XX0X
Timer0_A3 Out1 output
1
1
1
0
XX0X
Analog in A1 – A-Pool
X
X
X
1
XXXX
General-purpose digital I/O
LDO 1V Out
P1.4/TA0.2/TA0.1/TA1.2/LDO1/T
A0.CCI1B1/TA0.CCI2B1/A0
P1SEL1.x
Timer0_A3 Out2 output
LDO 1V Out
P1.1/TA0.2/TA0.1/TA1.2/LDO1/T
A0.CCI1A1/TA0.CCI2A1/A1
P1DIR.x
1
X
X
X
XX1X
In:0; Out:1
0
0
0
X0XX
Timer0_A3 Out2 output
1
0
1
0
X0XX
Timer1_A3 Out2 output
1
1
0
0
X0XX
Timer0_A3 Out1 output
1
1
1
0
X0XX
Analog in A0 – A-Pool
X
X
X
0
XXXX
LDO 1V Out
1
X
X
X
X1XX
General-purpose digital I/O
X = Don't care
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Pad Logic
to A-Pool A3a
NSEL.x=y or PSEL.x=y
from A-Pool Aout
ODEN
P1REN.x
Vss
P1DIR.x
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
from Module
from Module
from Module
30K
00
01
10
11
P1.x
P1SEL 0 .x
P1SEL1.x
P1IN . x
EN 1
# EN
2
Module X IN
D
P1IES.x
Set
Q
P1 IFG .x
P1IE.x
P1IRQ.x
Figure 13. Port P1, P1.2 Input/Output
Table 14. Port P1 (P1.2) Functions
PIN NAME (P1.x)
x
FUNCTION
P1.2/TA0.2/TA0.1/TA1.2/
AOUT/TA0.CCI1A2/TA0.
CCI2A2/A3
2
(1)
CONTROL BITS/SIGNAL
(1)
P1DIR.x
P1SEL1.x
P1SEL0.x
NSELx/PSELx
ODEN
A3PSEL
General-purpose digital
I/O
In:0; Out:1
0
0
≠3
0
X
Timer0_A3 Out2
1
0
1
≠3
0
X
Timer1_A3 Out2
1
1
0
≠3
0
X
Timer0_A3 Out1
1
1
1
≠3
0
X
Analog Input - A3a
X
X
X
3
0
0
A-pool Aout
1
X
X
X
1
0
X = Don't care
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Pad Logic
to A-Pool A3b
NSEL.x=y or PSEL.x=y
from A-Pool Aout
ODEN
P1REN.x
Vss
P1DIR.x
Vcc
00
01
10
11
0
1
PortsOn
P1OUT.x
from Module
from Module
from Module
30K
00
01
10
11
P1.x
P1 SEL 0.x
P1 SEL1.x
P1IN . x
EN 1
# EN
2
Module X IN
D
P1 IES. x
Set
Q
P1 IFG. x
P1IE.x
P1 IRQ. x
Figure 14. Port P1, P1.3 Input/Output
Table 15. Port P1 (P1.3) Functions
PIN NAME (P1.x)
x
P1.3/TA0.2/TA0.1/TA1.2/
REFOUT/TA0.CCI1A3/T
A0.CCI2A3/A3
3
FUNCTION
CONTROL BITS/SIGNALS
(1)
P1DIR.x
P1SEL1.x
P1SEL0.x
NSELx/PSELx
VREFEN
A3PSEL
In:0; Out:1
0
0
≠2
0
X
Timer0_A3 Out2
1
0
1
≠2
0
X
Timer1_A3 Out1
1
1
0
≠2
0
X
Timer0_A3 Out2
1
1
1
≠2
0
X
A-Pool Analog Input A3b
X
X
X
2
0
0
A-Pool Vref
X
X
X
X
1
X
General-purpose digital
I/O
Timer0_A3 CCR1A3
Timer0_A3 CCR2A3
(1)
56
X = Don't care
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P1 REN. x
Pad Logic
P1DIR.x
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1 OUT.x
Module X OUT
Module X OUT
Module X OUT
00
01
10
11
PAD P1.x
P1 SEL0.x
P1 SEL1.x
P1IN.x
EN1
# EN2
Module X IN
D
P1 IES.x
Set
Q
P1IFG.x
P1IE.x
P1 IRQ.x
Figure 15. Port P1, P1.5 to P1.6 Input/Output
Table 16. Port P1 (P1.5 to P1.6) Functions
PIN NAME (P1.x)
x
P1.5/TA0.2/TA1.2/TA0.1
5
P1.6/TA0.2/TA1.2/TA0.1
(1)
6
FUNCTION
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL1.x
P1SEL0.x
I:0; O:1
0
0
Timer0_A3 Out2
1
0
1
Timer1_A3 Out2
1
1
0
Timer0_A3 Out1
1
1
1
Timer0_A3 CCR1A3
0
≠0
≠0
I:0; O:1
0
0
Timer0_A3 Out2
1
0
1
Timer1_A3 Out2
1
1
0
Timer1_A3 Out1
1
1
1
Timer1_A2 CCR1B0
0
≠0
≠0
General-purpose digital I/O
General-purpose digital I/O
X = Don't care
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P2 REN. x
VDDIO
P 2 DIR .x
VCC
00
01
10
11
10K
PortsOn
P2OUT.x
Module X OUT
Module X OUT
Module X OUT
00
01
10
11
P2.x
P2 SEL0.x
P2 SEL1.x
P2IN.x
# EN1
EN2
Module X IN
D
P2 IES.x
Set
Q
P2IFG.x
P2IE.x
P2 IRQ.x
Figure 16. Port P2, P2.0, P2.1, P2.2 and P2.3, Input/Output
Table 17. Port P2 (P2.0 to P2.2) Functions
PIN NAME (P2.x)
TCK/P2.0/TA1.2/TA1.1/CxOUT
(1)
(2)
(3)
(4)
58
x
FUNCTION
0
General-purpose digital I/O
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL1.x
P2SEL0.x
JTAG Mode
I:0; O:1
0
0
0
Timer1_A3 Out1
1
0
1
0
Timer1_A3 Out2
1
1
0
0
CxOUT from Apool
1
1
1
0
JTAG-TCK (2) (3) (4)
x
x
x
1
X = Don't care
JTAG signals TMS,TCK and TDI read as "1" when not configured as explicit JTAG terminals.
JTAG overrides digital output control when configured as explicit JTAG terminals.
JTAG function with enabled pull up resistors is default after power up.
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Table 17. Port P2 (P2.0 to P2.2) Functions (continued)
PIN NAME (P2.x)
TMS/P2.1/ EXT_CLK/TA0.1/TA0.2
TDI/P2.2/HF_CLK/CxOUT/TA1.0
x
FUNCTION
1
General-purpose digital I/O
2
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL1.x
P2SEL0.x
JTAG Mode
I:0; O:1
0
0
0
EXT_CLK Out
1
0
1
0
Timer0_A3 Out1
1
1
0
0
Timer0_A3 Out2
1
1
1
0
JTAG-TMS (2) (3) (4)
x
x
x
1
I:0; O:1
0
0
0
HF_CLK Out
1
0
1
0
Timer1_A3 Out0
1
1
0
0
CxOUT from Apool
1
1
1
0
JTAG-TDI (2) (3) (4)
X
X
X
1
General-purpose digital I/O
Port P2, P2.3, Input/Output
Table 18. Port P2 (P2.3) Functions
PIN NAME (P2.x)
TDO/P2.3/LFCLK/TA0.2
x
3
FUNCTION
General-purpose digital I/O
P2DIR.x
P2SEL1.x
P2SEL0.x
I:0; O:1
0
0
LFCLK Out
1
0
1
Timer0_A3 Out2
1
1
0
1
1
1
JTAG-TDO
(1)
(2)
(3)
CONTROL BITS/SIGNALS (1)
(2) (3)
X = Don't care
Configuring P2.3 to JTAG-TDO turns P2.0 to P2.3 also into JTAG functions
JTAG function with disabled pull up resistors is default after power up.
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P3REN.0
xt_byp
35K
EN
P3OUT.0
P3IN.0
1
CLKIN/XIN/P3.0
XOUT/P3.1
32KHz
XTAL
0
EN#
EN
P3IN.1
xt_byp
P3OUT.1
EN
35K
P3REN.1
disable_p3_1
Figure 17. Port P3, P3.0, P3.1 Input/Output
60
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Pad Logic
P1 REN . x
P 1 DIR. x
00
Vss
0
Vcc
1
01
10
11
PortsOn
P 1 OUT.x
00
Module X OUT
01
Module X OUT
10
Module X OUT
11
P1.x
P 1 SEL0. x
P 1 SEL1. x
disable_p3_2
P 1 IN. x
EN1
#EN2
Module X IN
D
P1 IES. x
Set
Q
P1 IFG. x
P 1 IE. x
P 1IRQ. x
Figure 18. Port P3, P3.2, P3.4 Input/Output
Table 19. Port P3 (P3.2, P3.4, P3.5) Functions
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
disable_p3_x
I:0; O:1
0
0
I:0; O:X
Timer0_A3 Out1 output
1
0
1
X
Timer1_A3 Out1 output
1
1
0
X
Timer1_A3 Out0 output
1
1
1
X
I:0; O:1
0
0
In:0; Out:X
Timer0_A3 Out1 output
1
0
1
X
Timer1_A3 Out1 output
1
1
0
X
Timer1_A3 Out0 output
1
1
1
X
Timer1_A3 CCR2A2 capture: CCI2A2 input
compare
X
X
X
0
General-purpose digital I/O
P3.2/ TA0.1/TA1.1/TA1.0
2
General-purpose digital I/O
P3.4/TA0.1/TA1.1/TA1.0/
TA1.CCI2A2
(1)
4
CONTROL BITS/SIGNALS (1)
Don't Care
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Table 19. Port P3 (P3.2, P3.4, P3.5) Functions (continued)
PIN NAME (P3.x)
x
CONTROL BITS/SIGNALS (1)
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
disable_p3_x
I:0; O:1
0
0
In:0; Out:X
Timer0_A3 Out1 output
1
0
1
X
Timer1_A3 Out1 output
1
1
0
X
Timer1_A3 Out0 output
1
1
1
X
Timer1_A3 CCR2A3 capture: CCI2A3 input,
compare
X
X
X
0
General-purpose digital I/O
P3.5/TA0.1/TA1.1/TA1.0/
TA1.CCI2A3
5
Table 20. Port P3 (P3.6) Functions
PIN NAME (P3.x)
x
P3DIR.x
P3SEL1.x
P3SEL0.x
Sel_port3_6<1:0>
In:0; Out:1
0
0
XX
Timer0_A3 Out0 output
1
0
1
00
Timer0_A3 Out1 output
1
0
1
01
Timer0_A3 Out2 output
1
0
1
10
Timer1_A3 Out1 output
1
0
1
11
Timer0_A3 Out0# output
1
1
0
00
Timer0_A3 Out1# output
1
1
0
01
Timer0_A3 Out2# output
1
1
0
10
Timer1_A3 Out1# output
1
1
0
11
BOR Out
1
1
1
00
Activation Sense Output
1
1
1
01
LFCLK Out
1
1
1
10
CP 1.8V OK Out
1
1
1
11
Timer1_A3 CCR1A3 capture: CCI1A3 input,
compare
X
X
X
XX
10mA General-purpose digital I/O
P3.6/TA0.0/TA0.1/TA0.2/TA0.0
N/
TA0.1N/TA0.2N/TA1.CCI1A3/
TA1.1/BOR/ACTSEN/LFOSC/C
P18OK
(1)
6
CONTROL BITS/SIGNALS (1)
FUNCTION
Don't Care
Table 21. Port P3 (P3.7) Functions
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL1.x
P3SEL0.x
Sel_port3_7<1:0>
In:0; Out:1
0
0
XX
Timer0_A3 Out0 output
1
0
1
00
Timer0_A3 Out1 output
1
0
1
01
Timer0_A3 Out2 output
1
0
1
10
LCD Voltage Comparator Out
1
0
1
11
Timer0_A3 Out0# output
1
1
0
00
Timer0_A3 Out1# output
1
1
0
01
Timer0_A3 Out2# output
1
1
0
10
LCD Voltage Comparator Out#
1
1
0
11
LCD Charge Pump Clock Out
1
1
1
00
LCD Frame Clock Out
1
1
1
01
HFCLK Out
1
1
1
10
1Khz Activation Clock Out
1
1
1
11
10mA General-purpose digital I/O
P3.7/TA0.0/TA0.1/TA0.2/TA0.0
N/TA0.1N/
TA0.2N/TA1.CCI2A1/HFOSC/L
CDCPCLK/
LCDFCLK/1KCLK/LCDCMP
7
CONTROL BITS/SIGNALS (1)
Timer1_A3 CCR2A1 capture: CCI2A1 input,
compare
(1)
62
Don't Care
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Pad Logic
to A- Pool
From Apool Register
from LDO1V
from LDO_IO_sel
P 3 REN.x
Vss
P3DIR.x
0
Vcc 1
00
01
10
11
PortsOn
P3OUT.x
from Module
from Module
from Module
P3SEL0.x
30K
00
01
10
11
P3.x
P3SEL1.x
P3IN. x
EN1
# EN
2
Module X IN
D
P3IES. x
Set
Q
P3IFG. x
P3IE.x
P3IRQ. x
Figure 19. Port P3, P3.3, Input/Output
Table 22. Port P3 (P3.3) Functions
CONTROL BITS/SIGNALS (1)
PIN NAME (P3.x)
x
P3.3/ TA0.1/TA1.1/TA1.0/A0/LDO1
3
(1)
FUNCTION
General-purpose digital I/O
P1DIR.x
P1SEL1.x
P1SEL0.x
NSELx/PSELx
LDO_IO_sel
<3-0>
In:0; Out:1
0
0
0
0XXX
Timer0_A3 Out1 output
1
0
1
0
0XXX
Timer1_A3 Out1 output
1
1
0
0
0XXX
Timer1_A3 Out0 output
1
1
1
0
0XXX
Analog input A0 – A-Pool
X
X
X
0
XXXX
LDO 1V Out
1
X
X
X
1XXX
X = Don't care
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P3 REN. 6
Sel_port3_6<0>
Sel_port3_6<1>
TA0.0
TA0.1
TA0.2
TA1.1
TA0.0 #
TA0.1 #
TA0.2 #
TA1.1 #
BROWNOUT
ACTIVATION _SENSE
LFCLK
CP_1P8_COMP
VDDIO
P 3 DIR 6
00
01
10
11
VCC
00
01
10
11
10K
PortsOn
P3OUT.6
00
01
10
11
00
01
10
11
PAD3.6
10mA
P3 SEL0.6
P3 SEL1.6
P3IN.6
00
01
10
11
# EN1
EN2
Module X IN
D
P3 IES.6
Set
Q
P3IFG.6
P3IE.6
P3 IRQ.6
Figure 20. Port P3, P3.6, Input/Output
P3 REN. 7
Sel_port3_7<4>
Sel_port3_7<5>
TA0.0
TA0.1
TA0.2
LCD_COMP
TA0.0 #
TA0.1 #
TA0.2 #
LCD_COMP #
LCD_CP_CLK
LCD_FCLK
HFCLK
ACTIVATION _OSC_1KHZ
VDDIO
P 3 DIR 7
00
01
10
11
00
01
10
11
10K
PortsOn
P3OUT.7
00
01
10
11
VCC
00
01
10
11
00
01
10
11
PAD3.7
10mA
P3 SEL0.7
P3 SEL1.7
P3IN.7
# EN1
EN2
Module X IN
D
P3 IES.7
Set
Q
P3 IRQ.7
P3IFG.7
P3IE.7
Figure 21. Port P3, P3.7, Input/Output
64
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Pad Logic
from Ana_test_mux
from Ana_test_mux_sel
P4REN.x
Vss
P4DIR.x
0
Vcc 1
00
01
10
11
PortsOn
30K
P4OUT.x
from Module
from Module
from Module
P4SEL0.x
00
01
10
11
P4.x
P4SEL1.x
P4IN. x
EN1
# EN
2
Module X IN
D
P4IES. x
Set
Q
P4IFG. x
P4IE.x
P4IRQ. x
Figure 22. Port P4 (P4.0) Pin Input/Output
Table 23. Port P4 (P4.0) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
Ana_test_mux<3:0>
I:0; O:1
0
0
0
Timer0_A3 Out2 output
1
0
1
0
Timer1_A3 Out2 output
1
1
0
0
ACLK Out
1
1
1
General-purpose digital I/O
P4.0/TA0.2/TA1.2/ACLK/ATEST/SPI_
CS
0
CONTROL BITS/SIGNALS (1)
Analog Test Multiplexer Out
SPI Chip Select
(1)
0
/=0
1
0
0
0
Don't Care
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P1 REN. x
Pad Logic
P1DIR.x
Vss
Vcc
00
01
10
11
0
1
PortsOn
P1 OUT.x
Module X OUT
Module X OUT
Module X OUT
00
01
10
11
PAD P1.x
P1 SEL0.x
P1 SEL1.x
P1IN.x
# EN1
EN2
Module X IN
D
P1 IES.x
Set
Q
P1IFG.x
P1IE.x
P1 IRQ.x
Figure 23. Port P4 (P4.1, P4.2, P4.3) Pin Input/Output
Table 24. Port P4 (P4.1, P4.2, P4.3) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL1.x
P4SEL0.x
I:0; O:1
0
0
Timer0_A3 Out2 output
1
0
1
Timer1_A3 Out2 output
1
1
0
SMCLK Out
0
1
1
SPI Serial In
0
0
0
I:0; O:1
0
0
Timer0_A3 Out2 output
1
0
1
Timer1_A3 Out2 output
1
1
0
MCLK Out
0
1
1
SPI Clock Out
1
0
0
I:0; O:1
0
0
Timer0_A3 Out2 output
1
0
1
Timer1_A3 Out2 output
1
1
0
1Khz Activation Oscillator Out
0
1
1
SPI Serial Out
1
0
0
General-purpose digital I/O
P4.1/TA0.2/TA1.2/SMCLK/
SPI_MOSI
1
General-purpose digital I/O
P4.2/TA0.2/TA1.2/MCLK/
SPI_CLK
2
General-purpose digital I/O
P4.3/TA0.2/TA1.2/1KOSC/
SPI_MISO
(1)
66
3
CONTROL BITS/SIGNALS (1)
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2012
PACKAGING INFORMATION
Orderable Device
AFE4110B000YS
Status
(1)
ACTIVE
Package Type Package
Drawing
WAFERSALE
YS
Pins
Package Qty
0
1
Eco Plan
TBD
(2)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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