AIC1384 DDR Termination Regulator DESCRIPTION FEATURES The AIC1384 linear regulator is designed to deliver 1.5A continuous current and up to 3A peak transient currents for termination of DDRSRAM. The AIC1384 contains a high-speed operational amplifier to supply superior load transient response. It also includes a VSENSE to provide excellent load regulation and VREF output as a reference for the chipset and DIMMs. The AIC1384 supply accurate VTT and VREF without external resistors that save PCB areas. Source and Sink Current Capability Suspend To RAM Functionality Support DDRⅠ (1.25VTT) and DDRⅡ (0.9VTT) Requirements Low Output Voltage Offset, ±20mV High Accuracy Output Voltage at Full-Load Low External Component Count No external resistor required Current Limit protection Thermal Protection The AIC1384 also features an active low shutdown pin that provides Suspend To RAM (STR) functionality. The VTT will remain high impedance when in shutdown, but VREF will keep active. The advantage of power saving can be obtained through low 150µA (DDRⅠ) quiescent current. SOP-8 and SOP-8 Exposed Pad (Heat Sink) Package APPLICATIONS Mother board Graphic cards DDRⅠ and DDRⅡ termination voltage Built in current limiting in source and sink mode, with thermal shutdown provide maximal protection to the AIC1384 against fault conditions. TYPICAL APPLICATION CIRCUIT 1 2 SD 3 VREF=1.25V 4 GND SD PVIN VSENSE AVIN VREF 10nF Analog Integrations Corporation VTT VDDQ AIC1384 VTT=1.25V Cout 22uF 8 7 VIN=2.5V 6 5 VDDQ=2.5V Cin 47uF Si-Soft Research Center DS-1384G-01 073108 3A1, No.1, Li-Hsin Rd. I , Science Park , Hsinchu 300, Taiwan , R.O.C. TEL: 886-3-5772500 FAX: 886-3-5772510 www.analog.com.tw 1 AIC1384 ORDERING INFORMATION AIC1384XXXX PIN CONFIGURATION PACKING TYPE TR: TAPE & REEL TB: TUBE SOP-8 TOP VIEW GND 1 PACKAGING TYPE S: SOP-8 SH: SOP-8 Exposed Pad (Heat Sink) 8 VTT SD 2 7 PVIN VSENSE 3 6 AVIN 5 VDDQ VREF 4 SOP-8 Exposed Pad (Heat Sink) TOP VIEW P: Lead Free Commercial G: Green Package GND 1 SD 2 Example: AIC1384PSTR In Lead Free SOP-8 Package & VSENSE 3 8 VTT (GND) VREF 4 7 PVIN 6 AVIN 5 VDDQ Taping & Reel Packing Type ABSOLUTE MAXIMUM RATINGS PVIN, AVIN, VDDQ, SD , VSENSE, VREF, VTT, to GND 6.0V -40°C ~ 85°C Operating Temperature Range 125°C Junction Temperature Storage Temperature Range - 65°C ~ 150°C 260°C Lead Temperature (Soldering. 10 sec) Thermal Resistance Junction to Ambient, RθJA (Assume no ambient airflow, no heatsink) SOP-8 Thermal Resistance Junction to Case, RθJC 160°C /W SOP-8 Exposed Pad (Heat Sink) 60°C /W SOP-8 40°C /W SOP-8 Exposed Pad (Heat Sink) 16°C /W Absolute Maximum Ratings are those values beyond which the life of a device may be Impaired. TEST CIRCUIT Refer to TYPICAL APPLICATION CIRCUIT. 2 AIC1384 ELECTRICAL CHARACTERISTICS (AVIN=2.5V, PVIN=VDDQ=1.8V / 2.5V, TA=25°C, unless otherwise specified) (Note 1) PARAMETER CONDITIONS SYMBOL MIN AVIN 2.2 PVIN 1.6 2.5/1.8 0.83 0.85 0.87 0.88 0.90 0.92 VDDQ = 1.9V 0.93 0.95 0.97 VDDQ = 2.3V 1.127 1.15 1.177 1.227 1.25 1.277 1.327 1.35 1.377 0.81 0.85 0.89 0.86 0.90 0.94 0.91 0.95 0.99 1.116 1.15 1.181 1.216 1.25 1.281 1.316 1.35 1.381 Input Voltage (DDR1/2) VDDQ = 1.7V VDDQ = 1.8V Reference Voltage VDDQ = 2.5V VREF VREF VDDQ = 2.7V TYP MAX 5.5 UNITS V V V IOUT = 0A, +0.9A, -0.9A VDDQ = 1.7V VDDQ = 1.8V VTT Output Voltage VTT VDDQ = 1.9V IOUT = 0A, +1.5A, -1.5A VDDQ = 2.3V VDDQ = 2.5V VTT VDDQ = 2.7V VTT Output Voltage Offset IOUT = 0A (for DDR I) IOUT =+1.5A/ -1.5A VTT Output Voltage Offset IOUT = 0A (for DDR II) IOUT =+0.9A/ -0.9A VOS VOS -20 20 -25 25 -40 40 -40 40 VDDQ = 2.5V, VREF Output Impendence IREF = -30µA to +30µA VDDQ = 1.8V, Quiescent Current PVIN = 2.5V PVIN = 1.8V ZVREF VTT Leakage Current in Shutdown IIL IQ-AVIN SD = 0V ISD-AVIN ISENSE SD = 0V, VTT = 1.25V mV mV kΩ 2.5 IOUT = 0A VSENSE Input Current V 2.5 IREF = -20µA to +20µA Current Limit V ILK-TT 3.0 A 1.6 320 500 150 13 µA nA 10 µA 3 AIC1384 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER Shutdown Leakage Current Shutdown Threshold Thermal Shutdown Temperature Thermal Shutdown Hysteresis CONDITIONS SD = 0V SYMBOL MIN ILK-SD Output ON VIH Output OFF VIL TSD TYP MAX UNITS 2 5 µA 1.9 0.8 V 165 °C 20 °C Note1: Specifications are production tested at TA=25°C. Specifications over the -40°C to 85°C operating temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). Note 2: VOS is the voltage measurement, which is defined as VTT subtracted VREF. Note 3: Load regulation and Current Limit are measured at constant junction temperature, by using pulse test with a short ON time. 4 AIC1384 TYPICAL PERFORMANCE CHARACTERISTICS 290 112 280 270 104 IQ (uA) IQ(uA) 108 100 260 250 240 96 230 92 220 88 2.0 210 2.5 3.5 4.0 AVIN (V) 3.0 4.5 5.0 200 2.0 5.5 2.5 1.32 3.5 1.30 2.5 VIL 1.0 1.20 3.0 3.5 4.0 AVIN (V) 4.5 5.0 1.18 -30 5.5 AVIN vs. VSD 3.0 2.5 2.5 2.0 2.0 1.5 1.0 0.5 0.5 1 2 3 VDDQ (V) Fig.5 0 10 20 30 5 6 1.5 1.0 0 -10 Fig.4 VREF vs. IREF 3.0 0.0 -20 IREF (uA) VTT (V) VREF (V) Fig.3 5.5 1.24 1.22 2.5 5.0 1.26 1.5 0.5 2.0 4.5 1.28 VIH VREF (V) VSD (V) 4.0 2.0 4.0 3.5 AVIN (V) Fig.2 IQ vs. AVIN Fig. 1 IQ vs. AVIN in Shutdown 3.0 3.0 4 VREF vs. VDDQ 5 6 0.0 0 1 2 Fig.6 3 VDDQ (V) 4 VTT vs. VDDQ 5 AIC1384 1.4 2.6 1.2 2.4 1.0 0.8 0.6 0.4 0.2 0.0 2.0 Fig.7 2.5 3.0 3.5 4.0 4.5 2.2 2.0 1.8 1.6 1.4 1.2 2.0 5.5 5.0 Fig.8 Maximum Sourcing Current vs. AVIN (VDDQ=2.5V , PVIN=1.8V) 4.0 1.6 3.8 1.4 3.6 3.4 3.2 3.0 2.8 2.6 2.4 3.0 Fig.9 3.5 4.0 4.5 AVIN (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) AVIN (V) OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A) TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 5.0 5.5 Maximum Sourcing Current vs AVIN (VDDQ=2.5V , PVIN=3.3V) Maximum Sourcing Current vs AVIN (VDDQ=2.5V , PVIN=2.5V) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 Fig.10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) Maximum Sourcing Current vs. AVIN (VDDQ=1.8V, PVIN =1.8V) OUTPUT CURRENT (A) 4.0 3.8 3.6 3.4 3.2 3.0 2.8 3.0 Fig.11 3.5 4.0 4.5 5.0 5.5 AVIN (V) Maximum Sourcing Current vs. AVIN (VDDQ=1.8V, PVIN =3.3V) 6 AIC1384 3.4 3.0 3.2 2.8 OUTPUT CURRENT (A) OUTPUT CURRENT (A) TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 3.0 2.8 2.6 2.4 2.2 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Fig.12 2.4 2.2 2.0 1.8 1.6 1.4 2.0 5.5 AVIN (V) 2.6 2.5 Fig.13 Maximum Sinking Current vs. AVIN (VDDQ=2.5V ) 3.0 4.5 5.0 5.5 AVIN (V) Maximum Sinking Current vs. AVIN (VDDQ =1.8V ) Q IN 280 108 270 o 0C 104 260 o o 25 C o 0C 25 C 100 o -40 C 250 o -40 C 85 C 96 o 125 C 92 IQ (uA) o o IQ (uA) 4.0 3.5 85 C 240 o 125 C 230 220 88 84 2.0 210 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVIN (V) Fig14 IQ vs. AVIN in Shutdown Fig15 IQ vs. AVIN 1.266 1.264 1.262 1.260 o 125 C 1.258 1.256 o -40 C VTT (V) 1.254 1.252 1.250 1.248 o -40 C 1.246 1.244 1.242 1.240 o 125 C 1.238 -100 -75 -50 -25 0 25 50 75 100 IOUT (mA) Fig16 VTT vs. IOUT 7 AIC1384 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Iout Iout VTT VTT Cin: 47uF electrolytic capacitor Cout: 220uF electrolytic capacitor Fig.17 -1.5A to +1.5A load transient Cin: 47uF ceramic capacitor Cout: 22uF ceramic capacitor Fig.18 Iout Iout VTT VTT Cin: 47uF ceramic capacitor Cout: 22uF ceramic capacitor Cin: 47uF electrolytic capacitor Cout: 220uF electrolytic capacitor Fig.19 -0.9A to +0.9A load transient -1.5A to +1.5A load transient Fig.20 -0.9A to +0.9A load transient 8 AIC1384 BLOCK DIAGRAM SD VDDQ AVIN PVIN 50k VREF + + - VTT 50k VSENSE GND PIN DESCRIPTION Pin 1: GND - Ground. Pin 2: SD - Active low shutdown pin. Pin 3: VSENSE - Sense VTT to improve load regulation. Pin 4: VREF - Buffered output of internal reference voltage, equal to VDDQ/2. Pin 5: VDDQ - Input voltage to internal reference voltage for regulating VTT. Pin 6: AVIN - Analog input voltage to supply internal control circuitry. Pin 7: PVIN - Power input voltage to supply the rail voltage exclusively for the output stage used to create VTT. Pin 8: VTT - Regulated VDDQ/2. Heat Sink output, equal to - Recommended to Connect to GND. 9 AIC1384 APPLICATION INFORMATION The AIC1384 linear termination regulator is increase at high PVIN. Connect AVIN and PVIN designed to meet JEDEC requirements of DDR- together with 2.5V is a good compromise in SDRAM (DDRⅠ/Ⅱ). The VTT is able to deliver SSTL-2 applications. This reduces the need for sinking and sourcing current while regulating the bypassing two supply pins separately. For the voltage equal to VDDQ/2. The output stage safe operation of the system; AVIN must always includes a sense function to maintain excellent exceed or equal to PVIN. load regulation to prevent shoot through. The power part has two distinct rails that split the internal analog circuitry from power output stage, which results in reducing internal power disspation. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is necessary to prevent data error from signal reflections while transmitting at VDDQ VDDQ is used to make internal reference voltage for regulating VTT. And VTT will track VDDQ/2 precisely because of internal resistor divider. For SSTL-2 application, connect VDDQ to the 2.5V rail directly at the DIMM instead of AVIN and PVIN to achieve that reference voltage tracks the DDR memory rails accurately without a voltage drop from power lines. high frequencies encountered with DDR-SDRAM. VSENSE The achievement of single parallel termination The sense pin is used to improve remote load can be seen as below figure. regulation. The termination resistors in most VIN motherboards connect to VTT with a long trace VTT that will cause a significant voltage drop. The VSENSE pin can improve that a lower termination RT voltage at one end of the bus than the other by Memory ChipSet RS connecting it to the middle of the bus. If a long VREF VSENSE trace is implemented close to the memory, noise pickup can be a problem in precise Between the chipset and memory are one RS series resistor and one RT termination resistor. Both RS and RT are 25 Ohms typically; they can regulation of VTT. A small 0.1µF ceramic capacitor can be used for filtering noise. VSENSE pin must still tie to VTT if remote load regulation is not used. be altered to scale the current requirements from VREF the AIC1384. VREF provides the buffered output of the internal VDDQ/2 reference voltage. It can be used to AVIN and PVIN AVIN and PVIN have the ability to work with separate supplies depending on the application. Higher PVIN will increase the maximum continuous output current resulting from output RDS-ON limitations at voltages close to VTT. Oppositely, the internal power dissipation will also support the reference voltage for the Northbridge chipset and memory. The VREF remains active during the shutdown state and thermal shutdown for the Suspend to RAM functionality. A bypass capacitor, located close to the VREF pin, can be used to improve performance. Ranging from 10 AIC1384 0.01µF to 0.1µF of ceramic capacitor is recommended. VTT VTT is the regulated output that is used to terminate the bus resistor, which obtains the ability of sinking and sourcing current while regulating the output accurately to VDDQ/2. The AIC1384 is designed to deliver up to ±3A peak transient currents with excellent transient response. The output capacitor should be large enough to prevent an excessive voltage drop if a transient is expected to last above the maximum continuous current rating for a significant amount of time. AIC1384 is able to provide large transient output currents, yet it can’t handle for long durations under all conditions that results from the standard packages are not able to dissipate the heat of the internal power loss. If large currents are required for longer durations, ensure that the maximum junction temperature is not exceeded. Capacitor Selection The input capacitor of AIC1384 is required for improved performance during large load transients to prevent the input rail from dropping. 47µF aluminum electrolytic capacitors or ceramic capacitor is recommended. If AVIN and PVIN are separated, the 47µF capacitor should be placed Thermal Dissipation The AIC1384 has a thermal-limiting circuitry, which is designed to protect the device against overload condition. For continuous load condition, maximum rating of junction temperature must not be exceeded. It is important to pay more attention in thermal resistance. It includes junction to case, junction to ambient. The maximum power dissipation of AIC1384 depends on the thermal resistance of its case and circuit board, the temperature difference between the die junction and ambient air, and the rate of airflow. The thermal resistance is greatly affected by the package used, the number of vias, the speed of airflow and the thickness of copper. When the IC mounting with good thermal conductivity is used, the junction temperature will be low even when large power dissipation applies. So the PCB mounting pad for GND pin of AIC1384 should provide maximum thermal conductivity to maintain low device temperature. The power dissipation across the device is P = IOUT (VIN-VOUT). The maximum power dissipation is: (T - TA ) PMAX = J-max Rθ JA Where TJ-max is the maximum allowable junction temperature (125°C), and TA is the ambient temperature suitable in application. as close as possible to the PVIN. And AVIN can Layout Considerations bypass a 0.1uF ceramic capacitor to prevent 1. Minimize high current ground loops. Place the ground of the device, the input capacitor, and the output capacitor together with short and wide connection. 2. Connect the bottom-side pad (available in SOP-8 Exposed Pad) to a large ground plane. Use as much copper as possible to decrease the thermal resistance of the device. 3. A buried layer may be used as a heat spreader if the large copper around the excessive noise. 220µF aluminum electrolytic capacitor is a recommendation for output capacitor to improve load transient response of VTT. And size above 22uF ceramic output capacitor is allowed to general used for obtain small profile. The value of ESR is determined by the acceptable maximum current spike and the output voltage droops. 11 AIC1384 device is not available. Use vias to lead the heat into the buried layer. 4. The input capacitor should be placed as close as possible to the PVIN pin. 5. A bypass capacitor, located close to the VREF pin, can be used to improve performance. Ranging from 0.01µF to 0.1µF of ceramic capacitor is recommended. 6. If long sense traces is used, the noise of VSENSE trace may occurs which from switching I/O signals. A 0.1uF ceramic capacitor connects to the VSENSE pin can be used to filter high frequency signal. APPLICATION EXAMPLES DDRⅠ Application VTT=1.25V Cout 1 2 SD 3 VREF=1.25V 4 GND SD PVIN VSENSE AVIN VREF All the input rails connect to 2.5V rail is 8 VTT 7 VIN=2.5V 6 5 VDDQ recommend for the SSTL-2 termination scheme application. The circuitry completes an optimal power dissipation and component count. Cin VDDQ=2.5V AIC1384 10nF 1 2 SD 3 VREF=1.25V 4 GND PVIN VSENSE AVIN VREF 7 the maximum continuous output current if 1.8V and VIN=3.3V 6 5 VDDQ from PVIN can never exceed AVIN. VTT=1.25V 1 2 3 VREF=1.25V 10nF temperature to exceed the maximum due to large limited to operation on the 3.3V or 5V rail results Cout SD 2.5V rail are not available. Beware the junction current level. In this configuration AVIN will be Cin VDDQ=2.5V AIC1384 10nF Connect the AIC1384 power rail to 3.3V to provide 8 VTT SD VTT=1.25V Cout 4 GND VTT SD PVIN VSENSE AVIN VREF AIC1384 VDDQ separate supplies. 8 7 6 1.8V Cin 0.1uF PVIN can be operated on a lower 1.8V rail and the AVIN can be connected to a higher rail. Although this circuitry can obtain better 2.2~5.5V 5 VDDQ=2.5V AVIN and PVIN have the ability to work with efficiency, but the maximum continuous current is reduced due to the lower rail voltage. Increasing the output capacitance can also help for large load transients. 12 AIC1384 DDRⅡ Application VTT=0.9V Cout 1 2 SD 3 4 VREF=0.9V GND VTT SD PVIN VSENSE AVIN VREF VDDQ 1 2 SD 3 4 VREF=0.9V GND VTT SD PVIN VSENSE AVIN VREF VDDQ 1.8V 6 2.2~5.5V 5 Cin 5V rail. VTT=0.9V Connect the power rail to 3.3V to provide a higher continuous output current if 1.8V rail is not VIN=3.3V 6 available. Careful with the junction temperature that may exceed the maximum due to the thermal dissipation Cin 5 the AVIN pin can be connected to either a 3.3V or Cout 8 7 The output stage is connected to the 1.8V rail and 0.1uF increases with lower VTT output voltages. In this configuration PVIN will be limited VDDQ=1.8V AIC1384 10nF 7 VDDQ=1.8V AIC1384 10nF The circuit is recommended for DDR-II applications. 8 to operation on the 3.3V rail. Level Shifting Application 1 R1 2 3 R2 4 GND SD VSENSE VREF VTT PVIN AVIN VDDQ R1 2 3 R2 4 GND SD VSENSE VREF AIC1384 The AIC1384 is available to scale the output to any Cout voltage required. One method is to level shift the 8 output above the internal reference voltage of 7 VDDQ/2 by using two resistors from the VTT to the VIN 6 VSENSE. The correct voltage at VTT is VTT = VDDQ/2 (1 + R1/R2) Cin 5 VDDQ AIC1384 1 VTT VTT PVIN AVIN VDDQ VTT Another method is to level shift the output below Cout the internal reference voltage of VDDQ/2 by using 8 two resistors from the VSENSE and VDDQ. The 7 VIN 6 correct voltage at VTT is VTT = VDDQ/2 (1 - R1/R2) Cin 5 VDDQ 13 AIC1384 PHYSICAL DIMENSIONS (unit: mm) SOP- 8 D h X 45° E A SOP-8 MILLIMETERS MIN. MAX. A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e SEE VIEW B A e A H S Y M B O L 1.27 BSC H 5.80 h 0.25 0.50 L 0.40 1.27 0° 8° θ 6.20 WITH PLATING 0.25 C A1 B GAUGE PLANE SEATING PLANE θ L VIEW B BASE METAL SECTION A-A Note: 1. Refer to JEDEC MS-012AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 14 AIC1384 SOP- 8 Exposed Pad (Heat Sink) D S Y M B O L h X 45° E A A SEE VIEW B MIN. MAX. 1.35 1.75 WITH PLATING 0.25 C A1 B 0.00 0.15 0.31 0.51 C 0.17 0.25 D 4.80 5.00 E 3.80 4.00 1.27 BSC H 5.80 h 0.25 0.50 L 0.40 1.27 6.20 q 0° 8° D1 1.5 3.5 E1 1.0 2.55 BASE METAL SECTION A-A GAUGE PLANE SEATING PLANE θ L VIEW B A1 B e A e H E1 MILLIMETERS A D1 EXPOSED THERMAL PAD(Heat Sink) (BOTTOM CENTER OF PACKAGE) SOP-8 Exposed Pad(Heat Sink) Note : 1. Refer to JEDEC MS-012E. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Note: Information provided by AIC is believed to be accurate and reliable. However, we cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AIC product; nor for any infringement of patents or other rights of third parties that may result from its use. We reserve the right to change the circuitry and specifications without notice. Life Support Policy: AIC does not authorize any AIC product for use in life support devices and/or systems. Life support devices or systems are devices or systems which, (I) are intended for surgical implant into the body or (ii) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 15