UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the UR5595 can provide superior load regulation. The UR5595 provides a VREF output as the reference for the application of the chipset and DIMMs. The output, VTT, is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The output stage has been designed to maintain excellent load regulation and with fast response time to minimum the transition preventing shoot-through. The UTC UR5595 also incorporates two distinct power rails that separates the analog circuitry (AVIN) from the power output stage (PVIN). This power rail split can be utilized to reduce the internal power dissipation. And this also permits UTC UR5595 to provide a termination solution for DDRII SDRAM. Lead-free: UR5595L Halogen-free: UR5595G FEATURES * Power regulating with driving and sinking capability * Low output voltage offset * No external resistors required * Low external component count * Linear topology * Low cost and easy to use * Thermal shutdown protection ORDERING INFORMATION Normal UR5595-S08-R UR5595-SH2-R Ordering Number Lead Free UR5595L-S08-R UR5595L-SH2-R Halogen Free UR5595G-S08-R UR5595G-SH2-R www.unisonic.com.tw Copyright © 2009 Unisonic Technologies Co., Ltd Package Packing SOP-8 HSOP-8 Tape Reel Tape Reel 1 of 12 QW-R502-062.B UR5595 CMOS IC PIN CONFIGURATION PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 PIN NAME NC GND VSENSE VREF VDDQ AVIN PVIN VTT DESCRIPTION No internal connection. Can be used for vias. Ground. Feedback pin for regulating VOUT. Buffered internal reference voltage of VDDQ/2. Input for internal reference equal to VDDQ/2. Analog input pin. Power input pin. Output voltage for connection to termination resistors. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 12 QW-R502-062.B UR5595 CMOS IC BLOCK DIAGRAM UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 12 QW-R502-062.B UR5595 CMOS IC ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT VDD -0.3 ~ +6 V Supply Voltage VDD 2.2 ~ 5.5 V ℃ Junction Temperature TJ +150 ℃ Operation Temperature TOPR 0 ~ +125 ℃ Storage Temperature TSTG -65 ~ +150 Note: 1.Signified recommend operating range that indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. 2.Absolute maximum ratings indicate limits beyond which damage to the device may occur. PVIN, AVIN, VDDQ to GND AVIN to GND(Note 1) THERMAL DATA PARAMETER Thermal Resistance Junction-Ambient SYMBOL θJA RATINGS 150 UNIT ℃/W ELECTRICAL CHARACTERISTICS (TJ=25℃, VIN=AVIN=PVIN=2.5V, VDDQ=2.5V, unless otherwise specified). PARAMETER SYMBOL VREF Voltage VREF IOUT = 0A VTT Output Voltage VTT IOUT = ±1.5A VTT Output Voltage Offset (VREF - VTT) Quiescent Current VSENSE Input Current VREF Output Impedance VDDQ Input Impedance Thermal Shutdown Thermal Shutdown Hysteresis VO(OFF)VTT IQ ISENSE ZVREF ZVDDQ TSHDN THYS TEST CONDITIONS VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VIN = VDDQ = 2.7V VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VIN = VDDQ = 2.7V VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VIN = VDDQ = 2.7V IOUT = 0A IOUT = -1.5A IOUT = +1.5A IOUT = 0A IREF = -30 ~ +30 μA UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN 1.135 1.235 1.335 1.125 1.225 1.325 1.125 1.225 1.325 -20 -25 -25 TYP 1.158 1.258 1.358 1.159 1.259 1.359 1.159 1.259 1.359 0 0 0 320 13 2.5 100 165 10 MAX 1.185 1.285 1.385 1.190 1.290 1.390 1.190 1.290 1.390 20 25 25 500 UNIT V V mV μA nA kΩ kΩ ℃ ℃ 4 of 12 QW-R502-062.B UR5595 CMOS IC PIN DESCRIPTIONS AVIN , PVIN Input supply pins. AVIN and PVIN are two independent input supply pins for UR5595. AVIN is used to supply all the internal analog circuits and PVIN is only used to supply the output stage to create the regulated VTT. Using a higher PVIN voltages will increase the driving capability of VTT, but the internal power loss will also increase. If the junction temperature exceeds the thermal shutdown than the UR5595 will enter a shutdown state, where VTT is tri-stated and VREF remains active. For SSTL-2 applications, the AVIN and PVIN can be short together at 2.5V to eliminate the need for bypassing capacitors for the two supply pins separately. VDDQ The input pin used to create the internal reference voltage from a resistor divider of two internal 50kΩ resistors for regulating VTT and to guarantee VTT will track VDDQ/2 precisely. As a remote sense by connecting VDDQ directly to the 2.5V rail for SSTL-2 applications is an optimal implementation of VDDQ at the DIMM. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. VSENSE The sense pin supply improved remote load regulation; if remote load regulation is not used then the VSENSE pin must still be connected to VTT. A long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. Connect VSENSE pin to the middle of the bus to provide a better distribution across the entire termination bus can reduce the IR drop. VREF VREF supply the buffered output of the internal reference voltage (VDDQ/2). It can provide the reference voltage of the Northbridge chipset and memory. For better performance, a bypass ceramic capacitor of 0.1μF~0.01μF, located close to the pin, can be used to to help with noise. VTT VTT is a regulated output that is used to terminate the bus resistors of DDR-SDRAM. It can precisely track the VDDQ/2 voltage with the sinking and sourcing current capability. The UTC UR5595 is designed to handle peak transient currents of up to ± 3A with a fast transient response. If a transient is expected to remain above the maximum continuous current rating for a significant amount of time then the output capacitor size should be large enough to prevent an excessive voltage drop. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 12 QW-R502-062.B UR5595 CMOS IC CAPACITOR SELECTION A capacitor is recommended for improve input stability performance during large load transients to prevent the input power rail from dropping, especially for PVIN. The input capacitor should be located as close as possible to the PVIN pin. A typical recommended value for AL electrolytic capacitors is 50μF and 10μF with X5R for Ceramic capacitors. If AVIN and PVIN are separated, the 47μF capacitor should be placed as close to possible to the PVIN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device. UTC UR5595 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). The choice for output capacitor depends on the application and the requirements for load transient response of VTT. As a general recommendation the output capacitor should be sized above 100μF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. THERMAL DISSIPATION The UR5595 will generate heat result from internal power dissipation when current flow working. The device might be damaged any beyond maximum junction temperature rating. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax − TAmax From this equation, the maximum power dissipation (PDmax) of the part can be calculated: PDmax = TRmax / θJA The θJA of UR5595 can be calculated (refer to JEDEC standard) and will depend on several package type, materials, ambient air temperature and so on. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 12 QW-R502-062.B UR5595 CMOS IC TYPICAL APPLICATION CIRCUITS Following demonstrate several different application circuits to illustrate some of the options that are possible in configuring the UTC UR5595. The individual circuit performance can be found in the Typical Performance Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AVIN and PVIN. STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most popular form of termination is Class II single parallel termination. It involves one RS series resistor from the chipset to the memory and one RT termination resistor (refer to Figure 1). RS and RT are changeable to meet the current requirement from UR5595, the recommended values both RS and RT are 25Ω. Figure 1. SSTL-Termination Scheme FOR SSTL-2 APPLICATIONS For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and component count and selection. Figure 2. Recommended SSTL-2 Implementation UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 12 QW-R502-062.B UR5595 CMOS IC TYPICAL APPLICATION CIRCUITS(Cont.) Figure 3 illustrate another application that the power rails are split when power dissipation or efficiency are concerned. The output stage (PVIN) can be as lower as 1.8V, and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current from VTT, but the disadvantage of this circuit is the maximum continuous current is reduced. Figure 3. Lower Power Dissipation SSTL-2 Implementation The third optional application is that PVIN connect to 3.3V and AVIN will be always limited to operation on the 3.3V or 5V to always equal or higher than PVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. The power dissipation increasing problem must be careful to prevent the junction temperature to exceed the maximum ranting. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V rail. Figure 4. SSTL-2 Implementation with higher voltage rails UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 12 QW-R502-062.B UR5595 CMOS IC TYPICAL APPLICATION CIRCUITS(Cont.) FOR DDR-II APPLICATIONS As a result of the separate VDDQ pin and an internal resistor divider, UR5595 can be utilized in DDR-II system, figure 5 and 6 show two recommended circuits in DDR-II SDRAM application. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. The power dissipation increasing concern must be careful as well SSTL-II application. The advantage of configuration of figure 6 is that it has the ability to source and sink a higher maximum continuous current. UTC UR5595 VREF VDDQ=1.8V VDDQ AVIN=2.2V ～ 5.5V AVIN VSENSE PVIN=1.8V PVIN VTT CIN + GND + VREF=0.9V CREF VTT=0.9V + COUT Figure 5. Recommended DDR-II Termination Figure 6. DDR-II Termination with higher voltage rails UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 9 of 12 QW-R502-062.B UR5595 CMOS IC TYPICAL CHARACTERISTICS VREF vs. IREF 1.40 1.35 1.30 1.25 1.20 1.15 1.10 -30 -20 -10 0 10 20 30 IREF (μA) VREF vs. VDDQ 3 1.275 2.5 1.270 2 1.265 1.5 1.260 VTT vs. IOUT (0 ,25,85,and 125 ℃) 125 ℃ 0℃ 1 1.255 0.5 1.250 0 0 1 2 3 4 5 6 VDDQ (V) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 1.245 -100 -75 -50 -25 0 25 50 75 100 IOUT (mA) 10 of 12 QW-R502-062.B UR5595 CMOS IC TYPICAL CHARACTERISTICS(Cont.) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 11 of 12 QW-R502-062.B UR5595 CMOS IC UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 12 of 12 QW-R502-062.B