FINAL Am28F020A 2 Megabit (256 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms DISTINCTIVE CHARACTERISTICS ■ High performance — Access times as fast as 70 ns ■ CMOS low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption ■ Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP ■ Latch-up protected to 100 mA from –1 V to VCC +1 V ■ Embedded Erase Electrical Bulk Chip Erase — Five seconds typical chip erase, including pre-programming ■ Embedded Program — 14 µs typical byte program, including time-out — 4 seconds typical chip program ■ Command register architecture for microprocessor/microcontroller compatible write interface ■ On-chip address and data latches ■ Advanced CMOS flash memory technology ■ 100,000 write/erase cycles minimum ■ Write and erase voltage 12.0 V ±5% — Low cost single transistor memory cell ■ Embedded algorithms for completely self-timed write/erase operations GENERAL DESCRIPTION devices within this family that offer Embedded Algorithms use the same command set. This offers designers the flexibility to retain the same device footprint and command set, at any density between 256 Kbits and 2 Mbits. The Am28F020A is a 2 Megabit Flash memory organized as 256 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F020A is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F020A is erased when shipped from the factory. The standard Am28F020A offers access times of as fast as 70 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE #) and output enable (OE#) controls. AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F020A uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. T he A m2 8F0 20A i s c omp ati bl e w i th th e AM D Am28F256A, Am28F512A, and Am28F010A Flash memories. All devices in the Am28Fxxx family follow the JEDEC 32-pin pinout standard. In addition, all Publication# 17502 Rev: D Amendment/+1 Issue Date: January 1998 AMD’s Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F020A uses a 12.0±5% VPP supply input to perform the erase and programming functions. The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F020A electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. Embedded Program Embedded Erase The Am28F020A is byte programmable using the Embedded Program algorithm, which does not require the system to time-out or verify the data programmed. The typical room temperature programming time of this device is four seconds. The entire device is bulk erased using the Embedded Erase algorithm, which automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device. Typical erasure time at room temperature is five seconds, including preprogramming. Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms Embedded Programming Algorithm vs. Flashrite Programming Algorithm Embedded Erase Algorithm vs. Flasherase Erase Algorithm Am28F020A with Embedded Algorithms Am28F020 using AMD Flashrite and Flasherase Algorithms AMD’s Embedded Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. A status bit, Data# Polling, provides the user with the programming operation status. The Flashrite Programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. The user is required to time the programming pulse width in order to issue the program verify command. An integrated stop timer prevents any possibility of overprogramming. AMD’s Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device automatically pre-programs and verifies the entire array. The device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. A status bit, Data# Polling, provides the user with the erase operation status. The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. During write cycles, the command register internally latches addresses and data needed for the programming and erase operations. For system design simplification, the Am28F010A is designed to support 2 Upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times. To invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. The user is required to time the erase pulse width in order to issue the erase verify command. An integrated stop timer prevents any possibility of overerasure. Upon completion of this sequence, the data is read back from the device and compared by the user with erased data. If there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times. either WE# or CE # controlled writes. During a system write cycle, addresses are latched on the falling edge of WE # or CE #, whichever occurs last. Data is latched on the rising edge of WE # or CE #, whichever occurs first. To simplify the following discussion, the WE # pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. Am28F020A PRODUCT SELECTOR GUIDE Am28F020A Family Part Number Speed Options (VCC = 5.0 V ± 10%) -70 -90 -120 -150 -200 Max Access Time (ns) 70 90 120 150 200 CE# (E#) Access (ns) 70 90 120 150 200 OE# (G#) Access (ns) 35 35 50 55 55 BLOCK DIAGRAM DQ0–DQ7 VCC VSS Erase Voltage Switch VPP Input/Output Buffers To Array WE# State Control Command Register Program Voltage Switch CE# OE# Chip Enable Output Enable Logic Data Latch Program/Erase Pulse Timer Low VCC Detector Address Latch Embedded Algorithms Y-Decoder Y-Gating X-Decoder 2,097,152 Bit Cell Matrix A0–A17 17502D-1 Am28F020A 3 CONNECTION DIAGRAMS PDIP 32 VCC A16 2 31 WE# (W#) A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A3 9 A2 A1 4 3 2 1 32 31 30 A7 5 29 A14 A6 6 28 A13 A5 27 A8 A4 7 8 26 A9 A3 9 25 A11 A11 A2 10 24 OE# (G#) 24 OE# (G#) A1 11 23 A10 10 23 A10 A0 12 22 11 22 CE# (E#) DQ0 13 21 CE# (E#) DQ7 A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 Note: Pin 1 is marked for orientation. Am28F020A DQ5 DQ6 DQ4 VSS DQ3 DQ1 DQ2 14 15 16 17 18 19 20 17502D-2 4 VPP VCC WE# (W#) A17 1 A16 VPP A12 A15 PLCC 17502D-3 CONNECTION DIAGRAMS (Continued) A11 A9 A8 A13 A14 A17 WE# VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 A17 WE# VCC VPP A16 A15 A12 A7 A6 A5 A4 32-Pin TSOP—Standard Pinout OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin TSOP—Reverse Pinout 17502D-4 LOGIC SYMBOL 18 8 A0–A17 DQ0–DQ7 CE# (E#) OE# (G#) WE# (W#) 17502D-5 Am28F020A 5 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of the following: AM28F020A -70 J C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am28F020A 2 Megabit (256 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms Valid Combinations Valid Combinations AM28F020A-70 AM28F020A-90 AM28F020A-120 AM28F020A-150 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM28F020A-200 6 Am28F020A PIN DESCRIPTION A0–A17 VPP Address Inputs for memory locations. Internal latches hold addresses during write cycles. Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP ≤ VCC +2 V. CE# (E#) Chip Enable active low input activates the chip’s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode. VCC Power supply for device operation. (5.0 V ± 5% or 10%) DQ0–DQ7 Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles. NC No Connect-corresponding pin is not connected internally to the die. OE# (G#) Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations. VSS Ground. WE# (W#) Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device. Am28F020A 7 BASIC PRINCIPLES The Am28FxxxA family uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input. Read Only Memory Without high V PP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes. Command Register The command register is enabled only when high voltage is applied to the V PP pin. The erase and reprogramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register. The device’s command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device operations. For system design simplification, the device is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. quires the user to only write a program setup command and a program command. The device automatically times the programming pulse width, provides the program verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the programming operation. DATA PROTECTION The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadver tent write cycles resulting from V CC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for V CC < VLKO (see DC characteristics section for voltages). When VCC < V LKO, the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. The device ignores all writes until V CC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent unintentional writes. Write Pulse “Glitch” Protection Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle. OVERVIEW OF ERASE/PROGRAM OPERATIONS Logical Inhibit Embedded Erase Algorithm AMD now makes erasure extremely simple and reliable. The Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device will automatically pre-program and verify the entire array. The device automatically times the erase pulse width, provides the erase verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the erase operation. Writing is inhibited by holding any one of OE# = V IL, CE#=V IH or WE# = V IH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit Power-up of the device with WE# = CE# = VIL and OE# = V IH will not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Embedded Programming Algorithm AMD now makes programming extremely simple and reliable. The Embedded Programming algorithm re- 8 Am28F020A FUNCTIONAL DESCRIPTION Description Of User Modes Table 1. Am28F020A Device Bus Operations (Notes 7 and 8) CE# (E#) OE# (G#) WE# (W#) VPP (Note 1) A0 A9 I/O Read VIL VIL X VPPL A0 A9 DOUT Standby VIH X X VPPL X X HIGH Z Output Disable VIL VIH VIH VPPL X X HIGH Z Auto-select Manufacturer Code (Note 2) VIL VIL VIH VPPL VIL VID (Note 3) CODE (01h) Auto-select Device Code (Note 2) VIL VIL VIH VPPL VIH VID (Note 3) CODE (29h) Read VIL VIL VIH VPPH A0 A9 DOUT (Note 4) Standby (Note 5) VIH X X VPPH X X HIGH Z Output Disable VIL VIH VIH VPPH X X HIGH Z Write VIL VIH VIL VPPH A0 A9 DIN (Note 6) Operation Read-Only Read/Write Legend: X = Don’t care, where Don’t Care is either VIL or VIH levels. VPPL = VPP < VCC + 2 V. See DC Characteristics for voltage levels of VPPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9). Notes: 1. VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. VPPH is the programming voltage specified for the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2. 3. 11.5 < VID < 13.0 V. Minimum V ID rise time and fall time (between 0 and VID voltages) is 500 ns. 4. Read operation with VPP = VPPH may access array data or the Auto select codes. 5. With VPP at high voltage, the standby current is ICC + IPP (standby). 6. Refer to Table 3 for valid DIN during a write operation. 7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all addresses except A9 and A0 must be held at VIL. 8. If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP rise time and fall time specification of 500 ns minimum. Am28F020A 9 READ-ONLY MODE When V PP is less than VCC + 2 V, the command register is inactive. The device can either read array or autoselect data, or be standby mode. Read The device functions as a read only memory when VPP < VCC + 2 V. The device has two control functions. Both must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected. Address access time tACC is equal to the delay from stable addresses to valid output data. The chip enable access time tCE is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least tACC - tOE). Output Disable Output from the device is disabled when OE# is at a logic high level. When disabled, output pins are in a high impedance state. Auto Select Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. Programming In A PROM Programmer Standby Mode The device has two standby modes. The CMOS standby mode (CE# input held at VCC ± 0.5 V), consumes less than 100 µA of current. TTL standby mode (CE# is held at V IH) reduces the current requirements to less than 1 mA. When in the standby mode the outputs are in a high impedance state, independent of the OE# input. If the device is deselected during erasure, programming, or program/erase verification, the device will draw active current until the operation is terminated. To activate this mode, the programming equipment must force VID (11.5 V to 13.0 V) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from V IL to VIH. All other address lines must be held at VIL, and VPP must be less than or equal to VCC + 2.0 V while using this Auto select mode. Byte 0 (A0 = V IL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the device the two bytes are given in the table 2 of the device data sheet. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Table 2. (Am28F020A Auto Select Code Type A0 Code (HEX) Manufacturer Code VIL 01 Device Code VIH 29 10 Am28F020A ERASE, PROGRAM, AND READ MODE When V PP is equal to 12.0 V ± 5%, the command register is active. All functions are available. That is, the device can program, erase, read array or autoselect data, or be standby mode. Write Operations High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device. The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to V IL, while OE# is at VIH. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used. The device requires the OE# pin to be V IH for write operations. This condition eliminates the possibility for bus contention during programming operations. In order to write, OE# must be V IH, and CE# and WE# must be V IL. If any pin is not in the correct state a write command will not be executed. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Command Definitions The contents of the command register default to 00h (Read Mode) in the absence of high voltage applied to the V PP pin. The device operates as a read only memory. High voltage on the V PP pin enables the command register. Device operations are selected by writing specific data codes into the command register. Table 3 in the device data sheet defines these register commands. Read Command Memory contents can be accessed via the read command when V PP is high. To read from the device, write 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered. The command register defaults to 00h (read mode) upon VPP power-up. The 00h (Read Mode) register default helps ensure that inadvertent alteration of the memory contents does not occur during the V PP power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Table 3. Am28F020A Command Definitions First Bus Cycle Second Bus Cycle Operation (Note 1) Address (Note 2) Data (Note 3) Operation (Note 1) Address Note 2) Data (Note 3) Read Memory (Note 4) Write X 00h/FFh Read RA RD Read Auto select Write X 80h or 90h Read 00h/01h 01h/29h Embedded Erase Set-up/ Embedded Erase Write X 30h Write X 30h Embedded Program Set-up/ Embedded Program Write X 10h or 50h Write PA PD Reset (Note 4) Write X 00h/FFh Write X 00h/FFh Command Notes: 1. Bus operations are defined in Table 1. 2. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# pulse. X = Don’t care. 3. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latched on the rising edge of WE#. 4. Please reference Reset Command section. Am28F020A 11 FLASH MEMORY PROGRAM/ERASE OPERATIONS Embedded Erase Algorithm The automatic chip erase does not require the device to be entirely pre-programmed prior to executing the Embedded set-up erase command and Embedded erase command. Upon executing the Embedded erase command the device automatically will program and verify the entire memory for an all zero data pattern. The system is not required to provide any controls or timing during these operations. When the device is automatically verified to contain an all zero pattern, a self-timed chip erase and verify begin. The erase and verify operation are complete when the data on DQ7 is “1" (see Write Operation Status section) atwhich time the device returns to Read mode. The system is not required to provide any control or timing during these operations. When using the Embedded Erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Embedded Erase Set-Up command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. Embedded Erase Setup is performed by writing 30h to the command register. To commence automatic chip erase, the command 30h must be written again to the command register. The automatic erase begins on the rising edge of the WE and terminates when the data on DQ7 is “1" (see Write Operation Status section) at which time the device returns to Read mode. Figure 1 and Table 4 illustrate the Embedded Erase algorithm, a typical command string and bus operation. START Apply VPPH Write Embedded Erase Setup Command Write Embedded Erase Command Data# Poll from Device Erasure Completed 17502D-6 Figure 1. Embedded Erase Algorithm Table 4. Embedded Erase Algorithm Bus Operations Command Comments Wait for VPP Ramp to VPPH (see Note) Standby Embedded Erase Setup Command Data = 30h Embedded Erase Command Data = 30h Write Read Data# Polling to Verify Erasure Standby Compare Output to FFh Read Available for Read Operations Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer to Functional Description. 12 Am28F020A Embedded Programming Algorithm of WE# also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to Read mode. The Embedded Program Setup is a command only operation that stages the device for automatic programming. Embedded Program Setup is performed by writing 10h or 50h to the command register. Once the Embedded Setup Program operation is performed, the next WE# pulse causes a transition to an active programming operation. Addresses are latched on the falling edge of CE# or WE# pulse, whichever happens later. Data is latched on the rising edge of WE# or CE#, whichever happens first. The rising edge Figure 2 and Table 5 illustrate the Embedded Program algorithm, a typical command string, and bus operation. START Apply V PPH Write Embedded Setup Program Command Write Embedded Program Command (A/D) Data# Poll Device No Increment Address Last Address Yes Programming Completed 17502D-7 Figure 2. Embedded Programming Algorithm Table 5. Embedded Programming Algorithm Bus Operations Command Comments Wait for VPP Ramp to VPPH (see Note) Standby Write Embedded Program Setup Command Data = 10h or 50h Write Embedded Program Command Valid Address/Data Read Data# Polling to Verify Completion Read Available for Read Operations Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer to Functional Description. Device is either powered-down, erase inhibit or program inhibit. Am28F020A 13 Write Operation Status Data Polling—DQ7 The device features Data# Polling as a method to indicate to the host system that the Embedded algorithms are either in progress or completed. While the Embedded Programming algorithm is in operation, an attempt to read the device at a valid address will produce the complement of expected Valid data on DQ7. Upon completion of the Embedded Program algorithm an attempt to read the device at a valid address will produce Valid data on DQ7. The Data# Polling feature is valid after the rising edge of the second WE# pulse of the two write pulse sequence. While the Embedded Erase algorithm is in operation, DQ7 will read “0" until the erase operation is completed. Upon completion of the erase operation, the data on DQ7 will read “1.” The Data# Polling feature is valid after the rising edge of the second WE# pulse of the two Write pulse sequence. The Data# Polling feature is only active during Embedded Programming or erase algorithms. See Figures 3 and 4 for the Data# Polling timing specifications and diagrams. Data# Polling is the standard method to check the write operation status, however, an alternative method is available using Toggle Bit. START Read Byte (DQ0–DQ7) Addr = VA DQ7 = Data ? VA = Byte address for programming = XXXXh during chip erase Yes No No DQ5 = 1 ? Yes Read Byte (DQ0–DQ7) Addr = VA DQ7 = Data ? Yes No Fail Pass 17502D-8 Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5 or after DQ5. Figure 3. 14 Data# Polling Algorithm Am28F020A tCH CE# tDF tOE OE# tOEH WE# tCE tOH * DQ7 DQ7# DQ7 = Valid Data High Z tWHWH 3 or 4 DQ0–DQ6 DQ0–DQ6 = Invalid DQ0–DQ7 Valid Data 17502D-9 *DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 4. AC Waveforms for Data# Polling during Embedded Algorithm Operations Am28F020A 15 Toggle Bit—DQ6 The device also features a “Toggle Bit” as a method to indicate to the host system that the Embedded algorithms are either in progress or completed. Successive attempts to read data from the device at a valid address, while the Embedded Program algorithm is in progress, or at any address while the Embedded Erase algorithm is in progress, will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase algorithm is completed, DQ6 will stop toggling to indicate the completion of either Embedded operation. Only on the next read cycle will valid data be obtained. The toggle bit is valid after the rising edge of the first WE# pulse of the two write pulse sequence, unlike Data# Polling which is valid after the rising edge of the second WE# pulse. This feature allows the user to determine if the device is partially through the two write pulse sequence. See Figures 5 and 6 for the Toggle Bit timing specifications and diagrams. START VA = Byte address for programming = XXXXh during chip erase Read Byte (DQ0–DQ7) Addr = VA DQ6 = Toggle ? No Yes No DQ5 = 1 ? Yes Read Byte (DQ0–DQ7) Addr = VA DQ6 = Toggle ? No Yes Fail Pass 17502D-10 Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”. Figure 5. 16 Toggle Bit Algorithm Am28F020A CE# tOEH WE# OE# * Data DQ0–DQ7 DQ6 = DQ6 Stop Toggling DQ6 = DQ0–DQ7 Valid tOE 17502D-11 Note: *DQ6 stops toggling (The device has completed the Embedded operation.) Figure 6. AC Waveforms for Toggle Bit during Embedded Algorithm Operations DQ5 Power-Up/Power-Down Sequence Exceeded Timing Limits The device powers-up in the Read only mode. Power supply sequencing is not required. Note that if VCC ≤ 1.0 Volt, the voltage difference between V PP and VCC should not exceed 10.0 Volts. Also, the device has a rise VPP rise time and fall time specification of 500 ns minimum. DQ5 will indicate if the program or erase time has exceeded the specified limits. This is a failure condition and the device may not be used again (internal pulse count exceeded). Under these conditions DQ5 will produce a “1.” The program or erase cycle was not successfully completed. Data# Polling is the only operating function of the device under this condition. The CE# circuit will partially power down the device under these conditions (to approximately 2 mA). The OE# and WE# pins will control the output disable functions as described in the Command Definitions table in the corresponding device data sheet. Parallel Device Erasure The Embedded Erase algorithm greatly simplifies parallel device erasure. Since the erase process is internal to the device, a single erase command can be given to multiple devices concurrently. By implementing a parallel erase algorithm, total erase time may be minimized. Note that the Flash memories may erase at different rates. If this is the case, when a device is completely erased, use a masking code to prevent further erasure (over-erasure). The other devices will continue to erase until verified. The masking code applied could be the read command (00h). Reset Command The Reset command initializes the Flash memory device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset must be written two consecutive times after the Setup Program command (10h or 50h). This will reset the device to the Read mode. Following any other Flash command, write the Reset command once to the device. This will safely abort any previous operation and initialize the device to the Read mode. The Setup Program command (10h or 50h) is the only command that requires a two-sequence reset cycle. The first Reset command is interpreted as program data. However, FFh data is considered as null data during programming operations (memory cells are only programmed from a logical “1" to “0"). The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. Am28F020A 17 This detailed information is for your reference. It may prove easier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the Setup Program state or not. In-System Programming Considerations Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the circuit board. Auto Select Command AMD’s Flash memories are designed for use in applications where the local CPU alters memory contents. In order to correctly program any Flash memories 18 in-system, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a generally desired system design practice. The device contains an Auto Select operation to supplement traditional PROM programming methodologies. The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h (AMD). A read cycle from address 0001h returns the device code (see the Auto Select Code table of the corresponding device data sheet). To terminate the operation, it is necessary to write another valid command, such as Reset (00h or FFh), into the register. Am28F020A ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . –65°C to +125°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C Voltage with Respect to Ground All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V A9, VPP (Note 2) . . . . . . . . . . . . . . . –2.0 V to +14.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. Industrial (I) Devices Extended (E) Devices Ambient Temperature (TA). . . . . . . . .–55°C to +125°C VCC Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V VPP Voltages Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on pins A9 and VPP is –0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 and VPP is +13.0 V, which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Am28F020A 19 MAXIMUM OVERSHOOT Maximum Negative Input Overshoot 20 ns 20 ns +0.8 V –0.5 V –2.0 V 20 ns 17502D-12 Maximum Positive Input Overshoot 20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns 17502D-13 Maximum VPP Overshoot 20 ns 14.0 V 13.5 V VCC + 0.5 V 20 ns 20 ns 17502D-14 20 Am28F020A DC CHARACTERISTICS over operating range unless otherwise specified TTL/NMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current VCC = VCC Max CE# = VIH 0.2 1.0 mA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 (Note 4) VCC Programming Current CE# = VIL Programming in Progress 20 30 mA ICC3 (Note 4) VCC Erase Current CE# = VIL Erasure in Progress 20 30 mA IPPS VPP Standby Current VPP = VPPL ±1.0 µA IPP1 VPP Read Current VPP = VPPH 70 200 ±1.0 VPP = VPPL µA IPP2 (Note 4) VPP Programming Current VPP = VPPH Programming in Progress 10 30 mA IPP3 (Note 4) VPP Erase Current 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage IOL = 5.8 mA VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA VCC = VCC Min 2.4 VID A9 Auto Select Voltage A9 = VID 11.5 IID A9 Auto Select Current A9 = VID Max VCC = VCC Max VPPL VPP during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL VPPH VLKO VPP = VPPH Erasure in Progress V 13.0 V 50 µA 0.0 VCC +2.0 V VPP during Read/Write Operations 11.4 12.6 V Low VCC Lock-out Voltage 3.2 5 3.7 V Notes: 1. Caution: the Am28F020A must not be removed from (or inserted into) a socket when V CC or VPP is applied. If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F020A has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP . 4. Not 100% tested. Am28F020A 21 DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current VCC = VCC Max CE# = VCC + 0.5 V 15 100 mA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 (Note 4) VCC Programming Current CE# = VIL Programming in Progress 20 30 mA ICC3 (Note 4) VCC Erase Current CE# = VIL Erasure in Progress 20 30 mA IPPS VPP Standby Current VPP = VPPL ±1.0 µA IPP1 VPP Read Current VPP = VPPH 70 200 µA IPP2 (Note 4) VPP Programming Current VPP = VPPH Programming in Progress 10 30 mA IPP3 (Note 4) VPP Erase Current 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 5.8 mA VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC IOH = –100 µA, V CC = VCC Min VCC –0.4 11.5 VOH2 VPP = VPPH Erasure in Progress VID A9 Auto Select Voltage A9 = VID IID A9 Auto Select Current A9 = VID Max VCC = VCC Max VPPL VPP during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL VPPH VLKO V 13.0 V 50 µA 0.0 VCC +2.0 V VPP during Read/Write Operations 11.4 12.6 V Low VCC Lock-out Voltage 3.2 5 3.7 V Notes: 1. Caution: the Am28F020A must not be removed from (or inserted into) a socket when V CC or VPP is applied. If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F020A has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP . 4. Not 100% tested. 22 Am28F020A 30 25 20 ICC Active in mA 15 -55 °C 0° C 25° C 70° C 125°C 10 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 Frequency in MHz 17502D-15 Figure 7. Am28F020A - Average ICC Active vs. Frequency VCC = 5.5 V, Addressing Pattern = Minmax Data Pattern = Checkerboard TEST CONDITIONS Table 6. 5.0 V Test Condition 2.7 kΩ Device Under Test Test Specifications Output Load Output Load Capacitance, CL (including jig capacitance) CL -70 Input Pulse Levels Note: Diodes are IN3064 or equivalent Unit 1 TTL gate 30 100 ≤10 Input Rise and Fall Times 6.2 kΩ All others pF ns 0.0–3.0 0.45–2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V 17502D-16 Figure 8. Test Setup Am28F020A 23 SWITCHING TEST WAVEFORMS 3V 2.4 V 2.0 V 2.0 V Test Points 0.8 V Test Points 1.5 V 1.5 V 0.8 V 0V 0.45 V Input Input Output AC Testing (all speed options except -70): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. Output AC Testing for -70 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. 17502D-17 SWITCHING CHARACTERISTICS over operating range, unless otherwise specified AC Characteristics—Read-Only Operations Parameter Symbols Am28F020A Speed Options JEDEC Standard Parameter Description -70 -90 -120 -150 -200 Unit tAVAV tRC Read Cycle Time (Note 3) Min 70 90 120 150 200 ns tELQV tCE Chip Enable Access Time Max 70 90 120 150 200 ns tAVQV tACC Address Access Time Max 70 90 120 150 200 ns tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns tELQX tLZ Chip Enable to Output in Low Z (2) Min 0 0 0 0 0 ns tEHQZ tDF Chip Disable to Output in High Z (1) Max 20 20 30 35 35 ns tGLQX tOLZ Output Enable to Output in Low Z (2) Min 0 0 0 0 0 ns tGHQZ tDF Output Disable to Output in High Z (2) Max 20 20 30 35 35 ns tAXQX tOH Output Hold Time From First Address, CE#, or OE# change (2) Min 0 0 0 0 0 ns VCC Set-up Time to Valid Read (2) Min 50 50 50 50 50 ns tVCS Notes: 1. Guaranteed by design; not tested. 2. Not 100% tested 24 Am28F020A AC Characteristics—Write (Erase/Program) Operations Parameter Symbols Am28F020A Speed Options JEDEC Standard Description -70 -90 -120 -150 -200 Unit tAVAV tWC Write Cycle Time (4) Min 70 90 120 150 200 ns tAVWL tAS Address Setup Time Min 0 0 0 0 0 ns tWLAX tAH Address Hold Time Min 45 45 50 60 75 ns tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns tOEH Output Enable Hold Time for Embedded Algorithm only Min 10 10 10 10 10 ns tGHWL Read Recovery Time Before Write Min 0 0 0 0 0 ns tELWLE tCSE CE# Embedded Algorithm Setup Time Min 20 20 20 20 20 ns tWHEH tCH CE# Hold Time Min 0 0 0 0 0 ns tWLWH tWP Write Pulse Width Min 45 45 50 60 60 ns tWHWL tWPH Write Pulse Width High Min 20 20 20 20 20 ns tWHWH3 Embedded Program Operation (2) Min 14 14 14 14 14 µs tWHWH4 Embedded Erase Operation (3) Typ 5 5 5 5 5 sec tVPEL VPP Setup Time to Chip Enable Low (4) Min 100 100 100 100 100 ns tVCS VCC Setup Time (4) Min 50 50 50 50 50 µs tVPPR VPP Rise Time (4) 90% VPPH Min 500 500 500 500 500 ns tVPPF VPP Fall Time (4) 90% VPPL Min 500 500 500 500 500 ns tLKO VCC < VLKO to Reset (4) Min 100 100 100 100 100 ns Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the minimum time for one pass through the programming algorithm. 3. Embedded Erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Am28F020A 25 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) SWITCHING WAVEFORMS Power-up, Standby Device and Address Selection Addresses Outputs Enabled Data Valid Standby, Power-down Addresses Stable tAVAV (tRC) CE# (E#) tEHQZ (tDF) OE# (G#) tWHGL tGHQZ (tDF) WE# (W#) tGLQV (tOE) tELQV (tCE ) tGLQX (tOLZ ) tVCS Data (DQ) tAXQX (tOH) tELQX (tLZ) High Z tVCS Output Valid High Z tAVQV (tACC) 5.0 V VCC 0V 17502D-18 Figure 9. 26 AC Waveforms for Read Operations Am28F020A SWITCHING WAVEFORMS Embedded Erase Setup Embedded Erase tWC tAS Erase Data# Polling Read Standby Addresses CE# tRC tAH tGHWL OE# tWHWH3 OR 4 tWP WE# tWPH tCSE Data 30h tVCS tDF tDH tOE 30h DQ7# DQ7# tDS tOH VCC tCE VPP tVPEL 17502D-19 Note: DQ7# is the complement of the data written to the device. Figure 10. AC Waveforms for Embedded Erase Operation Am28F020A 27 SWITCHING WAVEFORMS Embedded Program Setup Embedded Program Addresses Data# Polling PA tWC Read PA tRC tAS CE# tAH tGHWL OE# tWHWH3 OR 4 tWP WE# tCSE tDH Data tWPH tDF tOE DIN 50h DQ7# DQ7# DOUT tVCS tOH tDS VCC tCE VPP tVPEL 17502D-20 Notes: 1. DIN is data input to the device. 2. DQ7# is the complement of the data written to the device. 3. DOUT is the data written to the device. Figure 11. 28 AC Waveforms for Embedded Programming Operation Am28F020A AC CHARACTERISTICS—WRITE (ERASE/PROGRAM) OPERATIONS Alternate CE# Controlled Writes Parameter Symbols Am28F020A Speed Options JEDEC Standard Description -70 -90 -120 -150 -200 Unit tAVAV tWC Write Cycle Time (4) Min 70 90 120 150 200 ns tAVEL tAS Address Setup Time Min 0 0 0 0 0 ns tELAX tAH Address Hold Time Min 45 45 50 60 75 ns tDVEH tDS Data Setup Time Min 45 45 50 50 50 ns tEHDX tDH Data Hold Time Min 10 10 10 10 10 ns tOEH Output Enable Hold Time for Embedded Algorithm only Min 10 10 10 10 10 ns tGHEL Read Recovery Time Before Write Min 0 0 0 0 0 ns tWLEL tWS WE# Setup Time by CE# Min 0 0 0 0 0 ns tEHWK tWH WE# Hold Time Min 0 0 0 0 0 ns tELEH tCP Write Pulse Width Min 65 65 70 80 80 ns tEHEL tCPH Write Pulse Width High Min 20 20 20 20 20 ns tEHEH3 Embedded Program Operation (2) Min 14 14 14 14 14 µs tEHEH4 Embedded Erase Operation (3) Typ 5 5 5 5 5 sec tVPEL VPP Setup Time to Chip Enable Low (4) Min 100 100 100 100 100 ns tVCS VCC Setup Time (4) Min 50 50 50 50 50 µs tVPPR VPP Rise Time (4) 90% VPPH Min 500 500 500 500 500 ns tVPPF VPP Fall Time (4) 90% VPPL Min 500 500 500 500 500 ns tLKO VCC < VLKO to Reset (4) Min 100 100 100 100 100 ns Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the minimum time for one pass through the programming algorithm. 3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Am28F020A 29 SWITCHING WAVEFORMS Embedded Program Setup Embedded Program Data# Polling PA PA Addresses tWC tAS tAH WE# tGHEL OE# tCPH tEHEH3 OR 4 tCP CE# tDH tWS Data 50h DIN DQ7# DQ7# DOUT tDS VCC VPP tVPEL 17502D-21 Notes: 1. DIN is data input to the device. 2. DQ7# is the complement of the data written to the device. 3. DOUT is the data written to the device. Figure 12. AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes 30 Am28F020A ERASE AND PROGRAMMING PERFORMANCE Limits Typ (Note 1) Max (Note 2) Unit Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure Chip Programming Time 4 25 sec Excludes system-level overhead Parameter Min Write/Erase Cycles 100,000 Byte Programming Time Comments Cycles 14 µs 96 (Note 3) ms Notes: 1. 25°C, 12 V VPP . 2. Maximum time specified is lower than worst case. Worst case is derived from the Embedded Algorithm internal counter which allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is significantly less than the actual device limit. 3. Typical worst case = 84 µs. DQ5 = “1” only after a byte takes longer than 96 ms to program. LATCHUP CHARACTERISTICS Parameter Min Max Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V Input Voltage with respect to VSS on all pins I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA Current Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Typ Max Unit Input Capacitance VIN = 0 8 10 pF COUT Output Capacitance VOUT = 0 8 12 pF CIN2 VPP Input Capacitance VPP = 0 8 12 pF CIN Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time Am28F020A 31 PHYSICAL DIMENSIONS PD032—32-Pin Plastic DIP (measured in inches) 1.640 1.670 .600 .625 17 32 .009 .015 .530 .580 Pin 1 I.D. .630 .700 16 .045 .065 0° 10° .005 MIN .140 .225 16-038-S_AG PD 032 EC75 5-28-97 lv SEATING PLANE .090 .110 .120 .160 .016 .022 .015 .060 PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches) .447 .453 .485 .495 .009 .015 .585 .595 .042 .056 .125 .140 Pin 1 I.D. .080 .095 .547 .553 SEATING PLANE .400 REF. .490 .530 .013 .021 .050 REF. .026 .032 TOP VIEW 32 SIDE VIEW Am28F020A 16-038FPO-5 PL 032 DA79 6-28-94 ae PHYSICAL DIMENSIONS TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 0.50 0.70 Am28F020A 33 PHYSICAL DIMENSIONS TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 0.50 0.70 34 Am28F020A 16-038-TSOP-2 TSR032 DA95 3-25-97 lv DATA SHEET REVISION SUMMARY FOR AM28F020A Revision C+1 AC Characteristics: Read Only Operations Characteristics: Added the -70 column and test conditions. Distinctive Characteristics: Deleted -95 and -250 speed options. High Performance: The fastest speed option available is now 70 ns. AC Characteristics: General Description: Paragraph 2: Changed fastest speed option to 70 ns. Write/Erase/Program Operations, Alternate CE # Controlled Writes: Added the -70 column. Deleted -95 and -250 speed options. Switching Test Waveforms: Product Selector Guide: In the 3.0 V waveform caption, changed -95 to -70. Added -70, deleted -95 and -250 speed options. Revision D Ordering Information, Standard Products: Matched formatting to other current data sheets. The -70 speed option is now listed in the example. Valid Combinations: Added -70, deleted -95 and -250 combinations. Erase, Program, and Read Mode: Corrected the subheading to read “VPP = 12.0 V ± 5%”. Operating Ranges: Revision D+1 Programming In A PROM Programmer: Deleted the paragraph “(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory device in-system).” VCC Supply Voltages: Added -70, deleted -95 and -250 speed options. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. ExpressFlash is a trademark of Advanced Micro Devices, Inc. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am28F020A 35