AMD AM29F800B

PRELIMINARY
Am29F800T/Am29F800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS
5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ Compatible with JEDEC standards
■ Embedded Program Algorithm
— Automatically programs and verifies data at
specified address
— Pinout and software compatible with
single-power-supply flash
■ Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
— Superior inadvertent write protection
■ Ready/Busy output (RY/BY)
■ Package options
— 44-pin SO
— 48-pin TSOP
■ Minimum 100,000 write/erase cycles guaranteed
■ High performance
— 70 ns maximum access time
■ Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
■ Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
■ Embedded Erase Algorithm
— Automatically pre-programs and erases the chip
or any sector
— Hardware method for detection of program or
erase cycle completion
■ Erase Suspend/Resume
— Supports reading data from or programming
data to a sector not being erased
■ Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
■ Enhanced power management for standby
mode
— 1 µA typical standby current
■ Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
■ Hardware RESET pin
— Resets internal state machine to the read mode
GENERAL DESCRIPTION
The Am29F800 is an 8 Mbit, 5.0 Volt-only Flash memory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase capability, the 8 Mbits
of data are divided into 19 sectors as follows: one 16
Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte.
Eight bits of data appear on DQ0–DQ7 in byte mode; in
word mode 16 bits appear on DQ0–DQ15. The
Am29F800 is offered in 44-pin SO and 48-pin TSOP
packages. This device is designed to be programmed
in-system with the standard system 5.0 Volt VCC supply. A VPP of 12.0 volts is not required for program or
erase operations. The device can also be programmed
in standard EPROM programmers.
8/18/97
The standard Am29F800 offers access times of 70 ns, 90
ns, 120 ns, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus
contention, the device has separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The Am29F800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine which
controls the erase and program circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
Publication# 20375 Rev: C Amendment/+1
Issue Date: August 1997
P R E L I M I N A R Y
of the device is similar to reading from 12.0 Volt Flash
or EPROM devices.
The Am29F800 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper
cell margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F800 is erased when
shipped from the factory.
The Am29F800 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of nineteen sectors of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from or program data to a sector that
was not being erased. Thus, true background erase
can be achieved.
2
The device features single 5.0 Volt power supply operation for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29F800 also has a hardware RESET pin.
When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be automatically reset to the read mode and will have erroneous data stored in the address locations being
operated on. These locations will need re-writing after
the Reset. Resetting the device will enable the system’s microprocessor to read the boot-up firmware
from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The Am29F800 memory electrically erases all
bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part No:
Am29F800
Ordering Part No: VCC = 5.0 V ± 10%
-70
-90
-120
-150
Max Access Time (ns)
70
90
120
150
CE (E) Access (ns)
70
90
120
150
OE (G) Access (ns)
30
35
50
55
BLOCK DIAGRAM
DQ0–DQ15
VCC
VSS
WE
BYTE
RESET
RY/BY
Buffer
RY/BY
Input/Output
Buffers
Erase Voltage
Generator
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
VCC Detector
A0–A18
Timer
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A–1
20375C-1
8/18/97
Am29F800T/Am29F800B
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
RY/BY
1
44
RESET
A18
2
43
WE
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE
12
33
BYTE
VSS
13
32
VSS
OE
14
31
DQ15/A-1
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
20375C-2
4
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard TSOP
20375C-3
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
Reverse TSOP
20375C-4
8/18/97
Am29F800T/Am29F800B
5
P R E L I M I N A R Y
PIN CONFIGURATION
A0–A18
= 19 Addresses
BYTE
= Selects 8-bit or 16-bit mode
CE
LOGIC SYMBOL
A-1
19
= Chip Enable
DQ15/A-1
DQ0–DQ15
= DQ15 Data Input/Output,
A-1 Address Mux
CE (E)
NC
= Pin Not Connected Internally
OE (G)
OE
= Output Enable
WE (W)
RESET
= Hardware Reset Pin, Active Low
RESET
RY/BY
= Ready/Busy Output
BYTE
VCC
= +5.0 Volt Single-Power Supply
(±10% for -70, -90, -120, -150)
VSS
= Device Ground
WE
= Write Enable
6
16 or 8
A0–A18
DQ0–DQ14 = 15 Data Inputs/Outputs
Am29F800T/Am29F800B
RY/BY
20375C-5
8/18/97
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM29F800
T
-70
E
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F800
8 Megabit (1M x 8-Bit/512K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations
AM29F800T-70,
AM29F800B-70
EC, EI, FC, FI, SC, SI
AM29F800T-90,
AM29F800B-90
AM29F800T-120,
AM29F800B-120
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
EC, EI, EE, EEB,
FC, FI, FE, FEB,
SC, SI, SE, SEB
AM29F800T-150,
AM29F800B-150
8/18/97
Am29F800T/Am29F800B
7
P R E L I M I N A R Y
Table 1.
Am29F800 User Bus Operations (BYTE = VIH)
Operation
CE
OE
WE
A0
A1
A6
A9
DQ0–DQ15
RESET
Autoselect, AMD Manuf. Code (Note 1)
L
L
H
L
L
L
VID
Code
H
Autoselect Device Code (Note 1)
L
L
H
H
L
L
VID
Code
H
Read
L
L
X
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
HIGH Z
H
Output Disable
L
H
H
X
X
X
X
HIGH Z
H
Write
L
H
L
A0
A1
A6
A9
DIN
H
Verify Sector Protect (Note 2)
L
L
H
L
H
L
VID
Code
H
Temporary Sector Unprotect
X
X
X
X
X
X
X
X
VID
Hardware Reset
X
X
X
X
X
X
X
HIGH Z
L
Table 2.
Operation
Am29F800 User Bus Operations (BYTE = VIL)
CE
OE
WE
A0
A1
A6
A9
Autoselect, AMD Manuf. Code
(Note 1)
L
L
H
L
L
L
VID
Code
HIGH Z
H
Autoselect Device Code (Note 1)
L
L
H
H
L
L
VID
Code
HIGH Z
H
Read
L
L
X
A0
A1
A6
A9
DOUT
HIGH Z
H
Standby
H
X
X
X
X
X
X
HIGH Z
HIGH Z
H
Output Disable
L
H
H
X
X
X
X
HIGH Z
HIGH Z
H
Write
L
H
L
A0
A1
A6
A9
DIN
HIGH Z
H
L
L
H
L
H
L
VID
Code
HIGH Z
H
X
X
X
X
X
X
X
X
HIGH Z
VID
X
X
X
X
X
X
X
HIGH Z
HIGH Z
L
Verify
Sector Protect (Note 2)
Temporary
Sector Unprotect
Hardware Reset
DQ0–DQ7 DQ8–DQ15 RESET
Legend:
L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7.
2. Refer to the section on Sector Protection.
Read Mode
The Am29F800 has two control functions which must
be satisfied in order to obtain data at the outputs. CE is
the power control and should be used for device selection. OE is the output control and should be used to
gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses
and stable CE to valid data at the output pins.
The output enable access time is the delay from the
falling edge of OE to valid data at the output
8
pins (assuming the addresses have been stable for at
least tACC–tOE time).
Standby Mode
There are two ways to implement the standby mode on
the Am29F800 device, both using the CE pin.
A CMOS standby mode is achieved with the CE input
held at VCC ± 0.3V. Under this condition the current is
typically reduced to less than 5 µA. A TTL standby
mode is achieved with the CE pin held at VIH. Under
this condition the current is typically reduced to 1 mA.
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
In the standby mode the outputs are in the high impedance state, independent of the OE input.
The manufacturer and device codes may also be read
via the command register, for instances when the
Am29F800 is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in Table 4 (see Autoselect Command Sequence).
Output Disable
With the OE input at a logic high level (VIH), output from
the device is disabled. This will cause the output pins
to be in a high impedance state.
Byte 0 (A0 = VIL) represents the manufacturer’s code
(AMD=01H) and byte 1 (A0 = VIH) the device identifier
code (Am29F800T = D6H and Am29F800B = 58H for
x8 mode; Am29F800T = 22D6H and Am29F800B =
2258H for x16 mode). These two bytes/words are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as
the parity bit. In order to read the proper device codes
when executing the Autoselect, A1 must be VIL (see
Tables 3 and 4).
Autoselect
The autoselect mode allows the reading of a binary
code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically
matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment
must force VID (11.5 V to 12.5 V) on address pin A9.
Two identifier bytes may then be sequenced from the
device outputs by toggling address A0 from VIL to VIH.
All addresses are don’t cares except A0, A1, and A6
(see Table 3).
Table 3.
The autoselect mode also facilitates the determination
of sector protection in the system. By performing a read
operation at the address location XX02H with the
higher order address bits A12–A18 set to the desired
sector address, the device will return 01H for a protected sector and 00H for a non-protected sector.
Am29F800 Sector Protection Verify Autoselect Codes
Type
Manufacturer Code—AMD
A12–A18
A6
A1
A0
Code (HEX)
X
VIL
VIL
VIL
01H
X
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIH
VIL
D6H
Byte
Am29F800T
Word
22D6H
Am29F800 Device
58H
Byte
Am29F800B
X
Word
Sector
Address
Sector Protection
2258H
01H*
*Outputs 01H at protected sector addresses
Table 4.
Type
Manufacturer Code—AMD
Am29F800T(B)
Device
Code
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
01H
0
0
0
0
0
0
0
D6H
(W) 22D6H
Am29F800
Am29F800B(B)
Sector Protection
Expanded Autoselect Code Table
58H
(W) 2258H
01H
DQ DQ DQ DQ DQ DQ DQ DQ DQ
8
7
6
5
4
3
2
1
0
0
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
0
1
0
0
0
1
0
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(B) – Byte mode
(W) – Word mode
8/18/97
Am29F800T/Am29F800B
9
P R E L I M I N A R Y
Table 5.
Sector Address Tables (Am29F800T)
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
X
X
X
SA1
0
0
0
1
X
X
X
SA2
0
0
1
0
X
X
X
SA3
0
0
1
1
X
X
X
SA4
0
1
0
0
X
X
X
SA5
0
1
0
1
X
X
X
SA6
0
1
1
0
X
X
X
SA7
0
1
1
1
X
X
X
SA8
1
0
0
0
X
X
X
SA9
1
0
0
1
X
X
X
SA10
1
0
1
0
X
X
X
SA11
1
0
1
1
X
X
X
SA12
1
1
0
0
X
X
X
SA13
1
1
0
1
X
X
X
SA14
1
1
1
0
X
X
X
SA15
1
1
1
1
0
X
X
SA16
1
1
1
1
1
0
0
SA17
1
1
1
1
1
0
1
SA18
1
1
1
1
1
1
X
Sector
Size
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
32 Kbytes
16 Kwords
8 Kbytes
4 Kwords
8 Kbytes
4 Kwords
16 Kbytes
8 Kwords
(x16)
Address Range
(x8)
Address Range
00000h–07FFFh
00000h–0FFFFh
08000h–0FFFFh
10000h–1FFFFh
10000h–17FFFh
20000h–2FFFFh
18000h–1FFFFh
30000h–3FFFFh
20000h–27FFFh
40000h–4FFFFh
28000h–2FFFFh
50000h–5FFFFh
30000h–37FFFh
60000h–6FFFFh
38000h–3FFFFh
70000h–7FFFFh
40000h–47FFFh
80000h–8FFFFh
48000h–4FFFFh
90000h–9FFFFh
50000h–57FFFh
A0000h–AFFFFh
58000h–5FFFFh
B0000h–BFFFFh
60000h–67FFFh
C0000h–CFFFFh
68000h–6FFFFh
D0000h–DFFFFh
70000h–77FFFh
E0000h–EFFFFh
78000h–7BFFFh
F0000h–F7FFFh
7C000h–7CFFFh
F8000h–F9FFFh
7D000h–7DFFFh
FA000h–FBFFFh
7E000h–7FFFFh
FC000h–FFFFFh
Note: The address range is A18:A–1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).
10
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Table 6.
Sector Address Tables (Am29F800B)
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
0
X
SA1
0
0
0
0
0
1
0
SA2
0
0
0
0
0
1
1
SA3
0
0
0
0
1
X
X
SA4
0
0
0
1
X
X
X
SA5
0
0
1
0
X
X
X
SA6
0
0
1
1
X
X
X
SA7
0
1
0
0
X
X
X
SA8
0
1
0
1
X
X
X
SA9
0
1
1
0
X
X
X
SA10
0
1
1
1
X
X
X
SA11
1
0
0
0
X
X
X
SA12
1
0
0
1
X
X
X
SA13
1
0
1
0
X
X
X
SA14
1
0
1
1
X
X
X
SA15
1
1
0
0
X
X
X
SA16
1
1
0
1
X
X
X
SA17
1
1
1
0
X
X
X
SA18
1
1
1
1
X
X
X
Sector
Size
16 Kbytes
8 Kwords
8 Kbytes
4 Kwords
8 Kbytes
4 Kwords
32 Kbytes
16 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
(x16)
Address Range
(x8)
Address Range
00000h–01FFFh
00000h–03FFFh
02000h–02FFFh
04000h–05FFFh
03000h–03FFFh
06000h–07FFFh
04000h–07FFFh
08000h–0FFFFh
08000h–0FFFFh
10000h–1FFFFh
10000h–17FFFh
20000h–2FFFFh
18000h–1FFFFh
30000h–3FFFFh
20000h–27FFFh
40000h–4FFFFh
28000h–2FFFFh
50000h–5FFFFh
30000h–37FFFh
60000h–6FFFFh
38000h–3FFFFh
70000h–7FFFFh
40000h–47FFFh
80000h–8FFFFh
48000h–4FFFFh
90000h–9FFFFh
50000h–57FFFh
A0000h–AFFFFh
58000h–5FFFFh
B0000h–BFFFFh
60000h–67FFFh
C0000h–CFFFFh
68000h–6FFFFh
D0000h–DFFFFh
70000h–77FFFh
E0000h–EFFFFh
78000h–7FFFFh
F0000h–FFFFFh
Note: The address range is A18:A–1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).
8/18/97
Am29F800T/Am29F800B
11
P R E L I M I N A R Y
Write
Device erasure and programming are accomplished
via the command register. The contents of the register
serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used
to store the commands, along with the address and
data information needed to execute the command. The
command register is written to by bringing WE to VIL,
while CE is at V IL and OE is at V IH. Addresses are
latched on the falling edge of WE or CE, whichever
happens later; while data is latched on the rising edge
of WE or CE, whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The Am29F800 features hardware sector protection.
This feature will disable both program and erase operations in any combination of nineteen sectors of memory. The sector protect feature is enabled using
programming equipment at the user’s site. The device
is shipped with all sectors unprotected. Alternatively,
AMD may program and protect sectors in the factory
prior to shipping the device (AMD’s ExpressFlash™
Service).
12
It is possible to determine if a sector is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where
the higher order address bits A12–A18 is the desired
sector address, will produce a logical “1” at DQ0 for a
protected sector. See Table 3 for Autoselect codes.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors of the Am29F800 device in
order to change data in-system. The Sector Unprotect
mode is activated by setting the RESET pin to high voltage (12V). During this mode, formerly protected sectors can be programmed or erased by selecting the
sector addresses. Once the 12 V is taken away from
the RESET pin, all the previously protected sectors will
be protected again. Refer to Figures 17 and 18.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the
device to the read mode. Table 7 defines the valid
register command sequences. Note that the Erase
Suspend (B0H) and Erase Resume (30H) commands
are valid only while the Sector Erase operation is in
progress. Moreover, both Reset/Read commands are
functionally equivalent, resetting the device to the
read mode.
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Table 7.
Command
Sequence
Read/Reset
(Note 2)
Bus
Write
Cycles
Req’d
Addr
1
XXX
3
Autoselect
Word
Device ID
(Top Boot Block) Byte
3
Data
RA
RD
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
555
XXAA
2AA
XX55
555
XX90
XX00
XX01
AAA
AA
555
55
AAA
90
00
01
555
XXAA
2AA
XX55
555
XX90
XX01
22D6
AAA
AA
555
55
AAA
90
02
D6
555
XXAA
2AA
XX55
555
XX90
XX01
2258
Byte
AAA
AA
555
55
AAA
90
02
58
555
XXAA
2AA
XX55
555
XX90
(SA)
X02
XX00
Word
(SA)
X04
00
PA
PD
Word
3
XX01
3
Byte
AAA
Word
Byte Program
AA
555
55
AAA
90
Word
Chip Erase
01
555
XXAA
2AA
XX55
555
XXA0
AAA
AA
555
55
AAA
A0
555
XXAA
2AA
XX55
555
XX80
555
XXAA
2AA
XX55
555
XX10
AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
555
XXAA
2AA
XX55
555
XX80
555
XXAA
2AA
XX55
4
Byte
6
Byte
Word
Sector Erase
6
AAA
Word
AA
555
55
AAA
80
AAA
AA
555
55
30
XXB0
1
XXX
Byte
B0
Word
Erase Resume
XX30
SA
Byte
Erase Suspend
(Note 4)
Addr
Fourth Bus
Read/Write
Cycle
F0
Word
Autoselect
Manufacturer ID Byte
Autoselect
Sector Protect
Verify (Note 3)
Data
Third Bus Write
Cycle
XXF0
Byte
Autoselect
Device ID
(Bottom Boot
Block)
Second Bus
Read/Write
Cycle
First Bus
Write Cycle
Word
Reset/Read
Am29F800 Command Definitions
XX30
1
XXX
Byte
30
Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA = Address of the sector to be erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. All values are in hexadecimal.
2. See Tables 1 and 2 for description of bus operations.
3. The data is 00H for an unprotected sector group and 01H for a protected sector group. The complete bus address is
composed of the sector address (A18–A12), A1 = 1, and A0 = 0.
4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode.
5. Address bits A18–A11 are don’t care for unlock and command cycles.
8/18/97
Am29F800T/Am29F800B
13
P R E L I M I N A R Y
Read/Reset Command
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/
reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read
cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content
occurs during the power transition. Refer to the AC
Read Characteristics and Waveforms for the specific
timing parameters.
Autoselect Command
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must be accessible while the device resides in the target system.
PROM programmers typically access the signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice.
The device contains an autoselect command operation
to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F800T = D6H and Am29F800B = 58H for
x8 mode; Am29F800T = 22D6H and Am29F800B =
2258H for x16 mode) (see Tables 3 and 4).
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A18, A17, A16, A15, A14, A13, and A12) while (A6,
A1, A0) = (0, 1, 0) will produce a logical “1” at device
output DQ0 for a protected sector.
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
Byte/Word Programming
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These
are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm,
14
the system is not required to provide further controls or
timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are
no longer latched (see Table 8, Hardware Sequence
Flags). Therefore, the device requires that a valid address to the device be supplied by the system at this
particular instance of time for Data Polling operations.
Data Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success, according
to the data polling algorithm, but a read from reset/read
mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 1 illustrates the Embedded Programming Algorithm using typical command strings and
bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table “Erase and Programming Performance”). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to
read the mode.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Sector Erase
Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the sector erase command. The sector address (any address location within the desired
sector) is latched on the falling edge of WE, while the
command (30H) is latched on the rising edge of WE.
After a time-out of 80 µs from the rising edge of the
last sector erase command, the sector erase operation
will begin.
Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
sequentially erased. The time between writes must be
less than 80 µs otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A
time-out of 80 µs from the rising edge of the last WE will
initiate the execution of the Sector Erase command(s).
If another falling edge of the WE occurs within the 80
µs time-out window the timer is reset. (Monitor DQ3 to
determine if the sector erase timer window is still open.
See DQ3, Sector Erase Timer.) Any command other
than Sector Erase or Erase Suspend during this period
will reset the device to the read mode, ignoring the previous command string. In that case, restart the erase
on those sectors and allow them to complete.
Loading the sector erase buffer may be done in
any sequence and with any number of sectors (0 to18).
Refer to DQ3, Sector Erase Timer, in the Write Operation Status section.
Sector erase does not require the user to program the
device prior to erase. The device automatically programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations.
The automatic sector erase begins after the 80 µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on DQ7, Data Polling, is “1” (see Write Operation
Status section) at which time the device returns to the
read mode. Data Polling must be performed at an address within any of the sectors being erased.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
reads or programs to a sector not being erased. This
command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector
erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded
Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Any other command written during the Erase Suspend
mode will be ignored except the Erase
Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are
“don’t-cares” when writing the Erase Suspend or Erase
Resume command.
When the Erase Suspend command is written during a
Sector Erase operation, the chip will take a maximum
of 20 µs to suspend the operation and go into erase
suspended mode, at which time the user can read or
program from a sector that is not being erased. Reading data in this mode is the same as reading from the
standard read mode, except that the data must be read
from sectors that have not been erase suspended.
Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode
will cause DQ2 to toggle. After entering the erase-suspend mode, the user can program the device by writing
the appropriate command sequence for Byte Program.
This program mode is known as the erase suspend-program mode. Again, programming in this mode
is the same as programming in regular Byte Program
mode, except that the data must be programmed to
sectors that are not erase suspended. Successively
reading from the erase suspended sector while the device is in the erase suspend-program mode will cause
DQ2 to toggle. The end of the erase suspend-program
operation is detected by the RY/BY output pin, DATA
Polling of DQ7, or by the Toggle Bit (DQ6), which is the
same as the regular Byte Program operation. Note that
DQ7 must be read from the Byte Program address
while DQ6 can be read from any address.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended.
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data
8/18/97
Am29F800T/Am29F800B
15
P R E L I M I N A R Y
Write Operation Status
Table 8.
Status
DQ7
DQ6
DQ5
DQ3
DQ2
RDY/BSY
Byte Programming
DQ7
Toggle
0
0
No Tog
0
0
Toggle
0
1
(Note 1)
0
1
No Tog
0
1
Toggle
1
Data
Data
Data
Data
Data
1
DQ7
(Note 2)
Toggle
0
1
DQ7
Toggle
1
0
No Tog
0
0
Toggle
1
1
(Note 3)
0
DQ7
Toggle
1
1
(Note 3)
0
Program/Erase in Auto-Erase
Erase
In Progress suspend
mode
Erase sector address
Non-erase sector
address
Program in erase suspend
Exceeded
Hardware Sequence Flags
Byte Programming
Time
Program/Erase in Auto-Erase
Limits
Program in erase suspend
1
(Note 1)
0
Notes:
1. DQ2 can be toggled when sector address applied is that of an erasing sector. Conversely, DQ2 cannot be toggled when the
sector address applied is that of a non-erasing sector. DQ2 is therefore used to determine which sectors are erasing and
which are not.
2. These status flags apply when outputs are read from the address of a non-erase-suspended sector.
3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.
DQ7: Data Polling
The Am29F800 device features Data Polling as a
method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
device will produce the complement of the data last
written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the
Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output.
Upon completion of the Embedded Erase Algorithm an
attempt to read the device will produce a “1” at the DQ7
output. The flowchart for Data Polling (DQ7) is shown
in Figure 3.
For chip erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after
the last rising edge of the sector erase WE pulse. Data
Polling must be performed at sector addresses within
any of the sectors being erased and not a protected
sector. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the
output enable (OE) is asserted low. This means that the
device is driving status information on DQ7 at
one instant of time and then that byte’s valid data at the
ne x t in s ta nt o f ti m e. D e pe nd i ng on w he n th e
system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed
16
the Embedded Algorithm operations and DQ7 has a
valid data, the data outputs on DQ0–DQ6 may be still
invalid. The valid data on DQ0–DQ7 will be read on the
successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or sector erase time-out (see Table 7).
See Figure 11 for the Data Polling timing specifications
and diagrams.
DQ6: Toggle Bit
The Am29F800 also features the “Toggle Bit” as a
method to indicate to the host system that the embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data
from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will
stop toggling and valid data will be read on the next
successive attempt. During programming, the Toggle
Bit is valid after the rising edge of the fourth WE pulse
in the four write pulse sequence. For chip erase, the
Toggle Bit is valid after the rising edge of the sixth WE
pulse in the six write pulse sequence. For Sector erase,
the Toggle Bit is valid after the last rising edge of the
sector erase WE pulse. The Toggle Bit is active during
the sector erase time-out.
Either CE or OE toggling will cause DQ6 to toggle. In
addition, an Erase Suspend/Resume command will
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
cause DQ6 to toggle. See Figure 12 for the Toggle Bit
timing specifications and diagrams.
DQ5: Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data Polling is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 1.
The DQ5 failure condition will also appear if a user tries
to program a 1 to a location that is previously programmed to 0. In this case the device locks out and
never completes the Embedded Program Algorithm.
Hence, the system never reads a valid data on DQ7 bit
and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1”.
Please note that this is not a device failure condition
since the device was incorrectly used. If this occurs,
reset the device.
DQ3: Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 may be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent
commands (other than Erase Suspend) to the device
will be ignored until the erase operation is completed
as indicated by Data Polling or Toggle Bit. If DQ3 is low
(“0”), the device will accept additional sector erase
commands. To insure the command has been accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 were high on the second status check, the command may not have been accepted.
Refer to Table 8, Hardware Sequence Flags.
DQ2: Toggle Bit 2
This toggle bit, along with DQ6, can be used to determi ne w h eth er th e de v ic e i s i n the E m bed de d
Erase Algorithm or in Erase suspend.
Successive reads from the erasing sector will cause
DQ2 to toggle during the Embedded Erase Algorithm.
If the device is in the erase suspend-read mode, successive reads from the erase-suspend sector will
cause DQ2 to toggle. When the device is in the erase
suspend-program mode, successive reads from the
8/18/97
byte address of the non-erase suspend sector will indicate a logic “1” at the DQ2 bit. Note that a sector which
is selected for erase is not available for read in Erase
Suspend mode. Other sectors which are not selected
for Erase can be read in Erase Suspend.
DQ6 is different from DQ2 in that DQ6 toggles only
when the standard program or erase, or erase suspend-program operation is in progress.
If the DQ5 failure condition is observed while in Sector
Erase mode (i.e., exceeded timing limits), the DQ2 toggle bit can give extra information. In this case, the normal function of DQ2 is modified. If DQ5 is at logic “1”,
then DQ2 will toggle with consecutive reads only at the
sector address that caused the failure condition. DQ2
will toggle at the sector address where the failure occurred and will not toggle at other sector addresses.
RY/BY: Ready/Busy
The Am29F800 provides a RY/BY open-drain output
pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been
completed. If the output is low, the device is busy with
either a program or erase operation. If the output is
high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the device
will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the Am29F800 is placed in an Erase Suspend
mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after
the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising
edge of the sixth WE pulse. The RY/BY pin should be
ignored while RESET is at VIL. Refer to Figure 13 for a
detailed timing diagram.
Since this is an open-drain output, several RY/BY
pins can be tied together in parallel with a pull-up resistor to VCC.
RESET: Hardware Reset
The Am29F800 device may be reset by driving the
RESET pin to VIL. The RESET pin must be kept low
(VIL) for at least 500 ns. Any operation in progress will
be terminated and the internal state machine will be
reset to the read mode 20 µs after the RESET pin is
driven low. Furthermore, once the RESET pin goes
high, the device requires an additional 50 ns before it
will allow read access. When the RESET pin is low, the
device will be in the standby mode for the duration of
the pulse and all the data output pins will be tri-stated.
If a hardware reset occurs during a program or erase
operation, the data at that particular location will
be indeterminate.
The RESET pin may be tied to the system reset input.
Therefore, if a system reset occurs during
the Embedded Program or Erase Algorithm, the device
Am29F800T/Am29F800B
17
P R E L I M I N A R Y
will be automatically reset to read mode and this will
enable the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word
(16 bit) mode for the Am29F800 device. When this pin is
driven high, the device operates in the word (16 bit)
mode. The data is read and programmed at DQ0–
DQ15. When this pin is driven low, the device operates
in byte (8 bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8–DQ14 bits are
tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at
DQ0–DQ7 and the DQ8–DQ15 bits are ignored. Refer
to Figures 15 and 16 for the timing diagram.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up
and power-down, the Am29F800 locks out write cycles
for VCC < VLKO (see DC Characteristics section for voltages). When V CC < V LKO , the command register
is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. The
Am29F800 ignores all writes until VCC > VLKO. The
user must ensure that the control pins are in the correct
logic state when VCC > VLKO to prevent unintentional
writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not initiate a write cycle.
Logical Inhibit
Data Protection
The Am29F800 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
Writing is inhibited by holding any one of OE = V IL,
CE = VIH, or WE = VIH. To initiate a write cycle CE and
WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V IL and
OE = VIH will not accept commands on the rising edge
of WE. The internal state machine is automatically
reset to the read mode on power-up.
The device also incorporates several features to prevent inadvertent write cycles resulting from V CC
power-up and power-down transitions or system noise.
18
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence
(see below)
Data Poll Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
20375C-6
Figure 1.
8/18/97
Embedded Programming Algorithm
Am29F800T/Am29F800B
19
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional
Sector Address/30H
20375C-7
Note:
1. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted.
Figure 2.
20
Embedded Erase Algorithm
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Start
VA = Byte address for programming
= any of the sector addresses within the
sector being erased during sector erase
operation
= Valid address equals any non-protected
sector group address during chip erase
Read Byte
(DQ0–DQ7)
Addr=VA
DQ7=Data
?
Yes
No
No
DQ5=1
?
Yes
Read Byte
(DQ0–DQ7)
Addr=VA
DQ7=Data
?
No
Yes
Pass
Fail
20375C-8
Note:
1. DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 3.
8/18/97
Data Polling Algorithm
Am29F800T/Am29F800B
21
P R E L I M I N A R Y
Start
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
DQ6=Toggle
?
No
Yes
No
DQ5=1
?
Yes
Read Byte
(DQ0–DQ7)
Addr=Don’t Care
DQ6=Toggle
?
No
Yes
Pass
Fail
20375C-9
Note:
1. DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
Figure 4.
Toggle Bit Algorithm
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20375C-10
20 ns
Figure 5.
Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
Figure 6.
22
20 ns
20375C-11
Maximum Positive Overshoot Waveform
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Voltage with Respect to Ground
All pins except A9 (Note 1) . . . . . . . . –2.0 V to +7.0 V
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
VCC (Note 1). . . . . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
VCC Supply Voltages
VCC for Am29F800T/B-70, 90,
120, 150 . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . . –2.0 V to +13.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot VSS to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is VCC + 0.5 V. During voltage transitions,
input and I/O pins may overshoot to VCC + 2.0 V for
periods up to 20ns.
Operating ranges define those limits between which the functionality of the device is guaranteed.
2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 may overshoot VSS to –2.0 V for
periods of up to 20 ns. Maximum DC input voltage on A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one
second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.
8/18/97
Am29F800T/Am29F800B
23
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
±1.0
µA
35
µA
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILIT
A9 Input Load Current
VCC = VCC Max, A9 = 13.0 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH
ICC2
VCC Active Current (Notes 2, 3)
CE = VIL, OE = VIH
60
mA
ICC3
VCC Standby Current
VCC = VCC Max, CE = VIH, OE = VIL
1.0
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
10.5
13.0
V
0.45
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 5.25 Volt
VOL
Output Low Voltage
IOL = 5.8 mA, VCC = VCC Min
VOH
Output High Voltage
IOH = –2.5 mA, VCC = VCC Min
VLKO
Low VCC Lock-Out Voltage
Byte
40
Word
50
mA
2.4
3.2
V
4.2
V
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Program or Erase Algorithm is in progress.
3. Not 100% tested.
24
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILIT
A9 Input Load Current
VCC = VCC Max, A9 = 13.0 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC Max
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH
ICC2
VCC Active Current (Notes 2, 3) CE = VIL, OE = VIH
ICC3
VCC Standby Current (Note 4)
VIL
Input Low Voltage
VIH
Input High Voltage
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 5.25 Volt
VOL
Output Low Voltage
IOL = 5.8 mA, VCC = VCC Min
VOH1
Output Low Voltage
VOH2
VLKO
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
Byte
20
40
Word
28
50
30
50
mA
1
5
µA
–0.5
0.8
V
0.7 x VCC
VCC + 0.3
V
10.5
13.0
V
0.45
V
mA
VCC = VCC Max,
CE = VCC ± 0.3 V,
OE = VIL, RESET = VCC ± 0.3 V
IOH = –2.5 mA, VCC = VCC Min
0.85 VCC
V
IOH = –100 µA, VCC = VCC Min
VCC –0.4
V
Low VCC Lock-Out Voltage
3.2
4.2
V
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Program or Erase Algorithm is in progress.
3. Not 100% tested.
4. ICC3 = 20 µA max at extended temperatures (>+85°C)
8/18/97
Am29F800T/Am29F800B
25
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options (Notes 1
and 2)
JEDEC
Standard
-70
-90
-120
-150
Unit
tAVAV
tRC
Read Cycle Time (Note 4)
Min
70
90
120
150
ns
tAVQV
tACC
Address to Output Delay
Max
70
90
120
150
ns
tELQV
tCE
Chip Enable to Output Delay
Max
70
90
120
150
ns
tGLQV
tOE
Output Enable to Output Delay
Max
30
35
50
55
ns
tEHQZ
tDF
Chip Enable to Output High Z (Notes 3, 4)
Max
20
20
30
35
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 3, 4)
Max
20
20
30
35
ns
tAXQX
tOH
Output Hold Time From Addresses, CE,
or OE, Whichever Occurs First
Min
0
0
0
0
ns
tReady
RESET Pin Low to Read Mode (Note 4)
Max
20
20
20
20
µs
CE to BYTE Switching Low or High
Max
5
5
5
5
ns
BYTE Switching Low to Output High Z
(Note 3)
Max
20
30
30
30
ns
tELFL
Description
Test Setup
CE = VIL
OE = VIL
OE = VIL
tELFH
tFLQZ
Notes:
1. Test Conditions (for -70 only):
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
input and output voltage: 1.5 V
2. Test Conditions (for all others):
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 20 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference
level, input and output voltages:
0.8 V and 2.0 V
3. Output driver disable time.
4. Not 100% tested.
5.0 V
IN3064
or Equivalent
Device
Under
Test
CL
2.7 kΩ
6.2 kΩ
Diodes = IN3064
or Equivalent
Notes:
For -70: CL = 30 pF including jig capacitance
For all others: CL = 100 pF including jig capacitance
Figure 7.
26
20375C-12
Test Conditions
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
AC CHARACTERISTICS
Write/Erase/Program Operations
Parameter
Symbols
JEDEC
Standard Description
-70
-90
-120
-150
Unit
tAVAV
tWC
Write Cycle Time (Note 2)
Min
70
90
120
150
ns
tAVWL
tAS
Address Setup Time
Min
0
0
0
0
ns
tWLAX
tAH
Address Hold Time
Min
45
45
50
50
ns
tDVWH
tDS
Data Setup Time
Min
30
45
50
50
ns
tWHDX
tDH
Data Hold Time
Min
0
0
0
0
ns
Output
Enable
Read (Note 2)
Min
0
0
0
0
ns
tOEH
Hold Time
Toggle and Data Polling (Note 2)
Min
10
10
10
10
ns
Min
0
0
0
0
ns
Read Recover Time Before Write
tGHWL
tGHWL
tELWL
tCS
CE Setup Time
Min
0
0
0
0
ns
tWHEH
tCH
CE Hold Time
Min
0
0
0
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
45
50
50
ns
tWHWL
tWPH
Write Pulse Width High
Min
20
20
20
20
ns
tWHWH1
tWHWH1
Byte Programming Operation
Typ
7
7
7
7
µs
Typ
1
1
1
1
sec
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
Max
8
8
8
8
sec
(OE High to WE Low)
tVCS
VCC Set Up Time (Note 2)
Min
50
50
50
50
µs
tVIDR
Rise Time to VID
Min
500
500
500
500
ns
RESET Pulse Width
Min
500
500
500
500
ns
tBUSY
Program/Erase Valid to RY/BY Delay (Note 2)
Min
30
35
50
55
ns
tRSP
RESET Setup Time for Temporary Sector Unprotect
(Notes 2, 3)
Min
4
4
4
4
µs
tRP
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
3. These timings are for Temporary Sector Unprotect operation.
4. Output Driver Disable Time.
8/18/97
Am29F800T/Am29F800B
27
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010
SWITCHING WAVEFORMS
tRC
Addresses
Addresses Stable
tACC
CE
(tDF)
tOE
OE
tOEH
WE
(tCE)
(tOH)
Outputs
High Z
Output Valid
High Z
20375C-13
Figure 8.
28
AC Waveforms for Read Operations
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
SWITCHING WAVEFORMS
3rd Bus Cycle
Data Polling
PA
PA
555H
Addresses
tWC
tRC
tAH
tAS
CE
tGHWL
OE
tWHWH1
tWP
WE
tWPH
tCS
tDH
Data
PD
A0H
tDF
tOE
DQ7
DOUT
tDS
tOH
5.0 V
tCE
20375C-14
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 9.
Program Operation Timings
555 for chip erase
tAH
Addresses
2AAH
555H
555H
555H
2AAH
SA
tAS
CE
tGHWL
OE
tWP
WE
tWPH
tCS
tDH
tDS
AAH
Data
VCC
55H
80H
AAH
tVCS
55H
10H/30H
20375C-15
Notes:
1. SA is the sector address for Sector Erase.
2. These waveforms are for the x16 mode.
Figure 10.
8/18/97
AC Waveforms Chip/Sector Erase Operations
Am29F800T/Am29F800B
29
P R E L I M I N A R Y
SWITCHING WAVEFORMS
tCH
CE
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7=
Valid Data
DQ7
DQ7
tOH
High Z
tWHWH 1 or 2
DQ0–DQ6=Invalid
DQ0–DQ6
DQ0–DQ6
Valid Data
20375C-16
Note:
*DQ7=Valid Data (The device has completed the Embedded operation).
Figure 11.
AC Waveforms for Data Polling During Embedded Algorithm Operations
CE
tOEH
WE
OE
*
Data
(DQ0–DQ7)
DQ6=Toggle
DQ6=
Stop Toggling
DQ6=Toggle
DQ0–DQ7
Valid
tOE
20375C-17
Note:
*DQ6 stops toggling (The device has completed the Embedded operation).
Figure 12.
30
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
Figure 13.
20375C-18
RY/BY Timing Diagram During Program/Erase Operations
RESET
tRP
tReady
20375C-19
Figure 14.
8/18/97
RESET Timing Diagram
Am29F800T/Am29F800B
31
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
OE
BYTE
tELFL
tELFH
DQ0–DQ14
Data Output
(DQ0–DQ14)
DQ15
Output
DQ15/A–1
Data Output
(DQ0–DQ7)
Address
Input
tFLQZ
20375C-20
Figure 15.
BYTE Timing Diagram for Read Operation
CE
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
tHOLD (tAH)
20375C-21
Figure 16.
32
BYTE Timing Diagram for Write Operations
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotect Completed
(Note 2)
20375C-22
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 17.
Temporary Sector Unprotect Algorithm
tVIDR
12 V
RESET
0 V or 5 V
0 V or 5 V
CE
WE
tRSP
Program or Erase Command Sequence
20375C-23
Figure 18.
8/18/97
Temporary Sector Unprotect Timing Diagram
Am29F800T/Am29F800B
33
P R E L I M I N A R Y
AC CHARACTERISTICS
Write/Erase/Program Operations
Alternate CE Controlled Writes
Parameter
Symbols
JEDEC
Standard Description
-70
-90
-120
-150
Unit
tAVAV
tWC
Write Cycle Time (Note 2)
Min
70
90
120
150
ns
tAVEL
tAS
Address Setup Time
Min
0
0
0
0
ns
tELAX
tAH
Address Hold Time
Min
45
45
50
50
ns
tDVEH
tDS
Data Setup Time
Min
30
45
50
50
ns
tEHDX
tDH
Data Hold Time
Min
0
0
0
0
ns
tOES
Output Enable Setup Time
Min
0
0
0
0
ns
Output Enable Read (Note 2)
Min
0
0
0
0
ns
Hold Time
Min
10
10
10
10
ns
Read Recover Time Before Write
Min
0
0
0
0
ns
tOEH
Toggle and Data Polling (Note 2)
tGHEL
tGHEL
tWLEL
tWS
WE Setup Time
Min
0
0
0
0
ns
tEHWH
tWH
WE Hold Time
Min
0
0
0
0
ns
tELEH
tCP
CE Pulse Width
Min
35
45
50
50
ns
tEHEL
tCPH
CE Pulse Width High
Min
20
20
20
20
ns
Byte Programming Operation
Typ
7
7
7
7
µs
tWHWH1
tWHWH1
Word Programming Operation
Typ
14
14
14
14
µs
Typ
1
1
1
1
sec
tWHWH2
tWHWH2
Max
8
8
8
8
sec
Max
20
30
30
30
ns
tFLQZ
Sector Erase Operation (Note 1)
BYTE Switching Low to Output High Z (Note 2)
Notes:
1. This does not include the preprogramming time.
2. Not 100% tested.
34
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
SWITCHING WAVEFORM
Data Polling
Addresses
PA
PA
555H
tWC
tAH
tAS
WE
tGHEL
OE
tCP
CE
tWS
tWHWH1
tCPH
tDH
Data
A0H
P
DQ7
DOUT
tDS
5.0 Volt
20375C-24
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
Figure 19.
8/18/97
Alternate CE Controlled Program Operation Timings
Am29F800T/Am29F800B
35
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
1.0
8
sec
Chip Erase Time (Note 3)
19
152
sec
Byte Programming Time (Note 5)
7
300
µs
Word Programming Time (Note 5)
14
600
µs
Chip Programming Time (Notes 3, 5)
7.2
21.6
sec
Erase/Program Endurance
1,000,000
cycles
Comments
Excludes 00H programming prior to
erasure
Excludes system-level overhead (Note 4)
Minimum 100,000 cycles guaranteed
Notes:
1. The typical erase and programming times assume the following conditions: 25°C, 5.0 volt VCC, 100,000 cycles. These
conditions do not apply to erase/program endurance. Programming typicals assume checkerboard pattern.
2. The maximum erase and programming times assume the following conditions: 90°C, 4.5 volt VCC, 100,000 cycles.
3. Although Embedded Algorithms allow for longer chip program and erase time, the actual time will be considerably less since
bytes program or erase significantly faster than the worst case byte.
4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each
byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.
5. The Embedded Algorithms allow for 2.5 ms byte program time. DQ5 = “1” only after a byte takes the theoretical maximum
time to program. A minimal number of bytes may require significantly more programming pulses than the typical byte. The
majority of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming
Times listed above.
LATCHUP CHARACTERISTICS
Input Voltage with respect to VSS on all I/O pins
VCC Current
Min
Max
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
36
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
CIN
Typ
Max
Unit
6
7.5
pF
8.5
12
pF
8
10
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VPP = 0
8
10
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
8/18/97
Am29F800T/Am29F800B
37
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
0.10
0.21
1.20
MAX
0.25MM (0.0098") BSC
0°
5°
16-038-TS48-2
TS 048
DA101
8-8-94 ae
0.50
0.70
38
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TSR048
48-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
0.08
0.20
0.10
0.21
1.20
MAX
0.25MM (0.0098") BSC
0°
5°
16-038-TS48
TSR048
DA104
8-8-94 ae
0.50
0.70
8/18/97
Am29F800T/Am29F800B
39
P R E L I M I N A R Y
PHYISICAL DIMENSIONS (continued)
SO 044
44-Pin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
1
15.70
16.30
22
1.27 NOM.
TOP VIEW
28.00
28.40
2.17
2.45
0.10
0.21
2.80
MAX.
0.35
0.50
0.10
0.35
SEATING
PLANE
SIDE VIEW
40
0°
8°
0.60
1.00
END VIEW
16-038-SO44-2
SO 044
DA82
11-9-95 lv
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
REVISION SUMMARY FOR Am29F800
Distinctive Characteristics:
High Performance: The fastest speed option available
is now 70 ns.
Enhanced power management for standby mode:
Changed typical standby current to 1µA.
General Description:
Added 70 ns speed option.
Product Selector Guide:
Added -70 column.
In fact, software programs written using the previous
four-digit definitions do not require any changes; they
remain completely compatible with the new three-digit
definitions.
The addresses for the byte-mode read cycles (fourth
cycle) in the autoselect mode are corrected from 01h to
02h for device ID, and from SAX02h to SAX04h for
sector protect verification.
Note 5 is clarified.
Pin Configuration:
Added -70 speed option.
Ordering Information, Standard Products:
The -70 speed option is now listed in the example.
Valid Combinations: Added combinations for the -70
speed option.
Table 7, Command Definitions:
Corrected byte addresses for unlock and command cycles from “2AA” to “AAA”.
In the previous data sheet revision, the addresses for
command definitions were shortened from four hexadecimal digits to three. The more accurately represents
the actual address bits required, A10–A0. The remaining upper address bits are don’t cares.
The new address is compatible with the previous fourdigit definition of “AAAA”; the only difference is that the
highest-order hexadecimal digit “A” is now “don’t care”.
Operating Ranges:
VCC Supply Voltages: Added -70 speed option to the
list.
DC Characteristics:
CMOS Compatible: Added column for typical ICC specifications. Revised max ICC specifications.
AC Characteristics:
Read Only Operations Characteristics: Added the -70
column and test conditions.
Test Conditions, Figure 7:
Changed speed option in first CL statement to -70.
AC Characteristics:
Write/Erase/Program Operations, Alternate CE Controlled Writes: Added the -70 column; revised word/
byte programming and sector erase specifications.
Erase and Programming Performance:
Revised specifications.
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof, and ExpressFlash are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
8/18/97
Am29F800T/Am29F800B
41