PRELIMINARY Advanced Micro Devices Am53C94/Am53C96 High Performance SCSI Controller DISTINCTIVE CHARACTERISTICS ■ Pin/function compatible with NCR53C94/53C96 ■ ■ AMD’s Patented GLITCH EATERTM Circuitry on REQ and ACK inputs High current drivers (48 mA) for direct connection to the single ended SCSI bus ■ Supports Disconnect and Reselect commands ■ 5 Mbytes per second synchronous SCSI transfer rate ■ Supports burst mode DMA operation with a threshold of 8 ■ 20 Mbytes per second DMA transfer rate ■ ■ 16-bit DMA Interface plus 2 bits of parity Supports 3-byte-tagged queuing as per the SCSI-2 specification ■ Flexible three bus architecture ■ ■ Single ended SCSI bus supported by Am53C94 Supports group 2 and 5 command recognition as per the SCSI-2 specification ■ ■ Single ended and differential SCSI bus supported by Am53C96 Advanced CMOS process for low power consumption ■ Am53C94 available in 84-pin PLCC package ■ Am53C96 available in 100-pin PQFP package ■ Selection of multiplexed or non-multiplexed address and data bus GENERAL DESCRIPTION The High Performance SCSI Controller (HPSC) has a flexible three bus architecture. The HPSC has a 16-bit DMA interface, an 8 bit host data interface and an 8-bit SCSI data interface. The HPSC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported. The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16 bit host data bus and the 8 bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet. Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through. The patented GLITCH EATER Circuitry in the High Performance SCSI Controller detects signal changes that are less than or equal to 15 ns and filters them out. It is designed to dramatically increase system performance and reliability by detecting and filtering glitches that can cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines only. These lines often encounter many electrical anomalies which degrade system performance and reliability. The two most common are Reflections and Voltage Spikes. Reflections are a result of high current SCSI signals that are mismatched by stubs, cables and terminators. These reflections vary from application to application and can trigger false handshake signals on the ACK and REQ lines if the voltage amplitude is at the TTL threshold levels. Spikes are generated by high current SCSI signals switching concurrently. On the control signals (ACK and REQ) they can trigger false data transfers which result in loss of data, addition of random data, double clocking and reduced system reliability. AMD’s GLITCH EATER Circuitry helps maintain excellent system performance by treating the glitches. Refer to the diagram on the next page. This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 16506 Rev. C Issue Date: May 1993 Amendment /0 AMD PRELIMINARY GLITCH EATER Circuitry in SCSI Environment >15 ns <15 ns SCSI Environment Valid Signal Device without the GLITCH EATER Circuit Glitches ACK or REQ Input Glitches pass through as valid signals AMD’s Device with the GLITCH EATER Circuit ACK or REQ Input Glitches Filtered Valid Signal Passes 16506C-1 SYSTEM BLOCK DIAGRAM Addr 4 CPU 9 16 8 Data SCSI Data Am53C94/96 9 SCSI Control 16 DMA 16 Memory 16 DMA 16506C-2 2 Am53C94/Am53C96 PRELIMINARY AMD SYSTEM BUS MODE DIAGRAMS BUSMD 1 DMAWR BUSMD 0 WR RD Address Bus Am53C94/96 A 3–0 Host Processor 8-Bit Data Bus DMA 7–0 DACK Bus Controller DREQ DMA Controller 16506C-3 Bus Mode 0 VDD BUSMD 1 DMAWR BUSMD 0 WR Am53C94/96 RD Address Bus A 3–0 Data Bus DMA 15–0 DACK DREQ Host Processor Bus Controller 8 16 DMA Controller 16506C-4 Bus Mode 1 Am53C94/Am53C96 3 AMD PRELIMINARY SYSTEM BUS MODE DIAGRAMS VDD BUSMD 1 WR RD BUSMD 0 Host Processor ALE 8-Bit Data Bus AD 7–0 Am53C94/96 16-Bit Data Bus DMA 15–0 AS0 BHE DMA Controller DMARD DMAWR DREQ DACK 16506C-5 Bus Mode 2 VDD BUSMD 1 WR BUSMD 0 RD Address Bus A 3–0 Host Processor 8-Bit Data Bus AD 7–0 Am53C94/96 16-Bit Data Bus DMA 15–0 DMA Controller DMAWR DREQ DACK 16506C-6 Bus Mode 3 4 Am53C94/Am53C96 PRELIMINARY AMD 18 16 x 9 FIFO (including parity) DMAP1-0 CS BUSMD1-0 6 8 MUX AD 7-0 Host Control Parity Logic 4 Bus Interface Unit DMA Control 8 Register Bank DFMODE CLK RESET 9 9 SCSI Bus Data + Parity (Single Ended) SCSI Bus Data + Parity Direction Control Main Sequencer 8 SCSI Sequencer SCSI Control 18 DMA 15-0 Data Tranceivers BLOCK DIAGRAM 9 7 SCSI Control SCSI Control Direction Control 16506C-7 Am53C94/Am53C96 5 4 3 2 VSS VSS DMA1 DMA0 DMA3 DMA2 DMA4 DMA6 DMA5 5 DMA7 6 VSS DMAP0 7 1 84 83 82 81 80 79 78 77 76 75 13 74 73 DMAWR DACK SD2 14 72 DREQ SD3 SD4 15 16 71 70 AD7 SD5 17 69 SD6 SD7 18 68 19 67 AD4 VSS SDP VDD VSS 20 66 AD3 65 64 AD2 AD1 SDC0 SDC1 23 24 63 62 VDD Am53C94 84-Pin PLCC 21 22 AD6 AD5 AD0 SDC2 25 61 CLK SDC3 26 60 ALE [A3] VSS 27 59 DMARD [A2] SDC4 28 58 BHE [A1] SDC5 29 57 SDC6 SDC7 30 56 AS0 [A0] CS RESET SDC P SDC 7 VSS NC VSS 16506C-8 SELC BSYC BUSMD 1 BUSMD 0 INT REQC ACKC VSS ACK RST REQ MSG VSS C/D ATN I/O RSTC VSS SEL BSY I/O ATN RSTC VSS MSG C/D SEL VSS ACKC VSS BSY REQ VSS BSYC REQC ACK RST BUSMD 1 INT BUSMD 0 SELC 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 RESET NC WR RD WR 31 SDCP RD DMA10 DMA9 DMA8 11 10 9 8 12 SD0 SD1 DMA11 DMAP1 DMA15 CONNECTION DIAGRAMS Top View DMA12 PRELIMINARY DMA14 DMA13 AMD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CS AS0 [A0] 81 82 50 SDC 6 49 SDC 5 BHE [A1] 83 48 SDC 4 DMARD [A2] 84 47 VSS ALE [A3] 85 46 VSS CLK 86 45 SDC 3 DFMODE VDD 87 44 SDC 2 88 43 SDC 1 NC 89 42 SDC 0 AD0 90 41 VSS AD1 91 40 VSS AD2 92 39 NC AD3 93 38 VDD VSS 94 37 SD P VSS 95 36 SD 7 AD4 96 35 SD 6 AD5 97 34 SD 5 AD6 98 33 SD 4 AD7 99 32 SD 3 DREQ 100 31 SD 2 SD 1 SD 0 NC DMA15 DMAP1 DMA1 DMA14 DMA0 DMA13 VSS DMA12 TSEL DMA11 VSS DMA10 ISEL DMA9 NC DMA8 DACK VSS 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VSS 8 DMAP0 7 DMA7 6 DMA6 5 DMA5 4 DMA4 3 DMA3 2 DMA2 1 DMAWR Am53C96 100-Pin PQFP 16506C-9 6 Am53C94/Am53C96 PRELIMINARY AMD LOGIC SYMBOL SD7–0 SDP SDC7–0 SDCP DMA15–0 DMAP1–0 ALE [A3] MSG DMARD [A2] BHE [A1] C/D AS0 [A0] I/O DREQ ATN DACK BSY Am53C94/96 AD7–0 DMAWR SEL RST REQ RD ACK WR BSYC CS SELC INT BUSMD1–0 *DFMODE CLK RESET RSTC REQC ACKC *ISEL *TSEL Note: 16506C-10 *Pins available on the Am53C96 only. RELATED AMD PRODUCTS Part Number 85C30 26LSXX 33C93A 80C186 80C286 80286 Description Part Number Enhanced Serial Communcaiton Controller Line Drivers/Receivers Enhanced CMOS SCSI Bus Interface Controller Highly Integrated 16-Bit Microprocessor High-Performance 16-Bit Microprocessor TM Am386 80188 53C80A 85C80 53C94LV Am53C94/Am53C96 Description High-Performance 32-Bit Microprocessor Highly Integrated 8-Bit Microprocessor SCSI Bus Controller Combination 53C80A SCSI and 85C30 ESCC Low Voltage, High Performance SCSI Controller 7 AMD PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM53C96 K C /W ALTERNATE PACKAGING OPTION /W = Trimmed and Formed in a Tray (PQJ100) Blank = Molded Carrier Ring (35 mm) TEMPERATURE RANGE C = Commercial PACKAGE TYPE J = 84-Pin PLCC (PL 084) K = 100-Pin PQFP (PQR100) DEVICE NUMBER/DESCRIPTION Am53C94/Am53C96 High Performance SCSI Conroller Valid Combinations AM53C94 AM53C96 8 JC KC, KC/W Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check on newly released combinations. Am53C94/Am53C96 PRELIMINARY AMD SCSI OUTPUT CONNECTIONS Am53C94 SD7–0, P SDC7–0, P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ATN 16506C-11 Am53C94 Single Ended SCSI Bus Configuration Am53C94/Am53C96 9 AMD PRELIMINARY SCSI OUTPUT CONNECTIONS Am53C96 SD7–0, P SDC7–0, P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ATN DFMODE VCC Am53C96 Single Ended SCSI Bus Configuration 16506C-12 Am53C96 SD7–0, P DT SDC7–0, P SEL, BSY, RST DT SELC, BSYC, RSTC ATN, ACK DT ISEL MSG, C/D, I/O, REQ DT TSEL DFMODE Am53C96 Differential SCSI Bus Configuration 10 Am53C94/Am53C96 16506C-13 PRELIMINARY AMD TSEL MSG – MSG + MSG TSEL C/D – C/D + C/D SDC 0 SD 0 TSEL – SD 0 + SD 0 I/O – I/O + I/O SDC 1 SD 1 75ALS170 – SD 1 + SD 1 ISEL SDC 2 ATN – ATN + ATN SD 2 – SD 2 + SD 2 75ALS170 SDC 3 SD 3 – SD 3 + SD 3 SDC 4 SD 4 75ALS170 – SD 4 + SD 4 Vcc SELC GND SDC 5 SD 5 – SEL + SEL SEL – SD 5 + SD 5 BSYC 75ALS170 GND – BSY + BSY BSY RSTC GND SDC 6 SD 6 – RST + RST RST GND – SD 6 + SD 6 SDC 7 SD 7 75ALS171 – SD 7 + SD 7 Vcc TSEL REQC SDC P – REQ + REQ REQ SD P – SD P + SD P ISEL ACKC 75ALS170 – ACK + ACK ACK GND 16506C-14 75ALS171 Differential Transceiver Connections for the Differential SCSI Bus Configuration Using 75ALS170 and 75ALS171 Transceivers Am53C94/Am53C96 11 AMD PRELIMINARY TSEL SDC 0 MSG SD 0 MSG – MSG + MSG SD 0 TSEL SDC 0 TSEL SDC 1 C/D C/D SD 1 – C/D + C/D SD 1 TSEL SDC 1 TSEL SDC 2 – I/O + I/O SD 2 TSEL SDC 2 ISEL SDC 3 ATN SD 3 ATN – ATN + ATN SD 3 ISEL SDC 3 SELC SDC 4 GND SEL SD 4 SD 5 – BSY + BSY SD 5 GND SDC 5 RSTC SDC 6 – SD 5 + SD 5 SD 6 GND – RST + RST SD 6 GND SDC 6 TSEL SDC 7 REQC – SD 6 + SD 6 SD 7 – REQ + REQ SD 7 GND SDC 7 ISEL SDC P ACKC SD P ACK – SD 4 + SD 4 SDC 5 GND REQ – SD 3 + SD 3 SDC 4 BSYC RST – SD 2 + SD 2 SD 4 – SEL + SEL GND BSY – SD 1 + SD 1 SD 2 I/O I/O – SD 0 + SD 0 – ACK + ACK SD P – SD 7 + SD 7 – SD P + SD P SDC P GND 16506C-15 Differential Transceiver Connections for the Differential SCSI Bus Configuration Using 75176A Transceiver 12 Am53C94/Am53C96 PRELIMINARY PIN DESCRIPTION Host Interface Signals AMD AS0 [A0] DMA 15–0 Data/DMA Bus (Input/Output, Active High, Internal Pull-up) The configuration of this bus depends on the Bus Mode 1–0 (BUSMD 1–0) inputs. When the device is configured for a single bus operation, the host can access the internal register set on the lower eight lines and the DMA accesses can be made to the FIFO using entire bus. When using the Byte Mode via the BHE and A0 inputs the data can be transferred on either the upper or lower half of the DMA 15–0 bus. DMAP 1–0 Data/DMA Parity Bus (Input/Output, Active High, Internal Pull-up) These lines are odd parity for the DMA 15–0 bus. DMAP 1 is the parity for the upper half of the bus DMA 15–8 and DMAP 0 is the parity for the lower half of the bus DMA 7–0. ALE [A3] Address Status [Address 0] (Input, Active High) This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as AS0. As AS0, this input works in conjunction with BHE to indicate the lines on which data transfer will take place. When the device is configured for all other bus modes, this input acts as A0. As A0, this input is the zeroth bit of the address bus. The following is the decoding for the BHE and AS0 inputs: BHE AS0 Bus Used 1 1 Upper Bus – DMA 15–8, DMAP 1 1 0 Full Bus – DMA 15–0, DMAP 1–0 0 1 Reserved 0 0 Lower Bus – DMA 7–0, DMAP 0 DREQ Address Latch Enable [Address 3] (Input, Active High) This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as ALE. As ALE, this input latches the address on the AD 7–0 bus on its Low going edge. When the device is configured for all other bus modes, this input acts as A3. As A3, this input is the third bit of the address bus. DMARD [A2] DMA Request (Output, Active High, Hi-Z) This output signal to the DMA controller will be active during DMA read and write cycles. During a DMA read cycle it will be active as long as there is a word (or a byte in the byte mode) in the FIFO to be transferred to memory. During a DMA write cycle it will be active as long as there is an empty space for a word (or a byte in the byte mode) in the FIFO. DACK DMA Read [Address 2] (Input, Active Low [Active High]) This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as DMARD. As DMARD, this input is the read signal for the DMA 15–0 bus. When the device is configured for all other bus modes, this input acts as A2. As A2, this input is the second bit of the address bus. DMA Acknowledge (Input, Active Low) This input signal from the DMA controller will be active during DMA read and write cycles. The DACK signal is used to access the DMA FIFO only and should never be active simultaneously with the CS signal, which accesses the registers only. AD 7–0 BHE [A1] Host Address Data Bus (Input/Output, Active High, Internal Pull-up) Bus High Enable [Address 1] (Input, Active High) This bus is used only in the dual bus mode. This bus allows the host processor to access the device’s internal registers while the DMA bus is transferring data. When using multiplexed bus, these lines can be used for address and data. When using non multiplexed bus these lines can be used for the data only. This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as BHE. As BHE, this input works in conjunction with AS0 to indicate the lines on which data transfer will take place. When the device is configured for all other bus modes this input acts as A1. As A1, this input is the first bit of the address bus. Am53C94/Am53C96 13 AMD PRELIMINARY DMAWR BUSMD 1–0 DMA Write (Input, Active Low) Bus Mode (Input, Active High) This signal writes the data on the DMA 15–0 bus into the internal FIFO when DACK is also active. When in the single bus mode this signal must be tied to the WR signal. These inputs configure the device for single bus or dual bus operation and the DMA width. BUSMD1 RD BUSMD0 Bus Configuration 1 1 Two buses: 8-bit Host Bus and 16-bit DMA Bus Register Address on A 3–0 and Data on AD Bus 1 0 Two buses: Multiplexed and byte control Register Address on AD 3–0 and Data on AD Bus 0 1 Single bus: 8-bit Host Bus and 16-bit DMA Bus Register Address on A 3–0 and Data on DMA Bus 0 0 Single bus: 8-bit Host Bus and 8-bit DMA Bus Register Address on A 3–0 and Data on DMA Bus Read (Input Active Low) This signal reads the internal device registers and places their contents on the data bus, when either CS signal or DACK signal is active. WR Write (Input Active Low) This signal writes the internal device registers with the value present on the data bus, when the CS signal is also active. CS Chip Select (Input Active Low) This signal enables the read and write of the device registers. CS enables access to any register (including the FIFO) while the DACK enables access only to the FIFO. CS and DACK should never be active simultaneously in the single bus mode, they may however be active simultaneously in the dual bus mode provided the CS signal is not enabling access to the FIFO. INT Clock (Input) Clock input used to generate all the internal device timings. The maximum frequency of this input is 25 MHz. and a minimum of 10 MHz to maintain the SCSI bus timings. RESET Interrupt (Output, Active Low, Open Drain) This signal is a non maskable interrupt flag to the host processor. This signal is latched on the output on the high going edge of the clock. This flag may be cleared by reading the Interrupt Status Register (ISTAT) or by performing a device reset (hard or soft). This flag is not cleared by a SCSI reset. Reset (Input, Active High) This input when active resets the device. The RESET input must be active for at least two CLK periods after the voltage on the power inputs have reached Vcc minimum. SCSI Interface Signals DFMODE SD 7–0 Differential Mode (Input, Active Low) This input is available only on the Am53C96. This input configures the SCSI bus to either single ended or differential mode. When this input is active, the device operates in the differential SCSI mode. The SCSI data is available on the SD 7–0 lines and the high active transceiver enables on the SDC 7–0 outputs. When this input is inactive, the device operates in the single ended SCSI mode. The SCSI input data is available on SD 7–0 lines and the output data is available on SDC 7–0 lines. In the single ended SCSI mode, the SD 7–0 and the SDC 7–0 buses can be tied together externally. 14 CLK SCSI Data (Input/Output, Active Low, Schmitt Trigger) When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) these pins are defined as inputs for the SCSI data bus. When the device is configured in the Differential SCSI Mode (DFMODE active) these pins are defined as bidirectional SCSI data bus. Am53C94/Am53C96 PRELIMINARY AMD SDP ATN SCSI Data Parity (Input/Output, Active Low, Schmitt Trigger) Attention (Input/Output, Active Low, Schmitt Trigger) When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as the input for the SCSI data parity. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as bidirectional SCSI data parity. This signal is a 48 mA output in the initiator mode and a Schmitt trigger input in the target mode. This signal will be asserted when the initiator detects a parity error or it can be asserted via certain initiator commands. BSY SDC 7–0 Busy (Input, Active Low, Schmitt Trigger) SCSI Data Control (Output, Active Low, Open Drain) This is a SCSI input signal with a Schmitt trigger. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) these pins are defined as outputs for the SCSI data bus. When the device is configured in the Differential SCSI Mode (DFMODE active) these pins are defined as direction controls for the external differential transceivers. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. SEL Select (Input, Active Low, Schmitt Trigger) This is a SCSI input signal with a Schmitt trigger. RST SDCP Reset (Input, Active Low, Schmitt Trigger) SCSI Data Control Parity (Output, Active Low, Open Drain) This is a SCSI input signal with a Schmitt trigger. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as an output for the SCSI data parity. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. REQ MSG This is a SCSI input signal with a Schmitt trigger. Message (Input/Output, Active Low, Schmitt Trigger) BSYC This is a bidirectional signal with 48 mA output driver. It is an output in the target mode and a Schmitt trigger input in the initiator mode. C/D Command/Data (Input/Output, Schmitt Trigger) This is a bidirectional signal with 48 mA output driver. It is an output in the target mode and a Schmitt trigger input in the initiator mode. Request (Input, Active Low, Schmitt Trigger) This is a SCSI input signal with a Schmitt trigger. ACK Acknowledge (Input, Active Low, Schmitt Trigger) Busy Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as a BSY output for the SCSI bus. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. I/O Input/Output (Input/Output, Schmitt Trigger) This is a bidirectional signal with 48 mA output driver. It is an output in the target mode and a Schmitt trigger input in the initiator mode. Am53C94/Am53C96 15 AMD PRELIMINARY SELC REQC Select Control (Output, Active Low, Open Drain) Request Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as a SEL output for the SCSI bus. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. This is a SCSI output with 48 mA drive. This signal is activated only in the target mode. RSTC ISEL Reset Control (Output, Active Low, Open Drain) Initiator Select (Output, Active High) This is a SCSI output with 48 mA drive. The Reset SCSI command will cause the device to drive RSTC active for 25 ms–40 ms, which will depend on the CLK frequency and the conversion factor. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as a RST output for the SCSI bus. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. This signal is available on the Am53C96 only. This signal is active whenever the device is in the initiator mode. In the differential mode this signal is used to enable the initiator signals ACKC and ATN and the device also drives these signals. ACKC Acknowledge Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. This signal is activated only in the initiator mode. TSEL Target Select (Output, Active High) This signal is available on the Am53C96 only. This signal is active whenever the device is in the target mode. In the differential mode this signal is used to enable the target signals REQC, MSG, C/D and I/O and the device also drives these signals. FUNCTIONAL DESCRIPTION Register Map Address (Hex.) Operation 00 Read 00 Write 01 Read 01 Write 02 03 04 04 05 05 Read/Write Read/Write Read Write Read Write Address (Hex.) Operation Register Current Transfer Count Register LSB Start Transfer Count Register LSB Current Transfer Count Register MSB Start Transfer Count Register MSB FIFO Register Command Register Status Register SCSI Destination ID Register Interrupt Status Register SCSI Timeout Register Register 06 Read Internal State Register 06 Write 07 Read 07 08 09 0A 0B 0C Write Read/Write Write Write Read/Write Read/Write Synchronous Transfer Period Register Current FIFO/Internal State Register Synchronous Offset Register Control Register 1 Clock Factor Register Forced Test Mode Register Control Register 2 Control Register 3 0F Write Data Alignment Register Note: Not all registers in this device are both readable and writable. Some read only registers share the same address with write only registers. The registers can be accessed by asserting the CS signal and then asserting either RD or WR signal depending on the operation to be performed. Only the FIFO Register can be accessed by asserting either CS or DACK in conjunction with RD and WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid when CS is used. 16 Am53C94/Am53C96 PRELIMINARY STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0 Current Transfer Count Register (00H–01H) Read Only Current Transfer Count Register CTCREG 15 14 CRVL15 CRVL14 13 CRVL13 12 Address: 00H–01H Type: Read 11 10 CRVL12 CRVL11 CRVL10 9 8 CRVL9 CRVL8 x x x x x x x x 7 6 5 4 3 2 1 0 CRVL5 CRVL4 CRVL3 CRVL2 CRVL1 CRVL0 x x x x x x CRVL7 x CRVL6 x This is a two-byte register. It contains the number of bytes to be transferred during a DMA operation. The value of this register is set to the number of bytes to be transferred prior to a DMA transfer command. This register retains its programmed value until it is overwritten and is not affected by hardware or software reset. Therefore, it is not necessary to reprogram the count for subsequent DMA transfers of the same size. Writing a zero to this register sets a maximum transfer count of 65536 bytes. The value in this register is undefined at power-up. FIFO Register (02H) Read/Write FIFO Register FFREG 16506C-16 CTCREG – Bits 15:0 – CRVL 15:0 – Current Value 15:0 This is a two-byte register. It counts down to keep track of the number of DMA transfers. Reading this registers will return the current value of the counter. The counter will decrement by one for every byte transferred and two for every word transferred over the SCSI bus. The transaction is complete when the count reaches zero. These registers are automatically loaded with the values in the Start Transfer Count Register every time a DMA command is issued. In the target mode, this counter is decremented by the active edge of DACK during the Data-In phase and by REQC during the Data-Out phase. In the initiator mode, the counter is decremented by the active edge of DACK during the Synchronous Data-In phase or by ACKC during the Asynchronous Data-In phase and by DACK during the Data-Out phase. Start Transfer Count Register (00H–01H) Write Only Start Transfer Count Register STCREG AMD Address: 00H–01H Type: Write 15 14 13 12 11 10 9 8 STVL15 STVL14 STVL13 STVL12 STVL11 STVL10 STVL9 STVL8 x x x x x x x x Address: 02H Type: Read/Write 7 6 5 4 3 2 1 0 FF7 FF6 FF5 FF4 FF3 FF2 FF1 FF0 0 0 0 0 0 0 0 0 16506C-18 FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0 The bottom of the 16x9 FIFO is mapped into the FIFO Register address. By reading and writing this register the bottom of the FIFO can be read or written. This is the only register that can also be accessed by DACK along with DMARD or DMAWR. This register is reset to zero by hardware or software reset and also at the start of a selection or reselection sequence. Command Register (03H) Read/Write Command Register CMDREG Address: 03H Type: Read/Write 7 6 5 4 3 2 1 0 DMA CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 x x x x x x x x Command 6:0 Direct Memory Access 16506C-019 7 6 5 STVL7 STVL6 STVL5 x x x 4 STVL4 x 3 2 1 0 STVL3 STVL2 STVL1 STVL0 x x x x 16506C-017 Commands to the device are issued by writing to this register. This register is two deep which allows for command queuing. The second command can be issued before the first one is completed. The Reset command and the Stop DMA command are not queued and are executed immediately. Reading this register will return the command currently being executed (or the last command executed if there are no pending commands). Am53C94/Am53C96 17 AMD PRELIMINARY CMDREG – Bit 7 – DMA – Direct Memory Access CMDREG – Bits 6:0 – CMD 6:0 – Command 6:0 The DMA bit when set notifies the device that the command is a DMA instruction, when reset it is a non-DMA instruction. For DMA instructions the Current Transfer Count Register (CTCREG) will be loaded with the contents of the Start Transfer Count Register (STCREG). The data is then transferred and the CTCREG is decremented for each byte until it reaches zero. These command bits decode the commands that the device needs to perform. There are a total of 29 commands grouped into four categories. The groups are Initiator Commands, Target Commands, Selection/ Reselection Commands and General Purpose Commands. Initiator Commands CMD6 0 0 0 0 0 0 CMD5 0 0 0 0 0 0 CMD4 1 1 1 1 1 1 CMD3 0 0 0 1 1 1 CMD2 0 0 0 0 0 0 CMD1 0 0 1 0 1 1 CMD0 0 1 0 0 0 1 Command Information Transfer Initiator Command Complete Steps Message Accepted Transfer Pad Bytes Set ATN Reset ATN CMD4 0 0 0 0 0 0 0 0 0 0 0 0 CMD3 0 0 0 0 0 0 0 1 1 1 1 0 CMD2 0 0 0 0 1 1 1 0 0 0 0 1 CMD1 0 0 1 1 0 0 1 0 0 1 1 0 CMD0 0 1 0 1 0 1 1 0 1 0 1 0 Command Send Message Send Status Send Data Disconnect Steps Terminate Steps Target Command Complete Steps Disconnect Receive Message Steps Receive Command Receive Data Receive Command Steps DMA Stop CMD4 0 0 0 0 0 0 0 CMD3 0 0 0 0 0 0 0 CMD2 0 0 0 0 1 1 1 CMD1 0 0 1 1 0 0 1 CMD0 0 1 0 1 0 1 0 Command Reselect Steps Select without ATN Steps Select with ATN Steps Select with ATN and Stop Steps Enable Selection/Reselection Disable Selection/Reselection Select with ATN3 Steps CMD4 0 0 0 0 CMD3 0 0 0 0 CMD2 0 0 0 0 CMD1 0 0 1 1 CMD0 0 1 0 1 Command No Operation Clear FIFO Reset Device Reset SCSI Bus Target Commands CMD6 0 0 0 0 0 0 0 0 0 0 0 0 CMD5 1 1 1 1 1 1 1 1 1 1 1 0 Idle Commands CMD6 1 1 1 1 1 1 1 CMD5 0 0 0 0 0 0 0 General Commands CMD6 0 0 0 0 18 CMD5 0 0 0 0 Am53C94/Am53C96 PRELIMINARY AMD Status Register (04H) Read Status Register STATREG Address: 04H Type: Read 7 6 5 4 3 2 1 0 INT IOE PE CTZ GCV MSG C/D I/O 0 0 0 0 0 x x x Input/Output Command/Data Message Group Code Valid Count to Zero Parity Error Illegal Operation Error Interrupt 16506C-20 This read only register contains flags to indicate the status and phase of the SCSI transactions. It indicates whether an interrupt or error condition exists. It should be read every time the host is interrupted to determine which device is asserting an interrupt. The data is latched until the Interrupt Status Register is read. The phase bits will be latched only if latching is enabled in the Control Register 2, otherwise, it will indicate the current SCSI phase. If command stacking is used, two interrupts might occur. Reading this register will clear the status information for the first interrupt and update the Status Register for the second interrupt. STATREG – Bit 7 – INT – Interrupt The INT bit is set when the device asserts the interrupt output. This bit will be cleared by a hardware or software reset. Reading the Interrupt Status Register will deassert the interrupt output and also clear this bit. STATREG – Bit 6 – IOE – Illegal Operation Error The IOE bit is set when an illegal operation is attempted. This condition will not cause an interrupt, it will be detected by reading the status register while servicing another interrupt. The following conditions will cause the IOE bit to be set: ■ DMA and SCSI transfer directions are opposite. ■ FIFO overflows. ■ In initiator mode an unexpected phase change detected during synchronous data transfer. ■ Command Register overwritten. This bit will be cleared by reading the Interrupt Status Register or by a hard or soft reset. STATREG – Bit 5 – PE – Parity Error The PE bit is set if the parity checking option is enabled in Control Register 1 and the device detects a parity error on incoming SCSI data, command, status or mes- sage bytes. Detection of a parity error condition will not cause an interrupt but will be reported with other interrupt causing conditions. When a parity error is detected in the information phase of the initiator mode ATN is asserted on the SCSI bus. This bit will be cleared by reading the Interrupt Status Register or by a hard or soft reset. STATREG – Bit 4 – CTZ – Count To Zero The CTZ bit is set when the Current Transfer Count Register (CTCREG) has counted down to zero. This bit will be reset when the CTCREG is written. Reading the Interrupt Status Register will not affect this bit. This bit will however be cleared by a hard or soft reset. Note: A non-DMA NOP will not reset the CTZ bit since it does not load the CTCREG but a DMA NOP will reset this bit since it loads the CTCREG. STATREG – Bit 3 – GCV – Group Code Valid The GCV bit is set if the group code field in the Command Descriptor Block (CDB) is one that is defined by the ANSI Committee in their document X3.131 – 1986. If the SCSI-2 Feature Enable (S2FE) bit in the Control Register 2 (CNTLREG2) is set, Group 2 commands will be treated as ten byte commands and the GCV bit will be set. If S2FE is reset then Group 2 commands will be treated as reserved commands. Group 3 and 4 command will always be considered as reserved commands. The device will treat all reserved commands as six byte commands. Group 6 commands will always be treated as vendor unique six byte commands and Group 7 commands will always be treated as vendor unique ten byte commands. The GCV bit is cleared by reading the Interrupt Status Register (INSTREG) or by a hard or soft reset. Am53C94/Am53C96 19 AMD PRELIMINARY STATREG – Bit 2 – MSG – Message The MSG, C/D and I/O bits together can be referred to as the SCSI Phase bits. They indicate the phase of the SCSI bus. These bits may be latched or unlatched depending on the option selected in Control Register 2 (CNTLREG2) by the Latch SCSI Phase (LSP) bit. STATREG – Bit 1 – C/D – Command/Data STATREG – Bit 0 – I/O – Input/Output Bit2 MSG Bit1 C/D Bit0 I/O SCSI Phase 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Message In Message Out Reserved Reserved Status Command Data_In Data_Out In the latched mode the SCSI phase bits are latched at the end of a command and the latch is opened when the Interrupt Status Register (INSTREG) is read. In the unlatched mode, they indicate the phase of the SCSI bus when this register is read. SCSI Destination ID Register (04H) Write SCSI Destination ID Register SDIDREG Address: 04H Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES RES DID2 DID1 DID0 0 0 0 0 0 x x x SCSI Destination ID 2:0 Reserved Reserved Reserved Reserved Reserved 16506C-21 At power-up the state of these bits is undefined. The DID 2:0 bits are not affected by reset. SDIDREG – Bits 7:3 – RES – Reserved SDIDREG – Bits 2:0 – DID 2:0 – Destination ID 2:0 The DID 2:0 bits are the encoded SCSI ID of the device on the SCSI bus which needs to be selected or reselected. 20 DID2 DID1 DID0 SCSI ID 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 7 6 5 4 3 2 1 0 Am53C94/Am53C96 PRELIMINARY AMD Interrupt Status Register (05H) Read Interrupt Status Register INSTREG 7 SRST 0 6 ICMD 0 Address: 05h Type: READ 5 4 3 2 1 0 DIS SR SO RESEL SELA SEL 0 0 0 0 0 0 Selected Selected with Attention Reselected Successful Operation Service Request Disconnected Invalid Command SCSI Reset 16506C-22 The Interrupt Status Register (INSTREG) will indicate the reason for the interrupt. This register is used with the Status Register (STATREG) and Internal Status Register (ISREG) to determine the reason for the interrupt. Reading the INSTREG will clear all three registers. quest. In the target mode this bit will be set when the initiator asserts the ATN signal. In the Initiator mode this bit is set whenever the target requests an information transfer phase. INSTREG – Bit 3 – SO – Successful Operation INSTREG – Bit 7 – SRST – SCSI Reset The SRST bit will be set if a SCSI Reset is detected and SCSI reset reporting is enabled via the DISR (bit 6) of the CNTLREG1. INSTREG – Bit 6 – ICMD – Invalid Command The ICMD bit will be set if the device detects an illegal command code. This bit is also set if a command code from a different mode is detected than the mode the device is currently in. INSTREG – Bit 5 – DIS – Disconnected The DIS bit can be set in the target or the initiator mode when the device disconnects from the SCSI bus. In the target mode this bit will be set if a terminate or a command complete sequence causes the device to disconnect from the SCSI bus. In the Initiator mode this bit will be set if the target disconnects or a selection or reselection timeout occurs. The SO bit can be set in the target or the initiator mode when an operation is successfully complete. In the target mode this bit will be set when any target mode command is completed. In the initiator mode this bit is set after a target has been successfully selected, after a command is successfully completed and after an information transfer command when the target requests a message in phase. INSTREG – Bit 2 – RESEL – Reselected The RESEL bit is set at the end of the reselection phase indicating that the device has been reselected as an initiator. INSTREG – Bit 1 – SELA – Selected with Attention The SELA bit is set at the end of the selection phase indicating that the device has been selected and that the ATN signal was active during the selection. INSTREG – Bit 0 – SEL – Selected INSTREG – Bit 4 – SR – Service Request The SR bit can be set in the target or the initiator mode when another device on the SCSI bus has a service re- The SEL bit is set at the end of the selection phase indicating that the device has been selected and that the ATN signal was inactive during the selection. Am53C94/Am53C96 21 AMD PRELIMINARY STIMREG – Bits 7:0 – STIM 7:0 – SCSI Timer 7:0 SCSI Timeout Register (05H) Write SCSI Timeout Register STIMREG Address: 05H Type: Write 7 6 5 4 3 2 1 0 STIM7 STIM6 STIM5 STIM4 STIM3 STIM2 STIM1 STIM0 x x x x x x x x The value loaded in STIM 7:0 can be calculated from the following formula: STIM 7:0 = [(SCSI Time Out) (Clock Frequency) / (8192 (Clock Factor))] Example: 16506C-23 This register determines how long the initiator (target) will wait for a target to respond to a selection (reselection) before timing out. It should be set to yield 250 ms to comply with ANSI standards for SCSI. SCSI Time Out (in seconds): 250 ms. (Recommended by the ANSI Standard) = 250 x 10–3 s. Clock Frequency: 20 MHz. (assume) = 20 x 106 Hz. Clock Factor: CLKF 2:0 from Clock Conversion Register (09H) = 5 STIM 7:0 = (250 x 10–3) X (20 x 106) / (8192 (5)) = 122 decimal Internal State Register (06H) Read Internal State Register ISREG Address: 06H Type: Read 7 6 5 4 3 2 1 0 RES RES RES RES SOF IS2 IS1 IS0 x x x x 0 0 0 0 Internal State 2:0 Synchronous Offset Flag Reserved Reserved Reserved Reserved 16506C-24 The Internal State Register (ISREG) tracks the progress of a sequence-type command. It is updated after each successful completion of an intermediate operation. If an error occurs, the host can read this register to determined at where the command failed and take the necessary procedure for recovery. Reading the Interrupt Status Register will clear this register. ISREG – Bits 7:4 – RES – Reserved 22 ISREG – Bit 3 – SOF – Synchronous Offset Flag The SOF is reset when the Synchronous Offset Register (SOFREG) has reached its maximum value. Note: The SOF bit is active Low. ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0 The IS 2:0 bits along with the Interrupt Status Register (INSTREG) indicates the status of the successfully completed intermediate operation. Refer to the Status Decode section for more details. Am53C94/Am53C96 PRELIMINARY AMD Initiator Select without ATN Steps Internal State Register (06H) Bits 2:0 (Hex) 0 4 3 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 18 2 18 Explanation Arbitration steps completed or disconnected or selection time–out Selection with ATN steps fully executed Sequence halted during command transfer due to premature phase change (target) Arbitration and selection completed; sequence halted because target failed to assert command phase Initiator Select with ATN Steps Internal State Register (06H) Bits 2:0 (Hex) 4 3 Interrupt Status Register (05H) Bits 7:0 (Hex) 18 18 2 18 0 18 Explanation Selection with ATN steps fully executed Sequence halted during command transfer due to premature phase change; some CDB bytes may not have been sent; check FIFO flags Message out completed; sent one message byte with ATN true, then released ATN; sequence halted because target failed to assert command phase after message byte was sent Arbitration and selection completed; sequence halted because target did not assert message out phase; ATN still driven by HPSC Initiator Select with ATN3 Steps Internal State Register (06H) Bits 2:0 (Hex) 0 4 3 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 18 2 18 0 18 Explanation Arbitration steps completed or disconnected or selection time–out Selection with ATN3 steps fully executed Sequence halted during command transfer due to premature phase change; some CDB bytes may not have been sent; check FIFO flags One, two, or three message bytes sent; sequence halted because target failed to assert command phase after third message byte, or prematurely released message out phase; ATN released only if third message byte was sent Arbitration and selection completed; sequence halted because target failed to assert message out phase; ATN still driven by HPSC Initiator Select with ATN and Stop Steps Internal State Register (06H) Bits 2:0 (Hex) 0 0 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 1 18 Explanation Arbitration steps completed or disconnected or selection time–out Arbitration and selection completed; sequence halted because target failed to assert message out phase; ATN still asserted by HPSC Message out completed; one message byte sent; ATN on Am53C94/Am53C96 23 AMD PRELIMINARY Target Selected without ATN Steps Internal State Register (06H) Bits 2:0 (Hex) 2 Interrupt Status Register (05H) Bits 7:0 (Hex) 11 1 11 2 1 01 01 0 01 Explanation Selected; received entire CDB; check group code valid bit; initiator asserted ATN in command phase Sequence halted in command phase due to parity error; some CDB bytes may not have been received; check FIFO flags; initiator asserted ATN in command phase Selected; received entire CDB; check group code valid bit Sequence halted in command phase because of parity error; some CDB bytes may not have been received; check FIFO flags Selected; loaded bus ID into FIFO; null–byte message loaded into FIFO Target Select with ATN Steps, SCSI–2 Bit NOT SET Internal State Register (06H) Bits 2:0 (Hex) 2 Interrupt Status Register (05H) Bits 7:0 (Hex) 12 1 0 12 12 2 1 02 02 0 02 Explanation Selection complete; received one message byte and entire CDB; initiator asserted ATN during command phase Halted in command phase; parity error and ATN true Selected with ATN; stored bus ID and one message byte; sequence halted because ATN remained true after first message byte Selection completed; received one message byte and the entire CDB Sequence halted in command phase because of parity error; some CDB bytes not received; check group code valid bit and FIFO flags Selected with ATN; stored bus ID and one message byte; sequence halted because of parity error or invalid ID message Target Select with ATN Steps, SCSI–2 Bit SET Internal State Register (06H) Bits 2:0 (Hex) 5 4 0 Interrupt Status Register (05H) Bits 7:0 (Hex) 12 12 02 Explanation Halted in command phase; parity error and ATN true ATN remained true after third message byte Selected with ATN; stored bus ID and one message byte; sequence halted because of parity error or invalid ID message 6 02 Selection completed; received three message bytes and the entire CDB 5 02 Received three message bytes then halted in command phase because of parity error; some CDB bytes not received; check group code valid bit and FIFO flags 402Parity error during second or third message byte Target Receive Command Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 Interrupt Status Register (05H) Bits 7:0 (Hex) 18 18 2 1 08 08 Explanation Received entire CDB; initiator asserted ATN Sequence halted during command transfer due to parity error; ATN asserted by initiator Received entire CDB Sequence halted during command transfer due to parity error; check FIFO flags Target Disconnect Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 0 24 Interrupt Status Register (05H) Bits 7:0 (Hex) 28 18 18 Explanation Disconnect steps fully executed; disconnected; bus is free Two message bytes sent; sequence halted because initiator asserted ATN One message byte sent; sequence halted because initiator asserted ATN Am53C94/Am53C96 PRELIMINARY AMD Target Terminate Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 Interrupt Status Register (05H) Bits 7:0 (Hex) 28 18 0 18 Explanation Terminate steps fully executed; disconnected; bus is free Status and message bytes sent; sequence halted because initiator asserted ATN Status byte sent; sequence halted because initiator asserted ATN Target Command Complete Steps Internal State Register (06H) Bits 2:0 (Hex) 1 0 2 Interrupt Status Register (05H) Bits 7:0 (Hex) 18 18 08 Explanation Status and message bytes sent; sequence halted because initiator set ATN Status byte sent; sequence halted because initiator set ATN Command complete steps fully executed Am53C94/Am53C96 25 AMD PRELIMINARY Synchronous Transfer Period Register (06H) Write Synchronous Transfer Period Register STPREG 7 6 5 4 3 Address: 06H Type: Write 1 0 2 RES RES RES STP4 STP3 STP2 STP1 STP0 x x x 0 0 1 0 1 Synchronous Transfer Period 4:0 Reserved Reserved Reserved 16506C-25 The Synchronous Transfer Period Register (STPREG) contains a 5-bit value indicating the number of clock cycles each byte will take to be transferred over the SCSI bus in synchronous mode. The minimum value allowed is 5. The STPREG defaults to five after a hard or soft reset. STPREG – Bits 7:5 – RES – Reserved STPREG – Bits 4:0 – STP 4:0 – Synchronous Transfer Period 4:0 The STP 4:0 bits are programmed to specify the synchronous transfer period or the number of clock cycles for each byte transfer in the synchronous mode. The minimum value for STP 4:0 is five. Missing table entries follow the binary code. 26 STP4 0 0 0 0 • • 1 0 0 0 0 Am53C94/Am53C96 STP3 0 0 0 0 • • 1 0 0 0 0 STP2 1 1 1 1 • • 1 0 0 0 0 STP1 0 0 1 1 • • 1 0 0 1 1 STP0 0 1 0 1 • • 1 0 1 0 1 Clocks/ Byte 5 5 6 7 • • 31 32 33 34 35 PRELIMINARY AMD Current FIFO/Internal State Register (07H) Read Current FIFO/Internal State Register CFISREG Address: 07H Type: Read 7 6 5 4 3 2 1 0 IS2 IS1 IS0 CF4 CF3 CF2 CF1 CF0 0 0 0 0 0 0 0 0 Current FIFO 4:0 Internal State 2:0 16506C-26 This register has two fields, the Current FIFO field and the Internal State field. CFISREG – Bits 7:5 – IS 2:0 – Internal State 2:0 that synchronous data transfer can continue. A zero value indicates that the synchronous offset count has been reached and no more data can be transferred until an acknowledge is received. The Internal State Register (ISREG) tracks the progress of a sequence-type command. CFISREG – Bits 4:0 – CF 4:0 – Current FIFO 4:0 The CF 4:0 bits are the binary coded value of the number of bytes in the FIFO. These bits should not be read when the device is transferring data since this count may not be stable. The IS 2:0 bits are duplicated from the IS 2:0 field in the Internal State Register (ISREG) in the normal mode. If the device is in the test mode, IS 0 is set to indicate that the offset value is non zero. A non zero value indicates Synchronous Offset Register (07H) Write Synchronous Offset Register SOFREG Address: 07H Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES SO3 SO2 SO1 SO0 x x x x 0 0 0 0 Synchronous Offset 3:0 Reserved Reserved Reserved Reserved The Synchronous Offset Register (SOFREG) contains a 4-bit count of the number of bytes that can be sent to (or received from) the SCSI bus without an ACK (or REQ). Bytes exceeding the threshold will be sent one byte at a time (asynchronously). That is, each byte will require an ACK/REQ handshake. To set up an asynchronous transfer, the SOFREG is set to zero. The SOFREG is set to zero after a hard or soft reset. 16506C-27 SOFREG – Bits 7:4 – RES – Reserved SOFREG – Bits 3:0 – SO 3:0 – Synchronous Offset 3:0 The SO 4:0 bits are the binary coded value of the number of bytes that can be sent to (or received from) the SCSI bus without an ACK (or REQ) signal. Am53C94/Am53C96 27 AMD PRELIMINARY Control Register One (08H) Read/Write Control Register One CNTLREG1 Address: 08H Type: Read/Write 7 6 5 4 3 2 1 0 ETM DISR PTE PERE STE CID2 CID1 CID0 0 0 0 0 0 x x x Chip ID 2:0 Self Test Enable Parity Error Reporting Enable Parity Test Enable Disable Interrupt on SCSI Reset Extended Timing Mode 16506C-28 The Control Register 1 (CNTLREG1) sets up the device with various operating parameters. CNTLREG1 – Bit 7 – ETM – Extended Timing Mode The ETM bit is set if an extra clock period is required between the data being driven on the bus and the REQ or ACK being asserted. This is some times necessary in high capacitive loading environments. The ETM bit is reset to zero by a hard or soft reset. CNTLREG1 – Bit 6 – DISR – Disable Interrupt on SCSI Reset The DISR bit masks the reporting of the SCSI reset. When the DISR bit is set and a SCSI reset is asserted, the device will disconnect from the SCSI bus and remain idle without interrupting the host processor. When the DISR bit is reset and a SCSI reset is asserted the device will respond by interrupting the host processor. The DISR bit is reset to zero by a hard or soft reset. CNTLREG1 – Bit 5 – PTE – Parity Test Enable The PTE bit is for test use only. When the PTE bit is set the parity on the output (SCSI or host processor) bus is forced to the value of the MSB (bit 7) of the output data from the internal FIFO. This allows parity errors to be created to test the hardware and software. The PTE bit is reset to zero by a hard or soft reset. 28 CNTLREG1 – Bit 4 – PERE – Parity Error Reporting Enable The PERE bit enables the checking and reporting of parity errors on incoming SCSI bytes during the information transfer phase. When the PERE bit set and a bad parity is detected, the PE bit in the STATREG is will be set but an interrupt will not be generated. In the initiator mode the ATN signal will also be asserted on the SCSI bus. When the PERE bit is reset and a bad parity occurs it is not detected and no action is taken. CNTLREG1 – Bit 3 – STE – Self Test Enable The STE bit is for test use only. When the STE bit is set the device is placed in a test mode which enables the device to access the test register at address 0AH. To reset this bit and to resume normal operation the device must be issued a hard or soft reset. CNTLREG1 – Bit 2:0 – CID 2:0 – Chip ID 2:0 The Chip ID 2:0 bits specify the binary coded value of the device ID on the SCSI bus. The device will arbitrate with this ID and will respond to selection or reselection to this ID. At power-up the state of these bit are undefined. These bits are not affected by hard or soft reset. Am53C94/Am53C96 PRELIMINARY AMD Clock Factor Register (09H) Write Clock Factor Register CLKFREG Address: 09H Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES RES CLKF2 CLKF1 CLKF0 x x x x x 0 1 0 Clock Factor 2:0 Reserved Reserved Reserved Reserved Reserved The Clock Factor Register (CLKFREG) must be set to indicate the input frequency range of the device. This value is crucial for controlling various timings to meet the SCSI specification. The selector can be calculated by rounding off the quotient of (Input Clock Frequency in MHz)/(5 MHz). The device has a frequency range of 10 to 25 MHz. 16506C-29 Input Clock CLKF0 Frequency in MHz CLKF2 CLKF1 0 1 0 10 0 1 1 10.01 to 15 1 0 0 15.01 to 20 1 0 1 20.01 to 25 CLKFREG – Bits 7:3 – RES – Reserved CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0 The CLKF 2:0 bits specify the binary coded value of the clock factor. The CLKF 2:0 bits will default to a value of 2 by a hard or soft reset. Forced Test Mode Register (0AH) Write Forced Test Mode Register FTMREG Address: 0AH Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES RES FHI FIM FTM x x x x x 0 0 0 Forced Target Mode Forced Initiator Mode Forced High Impedance Mode Reserved Reserved Reserved Reserved Reserved 16506C-30 The Forced Test Mode Register (FTMREG) is for test use only. The STE bit in the CNTLREG1 must be set for the FTMREG to operate. FTMREG – Bits 7:3 – RES – Reserved FTMREG – Bit 2 – FHI – Forced High Impedance Mode The FHI bit when set places all the output and bidirectional pins into a high impedance state. Am53C94/Am53C96 29 AMD PRELIMINARY FTMREG – Bit 1 – FIM – Forced Initiator Mode FTMREG – Bit 0 – FTM – Forced Target Mode The FIM bit when set forces the device into the initiator mode. The device will then execute all initiator commands irrespective of the SCSI bus status. The FTM bit when set forces the device into the target mode. The device will then execute all target commands irrespective of the SCSI bus status. Control Register Two (0BH) Read/Write Control Register Two CNTLREG2 Address: 0BH Type: Read/Write 7 6 5 4 3 2 1 0 DAE LSP SBO TSDR S2FE ACDPE PGRP PGDP 0 0 0 0 0 0 0 0 Pass Through/Generate Data Parity Pass Through/Generate Register Parity Abort on Command/Data Parity Error SCSI–2 Features Enable Tri–State DMA Request Select Byte Order Latch SCSI Phase Data Alignment Enable 16506C-31 The Control Register 2 (CNTLREG2) sets up the device with various operating parameters. actual state of the SCSI phase lines at any instant of time. The LSP bit is reset by a hard or soft reset. CNTLREG2 – Bit 7 – DAE – Data Alignment Enable CNTLREG2 – Bit 5 – SBO – Select Byte Order The DAE bit is used in the initiator Synchronous Data-In phase only. When the DAE bit is set one byte is reserved at the end of the FIFO when the phase changes to the Synchronous Data-In phase. The contents of this byte will become the lower byte of the DMA word (16-bit) transfer to the memory, the upper byte being the first byte of the first word received from the SCSI bus. The SBO bit is used only when the BUSMD 1:0 = 10 to enable or disable the byte control on the DMA interface. When SBO is set and the BUSMD 1:0 = 10, the byte control inputs BHE and AS0 control the byte positions. When SBO is reset the byte control inputs BHE and AS0 are ignored. Note: If an interrupt is received for a misaligned boundary on a phase change to synchronous data the following recovery procedure may be followed. The host processor should copy the byte at the start address in the host memory to the Data Alignment Register 0FH (DALREG) and then issue an information transfer command. The first word the device will write to the memory (via DMA) will consists of the lower byte from the DALREG and the upper byte from the first byte received from the SCSI bus. The DAE bit must be set before the phase changes to the Synchronous Data-In. The DAE bit is reset to zero by a hard or soft reset or by writing the DALREG when interrupted in the Synchronous Data-In phase. CNTLREG2 – Bit 6 – LSP – Latch SCSI Phase The LSP bit is used to enable or disable the latching of the SCSI phase bits (MSG, C/D and I/O) in the Status Register (STATREG) 04H. When the LSP bit is set the phase bits STSTREG – Bits 2:0 are latched at the end of each command. This simplifies software for stacked commands. When the LSP bit is reset the phase bits STATREG – Bits 2:0 reflect the 30 CNTLREG2 – Bit 4 – TSDR – Tri-State DMA Request The TSDR bit when set sends the DREQ output signal to high impedance state and the device ignores all activity on the DMA request (DREQ) input. This is useful for wiring-OR several devices that share a common DMA request line. When the TSDR bit is reset the DREQ output is driven to TTL levels. CNTLREG2 – Bit 3 – S2FE – SCSI–2 Features Enable The S2FE bit allows the device to recognize two SCSI-2 features. The two features are extended message feature and the Group 2 command recognition. Extended Message Feature: When the S2FE bit is set and the device is selected with attention, the device will monitor the ATN signal at the end of the first message byte. If the ATN signal is active, the device will request two more message bytes before switching to the command phase. If the ATN signal is inactive the device will switch to the command phase. When the S2FE bit is reset the device as a target will request a single message byte. As an initiator, the device will abort the selection sequence if the target does not switch to the command phase after receiving a single message byte. Am53C94/Am53C96 PRELIMINARY AMD Group 2 Command Recognition: When the S2FE bit is set the group 2 commands are recognized as 10 byte commands. The GCV (Group Code Valid) bit in the STATREG (04H) is set. When the S2FE bit is reset, the device will interpret the group 2 commands as reserved commands and will request 6 byte commands. The GCV bit in the STATREG will not be set in this case. PGRP bit is reset, the device generates the parity on the data from the host before writing it to the FIFO. CNTLREG2 – Bit 2 – ACDPE – Abort on Command/ Data Parity Error CNTLREG2 – Bit 0 – PGDP – Pass Through/Generate Data Parity The ACDPE bit when set allows the device to abort a command or data transfer when a parity error is detected. When the ACDPE bit is reset parity error is ignored. The PGDP bit when set causes the data along with the parity from the host to pass through to the FIFO under the control of the DACK and the WR signals. When the PGDP bit is reset, the device generates the parity on the data from the host before writing it to the FIFO. CNTLREG2 – Bit 1 – PGRP – Pass Through/Generate Register Parity When the device is placing the data on the SCSI bus, it will check for an outgoing parity error if either the PGDP bit is set or the PGRP (Pass Through/Generate Register Parity) bit is set. When the device is placing the data on the SCSI bus, it will check for an outgoing parity error if either the PGRP bit is set or the PGDP (Pass Through/Generate Data Parity) bit is set. The PGRP bit when set causes the data along with the parity from the host to pass through to the FIFO under the control of the CS and the WR signals. When the Control Register Three (0CH) Read/Write Control Register Three CNTLREG3 Address: 0CH Type: Read/Write 7 6 5 4 3 2 1 0 RES RES RES RES RES LBTM MDM BS8 0 0 0 0 0 0 0 0 Burst Size 8 Modify DMA Mode Last Byte Transfer Mode Reserved Reserved Reserved Reserved Reserved 16506C-32 CNTLREG3 – Bits 7:3 – RES – Reserved CNTLREG3 – Bit 1 – MDM – Modify DMA Mode CNTLREG3 – Bit 2 – LBTM – Last Byte Transfer Mode The LBTM bit specifies how the last byte in an odd byte transfer is handled during 16-bit DMA transfers. This mode is not used if byte control is selected via BUSMD 1:0 inputs and BSO (Byte Select Order) bit in the CNTLREG2. This mode has no affect during 8-bit DMA transfers and on transfers on the SCSI bus. When the LBTM bit is set the DREQ signal will not be asserted for the last byte, instead the host will read or write the last byte from or to the FIFO. When the LBTM bit is reset the DREQ signal will be asserted for the last byte and the following 16-bit DMA transfer will contain the last byte on the lower bus. If the transfer is a DMA read the upper bus will be all ones. The MDM bit is used to modify the timing of the DACK signal with respect to the DMARD and DMAWR signals. The MDM bit is used in conjunction with the Burst Size 8 (BS8) bit in the CNTLREG3. Both bits have to be set for proper operation. When the MDM bit is set and the device is in a DMA read or write mode the DACK signal will remain asserted while the data is strobed by the DMARD or DMAWR signals. In the DMA read mode when BUSMD 1:0 = 11 the DACK signal will toggle for every DMA read. When the MDM bit is reset and the device is in a DMA read or write mode the DACK signal will toggle every time the data is strobed by the DMARD or DMAWR signals. The LBTM bit is reset by hard or soft reset. Am53C94/Am53C96 31 AMD PRELIMINARY CNTLREG3 – Bit 0 – BS8 – Burst Size 8 The BS8 bit is used to modify the timing of the DREQ signal with respect to the DMARD and DMAWR signals. The BS8 bit is used in conjunction with the Modify DMA Mode (MDM) bit in the CNTLREG3. Both bits have to be set for proper operation. When the BS8 bit is set the device delays the assertion of the DREQ signal until 8 bytes or 4 words transfer is possible. When the BS8 bit is set and the device is in a DMA write mode the DREQ signal will be asserted only when 8 byte locations are available for writing. In the DMA read mode the DREQ signal will go active under the following circumstances: time the data is strobed by the DMARD or DMAWR signals. Using Bit 0 (BS8) and Bit 1 (MDM) of Control Register 3, one can enable the different combination modes shown in the table below. (MDM) (BS8) Bit 1 Bit 0 0 0 0 1 1 0 1 1 Maximum Synchronous Offset Normal DMA Mode 15 Burst Size 8 Mode 7 Reserved – Modified DMA Mode 15 Function At the end of a transfer, ■ In the target mode, – when the transfer is complete or – when the ATN signal is active ■ In the initiator mode, – when the Current Transfer Register is decremented to zero or – after any phase change Data Alignment Register (0FH) Write 16506C-33 In the middle of a transfer ■ In the initiator mode, – when the last 8 bytes of the FIFO are full – during Synchronous Data-In transfer when the Event Transfer Count Register is greater than 7 and the last 8 bytes of the FIFO are full. When the BS8 bit is reset and the device is in a DMA read or write mode the DREQ signal will toggle every 32 The Data Alignment Register (DALREG) is used if the first byte of a 16-bit DMA transfer from the SCSI bus to the host processor is misaligned. Prior to issuing an information transfer command, the host processor must set the Data Alignment Enable (DAE) bit in the CNTLREG2. DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0 Am53C94/Am53C96 PRELIMINARY AMD COMMANDS The device commands can be broadly divided into two categories, DMA commands and non-DMA commands. DMA commands are those which cause data movement between the host memory and the SCSI bus while non- DMA commands are those that cause data movement between the device FIFO and the SCSI bus. The MSB of the command byte differentiate the DMA from the nonDMA commands. Summary of Commands Command Code (Hex.) Command NonDMA Mode Command Code (Hex.) Command DMA Mode NonDMA Mode DMA Mode Idle State Commands Initiator Commands Information Transfer 10 90 Reselect Steps 40 C0 Initiator Command Complete Steps 11 91 Select without ATN Steps 41 C1 Message Accepted 12 – Select with ATN Steps 42 C2 Transfer Pad Bytes 18 98 Select with ATN and Stop Steps 43 C3 Set ATN 1A – Enable Selection/Reselection 44 C4 Reset ATN 1B – Disable Selection/Reselection 45 C5 Select With ATN3 46 C6 Target Commands Send Message 20 A0 General Commands Send Status 21 A1 No Operation 00 80 Send Data 22 A2 Clear FIFO 01 81 Disconnect Steps 23 A3 Reset Device 02 82 Terminate Steps 24 A4 Reset SCSI bus 03 83 Target Command Complete Steps 25 A5 Disconnect 27 A7 Receive Message 28 A8 Receive Command Steps 29 A9 Receive Data 2A AA Receive Command Steps 2B AB Target Abort DMA 04 84 Am53C94/Am53C96 33 AMD PRELIMINARY COMMAND DESCRIPTION Initiator Commands Initiator commands are executed by the device when it is in the initiator mode. If the device is not in the initiator mode and an initiator command is received the device will ignore the command, generate an illegal command interrupt and clear the Command Register (CMDREG) 03H. Information Transfer Command (Command Code 10H/90H) The Information Transfer command is used to transfer information bytes over the SCSI bus. This command may be issued during any SCSI Information Transfer phase. Information transfer for synchronous data must use the DMA mode. The device will continue to transfer information until it is terminated by any one of the following conditions: ■ The target changes the SCSI bus phase before the expected number of bytes are transferred. The device clears the Command Register (CMDREG) 03H, and generates a service interrupt when the target asserts REQ. ■ Transfer is successfully complete. If the phase is Message Out, the device deasserts ATN before asserting ACK for the last byte of the message. When the target asserts REQ, a service interrupt is generated. ■ In the Message In phase when the device receives the last byte. The device keeps the ACK signal asserted and generates a Successful Operation interrupt. During synchronous data transfers the target may send up to the maximum synchronous threshold number of REQ pulses to the initiator. If it is the Synchronous DataIn phase then the target sends the data and the REQ pulses. These bytes are stored by the initiator in the FIFO as they are received. Information Transfer Command when issued during the following SCSI phases and terminating in synchronous data phases, is handled as described below: ■ Message In/Status Phase – When a phase change to Synchronous Data-In or Synchronous Data-Out is detected by the device, the Command Register (CMDREG) 03H is cleared and the DMA interface is disabled to disallow any transfer of data phase bytes. If the phase change is to Synchronous Data-In and bad parity is detected on the data bytes coming in, it is not reported since the Status Register (STATREG) 04H will report the status of the command just completed. The parity error flag and the ATN signal will be asserted when the Transfer Information command begins execution. 34 ■ Message Out/Command Phase – When a phase change to Synchronous Data-In or Synchronous Data-Out is detected by the device, the Command Register (CMDREG) 03H is cleared and the DMA interface is disabled to allow any transfer of data phase bytes. If the phase change is to Synchronous Data-In and bad parity is detected on the data bytes coming in, it is not reported since the Status Register (STATREG) 04H will report the status of the command just completed. The parity error flag and the ATN signal will be asserted when the Transfer Information command begins execution. The FIFO Register29 (FFREG) 02H will be latched and will remain in that condition until the next command begins execution. The value in the FFREG indicates the number of bytes in the FIFO when the phase changed to Synchronous Data-In. These bytes are cleared from the FIFO, which now contains only the incoming data bytes. ■ In the Synchronous Data-Out phase, the threshold counter is incremented as REQ pulses are received. The transfer is completed when the FIFO is empty and the Current Transfer Count Register (CTCREG) 00H–01H is zero. The threshold counter will not be zero. ■ In the Synchronous Data-In phase, the Current Transfer Count Register (CTCREG) is decremented as bytes are read from the FIFO rather than being decremented when the bytes are being written to the FIFO. The transfer is completed when Current Transfer Count Register (CTCREG) is zero but the FIFO may not be empty. Initiator Command Complete Steps (Command Code 11H/91H) The Initiator Command Complete Steps command is normally issued when the SCSI bus is in the Status In phase. One Status byte followed by one Message byte is transferred if this command completes normally. After receiving the message byte the device will keep the ACK signal asserted to allow the initiator to examine the message and assert the ATN signal if it is unacceptable. The command terminates early if the target does not switch to the Message In phase or if the target disconnects from the SCSI bus. Message Accepted Command (Command Code 12H) The Message Accepted Command is used to release the ACK signal. This command is normally used to complete a Message In handshake. Upon execution of this command the device generates a service request interrupt after REQ is asserted by the target. Am53C94/Am53C96 PRELIMINARY After the device has received the last byte of message, it keeps the ACK signal asserted. This allows the device to either accept or reject the message. To accept the message, Message Accepted Command is issued. To reject the message the ATN signal must be asserted (with the help of the Set ATN Command) before issuing the Message Accepted Command. In either case the Message Accepted Command has to be issued to release the ACK signal. Transfer Pad Bytes Command (Command Code 18H/98H) The Transfer Pad Bytes Command is used to recover from an error condition. This command is similar to the Information Transfer Command, only the information bytes consists of null data. It is used when the target expects more data bytes than the initiator has to send. It is also used when the initiator receives more information than it expected from the target. When sending data to the SCSI bus, the FIFO is loaded with null bytes and these bytes are sent out to the SCSI bus. DMA has to be enabled when pad bytes are transferred to the SCSI bus. No actual DMA requests are made but the device uses the Current Transfer Count Register (CTCREG) 00H–01H to terminate the transfer. When receiving data from the SCSI bus, the device will receive the pad bytes and place them on the top of the FIFO and unload them from the bottom of the FIFO. The command terminates under the same condition as the Information Transfer Command, only the device does not keep the ACK signal asserted during the last byte of the Message In phase. If this command terminates prematurely, due to a disconnect or a phase change, before the CTCREG decrements to zero, the FIFO may contain residual pad bytes. Set ATN Command (Command Code 1AH) The Set ATN Command is used to drive the ATN signal active on the SCSI bus. An interrupt is not generated at the end of this command. The ATN signal is deasserted before asserting the ACK signal during the last byte of the Message Out phase. Note: The ATN signal is asserted by the device without this command in the following cases: ■ If any select with ATN command is issued and the arbitration is won. ■ An initiator needs the target’s attention to send a message. The ATN signal is asserted before deasserting the ACK signal. Reset ATN Command (Command Code 1BH) The Reset ATN Command is used to deassert the ATN signal on the SCSI bus. An interrupt is not generated at the end of this command. This command is used only when interfacing with devices that do not support the Common Command Set (CCS). These older devices do not deassert their ATN signal automatically on the last byte of the Message Out phase. This device does deas- AMD sert its ATN signal automatically on the last byte of the Message Out phase. Target Commands Target commands are executed by the device when it is in the target mode. If the device is not in the target mode and a target command is received the device will ignore the command, generate an illegal command interrupt and clear the Command Register (CMDREG) 03H. A SCSI bus reset during any target command will cause the device to abort the command sequence , flag a SCSI bus reset interrupt (if the interrupt is enabled) and disconnect from the SCSI bus. Normal or successful completion of a target command will cause a Successful Operation interrupt to be flagged. If the ATN signal is asserted during a target command sequence the Service Request bit is asserted in the Interrupt Status Register (INSTREG) 05H. If the ATN signal is asserted when the device is in an idle state a Service Request interrupt will be generated, the Successful Operation bit in the INSTREG will be reset and the CMDREG cleared. Send Message Command (Command Code 20H/A0H) The Send Message Command is used by the target to inform the initiator to receive a message. The SCSI bus phase lines are set to the Message In Phase and message bytes are transferred from the device FIFO to the buffer memory. Send Status Command (Command Code 21H/A1H) The Send Status Command is used by the target to inform the initiator to receive status information. The SCSI bus phase lines are set to the Status Phase and status bytes are transferred from the target device to the initiator device. Send Data Command (Command Code 22H/A2H) The Send Data Command is used by the target to inform the initiator to receive data bytes. The SCSI bus phase lines are set to the Data-In Phase and data bytes are transferred from the target device to the initiator device. Disconnect Steps Command (Command Code 23H/A3H) The Disconnect Steps Command is used by the target to disconnect from the SCSI bus. This command consists of two steps. The first step consists of sending two bytes of the Save Data Pointers commands by the target in the Message In Phase. In the second step the target disconnects from the SCSI bus. Successful Operation and Disconnected bits are set in the Interrupt Status Register (INSTREG) 05H upon command completion. If ATN signal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared and Disconnect Steps Command terminates without disconnecting. Am53C94/Am53C96 35 AMD PRELIMINARY The Terminate Steps Command is used by the target to disconnect from the SCSI bus. This command consists of three steps. The first step consists of sending one status byte by the target in the Status Phase. The second step consists of sending one message byte by the target in the Message In Phase. As the third step the target disconnects from the SCSI bus. Successful Operation and Disconnected bits are set in the Interrupt Status Register (INSTREG) 05H upon command completion. If ATN signal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared and Terminate Steps Command terminates without disconnecting. this command the target receives the command bytes from the initiator while the SCSI bus is in the Command Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) 05H upon command completion. If ATN signal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared and the command terminates prematurely. If a parity error is detected, the device continues to receive command bytes until the transfer is complete if the Abort on Command/ Data Parity Error (ACDPE) bit in the Control Register (CNTLREG2) 0BH is reset. If the ACDPE bit is set, the command is terminated immediately. The Parity Error (PE) bit in the Status Register (STATREG) 04H is set and CMDREG is cleared. Target Command Complete Steps Command (Command Code 25H/A5H) Receive Data Command (Command Code 2AH/AAH) The Target Command Complete Steps Command is used by the target to inform the initiator of a linked command completion. This command consists of two steps. The first step consists of sending one status byte by the target in the Status Phase. The second step consists of sending one message byte by the target in the Message In Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) 05H upon command completion. If ATN signal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared and Target Command Complete Steps Command terminates prematurely. The Receive Data Command is used by the target to request the initiator for data bytes. During this command the target receives the data bytes from the initiator while the SCSI bus is in the Data-Out Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) 05H upon command completion. If ATN signal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared and the command terminates prematurely. If a parity error is detected, the device continues to receive data bytes until the transfer is complete if the Abort on Command/Data Parity Error (ACDPE) bit in the Control Register (CNTLREG2) 0BH is reset. If the ACDPE bit is set, the command is terminated immediately. The Parity Error (PE) bit in the Status Register (STATREG) 04H is set and CMDREG is cleared. Terminate Steps Command (Command Code 24H/A4H) Disconnect Command (Command Code 27H/A7H) The Disconnect Command is used by the target to disconnect from the SCSI bus. All SCSI bus signals except RSTC are released and the device returns to the Disconnected state. The RSTC signal is driven active for about 25 micro seconds (depending on clock frequency and clock factor). Interrupt is not generated to the microprocessor. Receive Command Steps Command (Command Code 2BH/ABH) Receive Message Steps Command (Command Code 28H A8H) The target device determines the command byte length from the first command byte. If an unknown length is received, the Start Transfer Count Register (STCREG) 00H–01H is loaded with 5 and the Group Code Valid (GCV) bit in the Status Register (STATREG) 04H is reset. If a valid length is received, the STCREG is loaded with the appropriate value and the GCV bit in the STATREG is set. If ATN signal is asserted by the initiator then the Service Request bit is set in the INSTREG, and the CMDREG is cleared If a parity error is detected, the command is terminated prematurely and the CMDREG is cleared. The Receive Message Steps Command is used by the target to request message bytes from the initiator. During this command the target receives the message bytes from the initiator while the SCSI bus is in the Message Out Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) 05H upon command completion. If ATN signal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared. If a parity error is detected, the device ignores the received message bytes until ATN signal is asserted, the Successful Operation bit is set in the INSTREG, and the CMDREG is cleared. Receive Commands Command (Command Code 29H/A9H) The Receive Commands Command is used by the target to request the initiator for command bytes. During 36 The Receive Command Steps Command is used by the target to request the initiator for command information bytes. During this command the target receives the command information bytes from the initiator while the SCSI bus is in the Command Phase. DMA Stop Command (Command Code 04H/84H) The DMA Stop Command is used by the target to allow the microprocessor to discontinue data transfers due to a lack of activity on the DMA channel. This command is executed from the top of the command queue. If there is a queued command waiting execution, it will be overwritten and the Illegal Operation Error (IOE) bit in the Am53C94/Am53C96 PRELIMINARY Status Register (STATREG) 04H will be set. This command is cleared from the command queue once it is decoded. Caution must be exercised when using this command. The DMA Stop Command can be used only during a DMA Target Send Data Command or DMA Target Receive Data Command execution. In both cases the DMA controller has to be in the idle state. During a DMA Target Send Data Command the FIFO has to be empty or the Current FIFO (CF 4:0) bits in the Current FIFO/Internal State Register (CFISREG) 07H are zero. During a DMA Synchronous Target Receive Data Command the Current Transfer Count Register (CTCREG) 00–01H is zero, which is indicated by the Count to Zero (CTZ) bit of the Status Register (STATREG) 04H. or when the Synchronous Offset Register (SOFREG) 07H has reached its maximum value which is indicated by the Synchronous Offset Flag (SOF) bit of the Internal State Register (ISREG) 06H. During a DMA Asynchronous Target Receive Data Command the FIFO is full which is indicated by the Current FIFO (CF 4:0) bits in the Current FIFO/Internal State Register (CFISREG) 07H being all high or Current Transfer Count Register (CTCREG) 00–01H is zero, which is indicated by the Count to Zero (CTZ) bit of the Status Register (STATREG) 04H. Idle State Commands The Idle State Commands can be issued to the device only when the device is disconnected from the SCSI bus. If these commands are issued to the device when it is logically connected to the SCSI bus, the commands are ignored, and the device will generate an illegal command interrupt and clear the Command Register (CMDREG) 03H. AMD Select without ATN Steps Command (Command Code 41H/C1H) The Select without ATN Steps Command is used by the initiator to select a target. When this command is issued the device arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the target device and transfers the Command Descriptor Block (CDB). Before issuing this command the SCSI Timeout Register (STIMREG) 05H, the Control Register One (CNTLREG1) 08H and the SCSI Destination ID Register (SDIDREG) 04H must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) 00H–01H must be set to the total length of the command. If DMA is not enabled, the data must be loaded into the FIFO before issuing this command. This command will be terminated early if the SCSI Timeout Register times out or if the target does not go to the Command Phase following the Selection Phase or if the target exits the Command Phase early. Select with ATN Steps Command (Command Code 42H/C2H) The Select with ATN Steps Command is used by the initiator to select a target. When this command is issued the device arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the target device with the ATN signal asserted and transfers the Command Descriptor Block (CDB) and a one byte message. Before issuing this command the SCSI Timeout Register (STIMREG) 05H, the Control Register One (CNTLREG1) 08H and the SCSI Destination ID Register (SDIDREG) 04H must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) 00H–01H must be set to the total length of the command. If DMA is not enabled, the data must be loaded into the FIFO before issuing this command. This command will be terminated early in the following situations: ■ The SCSI Timeout Register times out Reselect Steps Command (Command Code 40H/C0H) ■ The target does not go to the Message Out Phase following the Selection Phase The Reselect Steps Command is used by the target device to reselect an initiator device. When this command is issued the device arbitrates for the control of the SCSI bus. If the device wins arbitration, it reselects the initiator device and transfers a single byte identify message. Before issuing this command the SCSI Timeout Register (STIMREG) 05H, the Control Register One (CNTLREG1) 08H and the SCSI Destination ID Register (SDIDREG) 04H must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) 00H–01H must be set to one. If DMA is not enabled, the single byte identify message must be loaded into the FIFO before issuing this command. This command will be terminated early if the SCSI Timeout Register times out. This command also resets the Internal State Register (ISREG) 06H. ■ The target exits the Message Phase early ■ The target does not go to the Command Phase following the Selection Phase ■ The target exits the Command Phase early. Select with ANT and Stop Steps Command (Command Code 43H/C3H) The Select with ATN and Stop Steps Command is used by the initiator to select a target. When this command is issued the device arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the target device with the ATN signal asserted and transfers the Command Descriptor Block (CDB) and stops after one message byte is sent, but the ATN signal is not Am53C94/Am53C96 37 AMD PRELIMINARY deasserted at the end of the command which allows the initiator to send other messages after the ID message is sent out. Before issuing this command the SCSI Timeout Register (STIMREG) 05H, the Control Register One (CNTLREG1) 08H and the SCSI Destination ID Register (SDIDREG) 04H must be set to the proper values. This command will be terminated early if the SCSI Timeout Register times out or if the target does not go to the Message Out Phase following the Selection Phase. command. This command will be terminated early in the following situations: Enable Selection/Reselection Command (Command Code 44H/C4H) ■ The target exits the Command Phase early. The Enable Selection/Reselection Command is used by the target to respond to a bus-initiated reselection. Upon disconnecting from the bus the Selection/Reselection circuit is automatically disabled by device. This circuit has to be enabled for the device to respond to subsequent reselection attempts and the Enable Selection/ Reselection Command is issued to do that. This command is normally issued within 250 ms (select/reselect timeout) after the device disconnects from the bus. If DMA is enabled the device loads the received data to the buffer memory, but if the DMA is disabled, the received data stays in the FIFO. General Commands Disable Selection/Reselection Command (Command Code 45H/C5H) The Disable Selection/Reselection Command is used by the target to disable response to a bus-initiated reselection. When this command is issued before a bus initiated selection or reselection is initiated, it resets the internal mode bits previously set by the Enable Selection/Reselection Command. The device also generates a function complete interrupt to the processor. If however, this command is issued after a bus initiated selection/reselection has already begun the command is ignored since the Command Register is held reset and all incoming commands are ignored. The device generates a selected or reselected interrupt when the sequence is complete. Select with ATN3 Steps Command (Command Code 46H/C6H) The Select with ATN3 Steps Command is used by the initiator to select a target. This command is similar to the Select with ATN Steps Command, except that it sends exactly three message bytes. When this command is issued the device arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the target device with the ATN signal asserted and transfers the Command Descriptor Block (CDB) and three message bytes. Before issuing this command the SCSI Timeout Register (STIMREG) 05H, the Control Register One (CNTLREG1) 08H and the SCSI Destination ID Register (SDIDREG) 04H must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) 00H–01H must be set to the total length of the command. If DMA is not enabled, the data must be loaded into the FIFO before issuing this 38 ■ The SCSI Timeout Register times out ■ The target does not go to the Message Out Phase following the Selection Phase ■ The target exits the Message Phase early ■ The target does not go to the Command Phase following the Selection Phase No Operation Command (Command Code 00H/80H) The No Operation Command is used to perform no operation and no interrupt is generated at the end of this command. This command is issued after the Reset Device Command to enable the Command Register. A No Operation Command in the DMA mode may be used to verify the contents of the Start Transfer Count Register (STCREG) 00H – 01H. After the STCREG is loaded with the transfer count and a No Operation Command is issued, reading the Current Transfer Count Register (CTCREG) 00H–01H will give the transfer count value. Clear FIFO Command (Command Code 01H/81H) The Clear FIFO Command is used to initialize the FIFO to the empty condition. The Current FIFO Register (CFISREG) 07H reflects the empty FIFO status and the bottom of the FIFO is set to zero. No interrupt is generated at the end of this command. Reset Device Command (Command Code 02H/82H) The Reset Device Command immediately stops any device operation and resets all the functions of the device. It returns the device to the disconnected state and it also generates a hard reset. The Reset Device Command remains on the top of the Command Register FIFO holding the device in the reset state until the No Operation Command is loaded. The No Operation command serves to enable the Command Register. Reset SCSI Bus Command (Command Code 03H/83H) The Reset SCSI Bus Command is used to assert the RSTC signal for approximately 25 ms. This command causes the device to go to the disconnected state. No interrupt is generated upon command completion. A SCSI reset interrupt is however generated upon command completion if the interrupt is not disabled in the Control Register One (CNTLREG1) 08H. Am53C94/Am53C96 PRELIMINARY AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Ambient Temperature Under Bias . –55°C to +125°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +7.0 V DC Voltage Applied to Any Pin . –0.5 to (VDD +0.5) V Input Static Discharge Protection . . 4000 V pin to pin (Human body model: 100 pF at 1.5K Ω) Commercial Devices Ambient Temperature (TA) . . . . . . . 0°C to +70°C Supply Voltage (VDD) . . . . . . . +4.75 V to +5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Am53C94/Am53C96 39 AMD PRELIMINARY DC OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Pin Names Test Conditions Max Unit IDDS Static Supply Current VDD MAX 4.0 mA IDDD Dynamic Supply Current VDD MAX 35 mA – 100 +100 10 mA pF ILU Latch Up Current C Capacitance SCSI Pins All I/O All Pins VLU ≤ 10 V VIH Input High Voltage All SCSI Inputs 2.0 VDD + 0.5 V VIL Input Low Voltage All SCSI Inputs VSS – 0.5 0.8 V VIHST Input Hysterisis All SCSI Inputs 4.75 V < VDD < 5.25 V 300 VOH Output High Voltage SD 7–0, SDP IOH = – 2 mA 2.4 VDD V IOL= 4 mA VSOL1 SCSI Output Low Voltage SD 7–0, SDP VSOL2 SCSI Output Low Voltage SDC 7–0, SDCP, IOL= 48 mA MSG, C/D, I/O, ATN, RSTC, SELC, BSYC, ACKC and REQC IIL Input Low Leakage IIH IOZ mV VSS 0.4 V VSS 0.5 V 0.0 V < VIN < 2.7 V –10 +10 µA Input High Leakage 2.7 V < VIN < VDD –10 +10 µA High Impedance Leakage 0 V < VOUT < VDD –10 +10 µA 2.0 VDD + 0.5 V VSS – 0.5 0.8 V Bidirectional Pins VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage DMA 15–0, DMAP 1–0 and AD 7–0 IOH = – 2 mA 2.4 VDD V VOL Output Low Voltage DMA 15–0, DMAP 1–0 and AD 7–0 IOL= 4 mA VSS 0.4 V IIL Input Low Leakage DMA 15–0, DMAP 1–0 and AD 7–0 VIN = VIL – 400 +10 µA IIH Input High Leakage DMA 15–0, DMAP 1–0 and AD 7–0 VIN = VIH –10 +10 µA IOZ High Impedance Leakage 0 V < VOUT < VDD –100 400 µA Output Pins VOH Output High Voltage 40 Min VOL Output Low Voltage IOZ High Impedance Leakage DREQ, ISEL, TSEL IOH = – 2 mA 2.4 VDD V DREQ, ISEL, TSEL IOL= 4 mA VSS 0.4 V 0 V < VOUT < VDD –10 +10 µA Am53C94/Am53C96 PRELIMINARY AMD DC OPERATING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Pin Names Test Conditions Min Max Unit Input Pins VIH Input High Voltage A 3-0, CS, RD. WR, DMAWR, CLK, BUSMD 1-0, DACK, RESET, and DFMODE 2.0 VCC + 0.5 V VIL Input Low Voltage A 3-0, CS, RD. WR, DMAWR, CLK, BUSMD 1-0, DACK, RESET, and DFMODE VSS + 0.5 0.8 V IIL Input Low Leakage A 3-0, CS, RD. WR, DMAWR, CLK, BUSMD 1-0, DACK, RESET, and DFMODE VIN = VIL –10 +10 µA IIH Input High Voltage A 3-0, CS, RD. WR, DMAWR, CLK, BUSMD 1-0, DACK, RESET, and DFMODE VIN = VIH –10 +10 µA SWITCHING TEST CIRCUIT IOL From Output Under Test VT CL 0V IOH 16505C-34 SWITCHING TEST WAVEFORMS 3.0 V All Inputs 1.5 V 0.0 V 2.0 V 0.8 V VOH 1.5 V VOL True Data Outputs AD 7–0, DMA 15–0, DMAP1–0 VOH –0.3 V 1.5 V VOL +0.3 V Hi-Z Outputs AD 7–0, DMA 15–0, DMAP1–0 1.5 V All Open Drain Outputs 0.8 V VOL VOH All Other Outputs 1.5 V VOL Am53C94/Am53C96 16505C-35 41 AMD PRELIMINARY KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 42 Am53C94/Am53C96 PRELIMINARY AMD CLK 1 4 2 3 Clock Input No. Parameter Symbol 1 2 tPWL tCP 3 tL 4 tPWH Parameter Description Test Conditions 16505C-36 Min Max Unit Clock Pulse Width Low Clock period 14.58 40 100 ns ns Synchronization latency (parameter 2 + parameter 1) Clock Pulse Width High 54.58 185.42 ns 14.58 ns Note: Clock Frequency Range = 10 to 25 MHz for Asynchronous SCSI Bus = 12 to 25 MHz for Synchronous SCSI Bus RESET 5 Reset Input No. Parameter Symbol 5 tPWH Parameter Description Test Conditions Reset Pulse Width High 16505C-37 Min 500 Max Unit ns Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 43 AMD PRELIMINARY 7 INT RD 6 8 9 16505C-38 Interrupt Output No. Parameter Symbol 6 7 8 tS tPD tPWL INT to RD Set Up Time RD to INT Delay RD Pulse Width Low 9 tPD RD Parameter Description to INT Test Conditions Delay Min 0 0 50 tL – tPD Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). 44 Am53C94/Am53C96 Max Unit 100 ns ns ns ns PRELIMINARY AMD A3–0 11 10 10 19 11 19 23 CS 16 24 RD 12 20 14 21 25 WR 15 17 18 13 22 26 AD 7–0 DMA 7–0 DMAP 0 Register Read/Write with Non-Multiplexed Address Data Bus 16505C-39 No. Parameter Symbol 10 tS Address to CS Set Up Time 0 ns 11 tH Address to CS Hold Time 50 ns 12 tS CS Set Up Time 0 ns 13 14 tPD tPWL CS to Data Valid Delay RD Pulse Width Low 15 tPD RD 16 17 18 19 tH tZ tH tPWH RD to CS Hold Time RD to Data High Impedance RD to Data Hold Time CS Pulse Width High 2 40 ns ns ns ns 20 21 tS tPWL CS to WR Set Up Time WR Pulse Width Low 0 40 ns ns 22 tS Data to WR Set Up Time 15 ns 23 tH WR Hold Time 0 ns 24 25 tS tPWH WR to CS Set Up Time WR Pulse Width High 60 60 ns ns 26 tH Data to WR 0 ns Parameter Description to RD Test Conditions Min ns ns 50 ns 0 40 Hold Time Unit 90 50 to Data Valid Delay to CS Max Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 45 AMD PRELIMINARY 27 27 AL 28 29 28 30 42 30 Address AD 7–0 29 Data 31 35 33 Address Data 38 41 43 CS 32 34 36 37 RD 39 40 44 WR 16506C-40 Register Read/Write with Multiplexed Address Data Bus No. Parameter Symbol 27 tPWH 28 29 Parameter Description Test Conditions Min Unit ALE Pulse Width High 20 ns tS Address to ALE Set Up Time 10 ns tH Address to ALE Hold Time 10 ns 30 tS ALE to CS Set Up Time 10 31 tPD CS to Data Valid Delay 32 tS CS to RD 33 34 35 tPD tPWL tH 36 37 tH tZ RD RD to CS Hold Time to Data High Impedance 0 38 tS CS to ALE Set Up Time 50 ns 39 40 tS tPWL CS to WR Set Up Time WR Pulse Width Low 0 40 ns ns 41 tS Data to WR 15 ns Set Up Time RD to Data Valid Delay RD Pulse Width Low RD to Data Hold Time Set Up Time ns 90 0 ns ns 50 50 2 40 ns ns ns ns ns 42 tS WR 50 ns 43 tH Data to WR Hold Time 0 ns 44 tH WR Hold Time 0 ns to ALE to CS Set Up Time Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). 46 Max Am53C94/Am53C96 PRELIMINARY AMD DREQ 45 49 45 49 46 50 DACK 47 47 51 51 54 57 55 DMAWR 52 58 56 53 48 59 DMA 15–0 DMAP 1–0 16506C-41 DMA Write without Byte Control DREQ 49 45 45 46 49 50 DACK 51 47 67 47 51 52 48 53 DMA 15–0 DMAP 1–0 16506C-42 DMA Read without Byte Control No. Parameter Symbol 45 tPD DACK 46 47 tP tPWL DACK to DACK period DACK Pulse Width Low 48 tPD DACK to Data Valid Delay 41 ns 49 tPD DACK to DREQ 40 ns 50 51 52 53 tP tPWH tZ tH 54 55 tS tPWL 56 tS 57 58 tH tPWH 59 tH Parameter Description to DREQ Test Conditions Min Valid Delay Unit 38 ns 100 60 Valid Delay DACK to DACK period DACK Pulse Width High DACK to Data High Impedance DACK to Data Hold Time Max ns ns 2 ns ns ns ns DACK to DMAWR Set Up Time DMAWR Pulse Width Low 0 50 ns ns Data to DMAWR 15 ns DMAWR to DACK Hold Time DMAWR Pulse Width High 0 40 ns ns Data to DMAWR 0 ns Set Up Time Hold Time t3+50–t51 12 40 Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 47 AMD PRELIMINARY DREQ 60 60 71 71 61 72 DACK 61 73 62 62 73 AS 0 BHE 79 75 74 76 78 DMAWR 77 80 81 DMA 15–0 DMAP 1–0 16506C-52 DMA Write with Byte Control DREQ 71 60 71 60 61 72 DACK 61 73 62 62 73 AS 0 BHE 64 67 68 63 DMARD 65 69 66 66 70 69 70 DMA 15–0 DMAP 1–0 16506C-53 DMA Read with Byte Control 48 Am53C94/Am53C96 PRELIMINARY No. Parameter Symbol 60 tPD DACK 61 62 tP tPWL DACK to DACK period DACK Pulse Width Low 63 tS 64 65 tS tPWL BHE, AS0 to DMARD Set Up Time DMARD Pulse Width Low 66 tPD DMARD 67 tH BHE, AS0 to DMARD 68 69 70 tH tZ tH DMARD DMARD DMARD 71 tPD DACK 72 73 tP tPWH 74 tS 75 76 tS tPWL 77 Parameter Description DACK to DREQ Test Conditions AMD Min Valid Delay to DMARD ns 0 ns 20 60 ns ns 51 20 to DACK Hold Time to Data High Impedance to Data Hold Time ns ns 0 40 ns ns ns 40 ns 2 Valid Delay DACK to DACK period DACK Pulse Width High 38 ns ns to Data Valid Delay to DREQ Unit 100 60 Set Up Time Hold Time Max 100 12 ns ns 0 ns BHE, AS0 to DMAWR Set Up Time DMAWR Pulse Width Low 20 50 ns ns tS Data to DMAWR 15 ns 78 tH BHE, AS0 to DMAWR Hold Time 20 ns 79 80 tH tPWH DMAWR to DACK Hold Time DMAWR Pulse Width High 0 40 ns ns 81 tH Data to DMAWR 0 ns DACK to DMAWR Set Up Time Set Up Time Hold Time Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 49 AMD PRELIMINARY DREQ 82 93 94 83 DACK 90 87 DMARD 84 85 88 89 91 92 86 DMA 15–0 DMAP 1–0 16506C-43 Burst DMA Read without Byte Control DREQ 93 94 82 83 DACK 101 97 DMAWR 95 96 98 99 102 100 DMA 15–0 DMAP 1–0 16506C-44 Burst DMA Write without Byte Control 50 Am53C94/Am53C96 PRELIMINARY No. Parameter Symbol 82 83 tPD tPWL 84 tS DACK 85 tP DMARD 86 87 88 tPD tPWH tPWL DMARD to Data Valid Delay DMARD Pulse Width High DMARD Pulse Width Low 89 90 91 92 tP tPD tZ tH DMARD DMARD DMARD DMARD 93 94 tPD tPWH DACK to DREQ Valid Delay DACK Pulse Width High 95 tS DACK 96 97 98 tP tPWH tPWL DMAWR to DMAWR period DMAWR Pulse Width High DMAWR Pulse Width Low 99 tP DMAWR 100 tS Data to DMAWR 101 tPD DMAWR 102 tH Data to DMAWR Parameter Description Test Conditions DACK to DREQ Valid Delay DACK Pulse Width Low to DMARD Set Up Time to DMARD period to DMARD period to DREQ Valid Delay to Data High Impedance to Data Hold Time to DMAWR Set Up Time to DMAWR period Set Up Time to DREQ AMD Min Max Unit 45 100 ns ns 0 ns 130 60 70 t3 + 50 140 50 2 40 60 ns ns ns ns ns ns ns ns ns 0 ns 160 60 100 ns ns ns t3 + 50 ns 15 ns Valid Delay Hold Time ns 70 140 0 ns ns Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 51 AMD PRELIMINARY DREQ 103 116 117 104 DACK AS 0 BHE 105 111 109 113 DMARD 106 107 108 110 112 114 115 DMA 15–0 DMAP 1–0 16506C-45 Burst DMA Read with Byte Control DREQ 103 116 117 104 DACK AS 0 BHE 119 123 121 125 DMAWR 118 120 122 124 126 127 DMA 15–0 DMAP 1–0 16506C-46 Burst DMA Write with Byte Control 52 Am53C94/Am53C96 PRELIMINARY No. Parameter Symbol Parameter Description 103 104 tPD tPWL DACK to DREQ Valid Delay DACK Pulse Width Low 105 tS BHE, AS0 to DMARD 106 tS DACK 107 tP DMARD 108 109 110 tPD tPWH tPWL 111 to DMARD Test Conditions AMD Max Unit 45 100 ns ns 20 ns Set Up Time 0 ns period 130 ns Set Up Time to DMARD Min DMARD to Data Valid Delay DMARD Pulse Width High DMARD Pulse Width Low 60 70 ns ns ns tH BHE, AS0 to DMARD 20 ns 112 113 114 115 tP tPD tZ tH DMARD DMARD DMARD DMARD t3 + 50 ns ns ns ns 116 117 tPD tPWH DACK to DREQ Valid Delay DACK Pulse Width High 60 ns ns 118 tS DACK 0 ns 119 tS BHE, AS0 to DMAWR 20 ns 120 121 122 tP tPWH tPWL 160 60 100 ns ns ns 123 tH BHE, AS0 to DMAWR Hold Time 20 ns 124 tP DMAWR to DMAWR period t3 + 50 ns 125 tPD DMAWR to DREQ 126 tH Data to DMAWR Hold Time 0 ns 127 tS Data to DMAWR Set Up Time 15 ns Hold Time to DMARD period to DREQ Valid Delay to Data High Impedance to Data Hold Time to DMAWR Set Up Time Set Up Time DMAWR to DMAWR period DMAWR Pulse Width High DMAWR Pulse Width Low 70 140 50 2 50 Valid Delay 140 ns Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 53 AMD PRELIMINARY SDC 7–0 SDCP 128 129 ACKC 130 131 REQ 16505C-47 Asynchronous Initiator Send No. Parameter Symbol 128 tS Data to ACKC 129 tPD REQ to Data Delay 80 ns 130 tPD REQ to ACKC Delay 46 ns 131 tPD REQ to ACKC Delay 55 ns Parameter Description Test Conditions Set Up Time Min Max 55 Unit ns ACKC 132 133 REQ 16505C-48 Asynchronous Initiator Receive No. Parameter Symbol 132 tPD REQ to ACKC 133 tPD REQ to ACKC Parameter Description Test Conditions Min Max Unit Delay 43 ns Delay 47 ns Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). 54 Am53C94/Am53C96 PRELIMINARY AMD SDC 7–0 SDCP 134 135 REQC 136 137 ACK 16505C-49 Asynchronous Target Send No. Parameter Symbol 134 tS Data to REQC Parameter Description Test Conditions Set Up Time Min Max 55 Unit ns 135 tPD ACK to Data Delay 78 ns 136 tPD ACK to REQC Delay 60 ns 137 tPD ACK to REQC Delay 45 ns REQC 138 139 ACK 16505C-50 Asynchronous Target Receive No. Parameter Symbol 138 tPD ACK to REQC 139 tPD ACK to REQC Parameter Description Test Conditions Min Max Unit Delay 60 ns Delay 45 ns Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). Am53C94/Am53C96 55 AMD PRELIMINARY CLK 140 140 SDC 7–0 SDCP 142 141 142 143 REQC ACKC 16505C-51 Synchronous Initiator Target Transmit No. Parameter Symbol 140 141 tPD tS CLK to Data Delay ACKC or REQC to Data Set Up Time 142 tPD CLK to ACKC or REQC 143 tPD CLK to ACKC or REQC Parameter Description Test Conditions Min Max Unit 15* 55 90 ns ns Delay 13* 68 ns Delay 17 70 ns * The minimum values have a wide range since they depend on the Synchronization latency. The synchronization latency, in turn, depends on the operating frequency of the device. Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B). 56 Am53C94/Am53C96 PRELIMINARY AMD APPENDIX A Pin Connection Cross Reference for Am53C94 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 AMD DMAP0 VSS DMA8 DMA9 DMA10 DMA11 DMA12 DMA13 DMA14 DMA15 DMAP1 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SDP VDD VSS SDC0 SDC1 SDC2 SDC3 VSS SDC4 SDC5 SDC6 SDC7 SDCP VSS SELC BSYC REQC ACKC VSS MSG C/D I/O ATN NCR DBP0 VSS DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DBP1 SDI0/ SDI1/ SDI2/ SDI3/ SDI4/ SDI5/ SDI6/ SDI7/ SDIP/ VDD VSS SDO0/ SDO1/ SDO2/ SDO3/ VSS SDO4/ SDO5/ SDO6/ SDO7/ SDOP/ VSS SELO/ BSYO/ REQO/ ACKO/ VSS MSGIO/ C/DIO I/OIO ATNIO/ Pin# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Am53C94/Am53C96 AMD RSTC VSS SEL BSY REQ ACK RST BUSMD 1 BUSMD 0 INT RESET WR RD CS ASO [AO] BHE [A1] DMARD [A2] ALE [A3] CLK VDD AD0 AD1 AD2 AD3 VSS AD4 AD5 AD6 AD7 DREQ DACK DMAWR VSS VSS DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 NCR RSTO/ VSS SELI/ BSYI/ REQI/ ACKI/ RSTI/ MODE 1 MODE 0 INT/ RESET WR/ RD/ CS/ A0–SA0 A1–BHE A2–DBRD/ A3–ALE CLK VDD PAD0 PAD1 PAD2 PAD3 VSS PAD4 PAD5 PAD6 PAD7 DREQ DACK/ DBWR/ VSS VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 57 AMD PRELIMINARY APPENDIX A Pin Connection Cross Reference for Am53C96 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 58 AMD DACK DMAWR NC ISEL VSS TSEL VSS DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMAP0 VSS VSS DMA8 DMA9 DMA10 DMA11 DMA12 DMA13 DMA14 DMA15 DMAP1 NC SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SDP VDD NC VSS VSS SDC0 SDC1 SDC2 SDC3 VSS VSS SDC4 SDC5 SDC6 NCR DACK DBWR/ NC IGS VSS TGS VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DBP0 VSS VSS DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DBPI NC SDI0/ SDI1/ SDI2/ SDI3/ SDI4/ SDI5/ SDI6/ SDI7/ SDIP/ VDD NC VSS VSS SDO0/ SDO1/ SDO2/ SDO3/ VSS VSS SDO4/ SDO5/ SDO6/ Pin# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Am53C94/Am53C96 AMD SDC 7 SDC P NC VSS VSS SELC BSYC REQC ACKC VSS VSS MSG C/D I/O ATN RSTC VSS VSS SEL BSY REQ ACK RST BUSMD 1 BUSMD 0 INT RESET NC WR RD CS ASO [A0] BHE [A1] DMARD [A2] ALE [A3] CLK DFMODE VDD NC AD0 AD1 AD2 AD3 VSS VSS AD4 AD5 AD6 AD7 DREQ NCR SDO7/ SDOP/ NC VSS VSS SELO/ BSYO/ REQO/ ACKO/ VSS VSS MSGIO/ C/DIO I/OIO ATNIO/ RSTO/ VSS VSS SELI/ BSYI/ REQI/ ACKI/ RSTI/ MODE 1 MODE 0 INT/ RESET NC WR/ RD/ CS/ A0–SAO A1–BHE A2–DBRD/ A3–ALE CLK DIFFM/ VDD NC PAD0 PAD1 PAD2 PAD3 VSS VSS PAD4 PAD5 PAD6 PAD7 DREQ PRELIMINARY AMD APPENDIX B AMD/NCR Timing Parameters Cross Reference NCR Symbol tCH tCL tCP tCS tRST tIR tRD tRI tICY tRDP1 tRDP2 tRDP3 tRDP4 tRDP5 tRDP6 tRDP7 tRDP8 tRDP9 (max) tRDP9 (min) tRDP10 tRDP11 tRDP12 tRDP13 tRDP14 tRDP15 tRDP16 tRMP1 tRMP2 tRMP3 tRMP4 tRMP5 tRMP6 tRMP7 tRMP8 tRMP9 tRMP10 tRMP11 (max) tRMP11 (min) tRMP12 tRMP13 tRMP14 tRMP15 tRMP16 tRMP17 tDNB1 tDNB2 tDNB3 tDNB4 AMD Parameter # 4 1 2 3 5 6 8 7 9 10 11 19 13 12 14 16 15 17 18 20 21 23 22 26 24 25 28 29 27 30 31 38 32 34 36 33 37 35 39 40 44 41 43 42 45 49 51 47 NCR Symbol tDNB5 tDNB6 tDNB7 tDNB8 (max) tDNB8 (min) tDNB9 tDNB10 tDNB11 tDNB12 tDNB13 tDNB14 tDBC1 tDBC2 tDBC3 tDBC4 tDBC5 tDBC6 tDBC7 tDBC8 tDBC9 tDBC10 tDBC11 tDBC12 tDBC13 (max) tDBC13 (min) tDBC14 tDBC15 tDBC16 tDBC17 tDBC18 tDBC19 tDBC20 tDBC21 tDAN1 tDAN2 tDAN3 tDAN4 tDAN5 tDAN6 tDAN7 tDAN8 tDAN9 tDAN10 (max) tDAN10 (min) tDAN11 tDAN12 tDAN13 tDAN14 AMD Parameter # 46 50 48 52 53 54 55 57 56 59 58 60 71 73 62 61 72 64 67 63 65 68 66 69 70 75 78 74 76 79 77 81 80 93 82 94 83 90 84 88 87 86 91 92 85 89 101 95 Am53C94/Am53C96 NCR Symbol tDAN15 tDAN16 tDAN17 tDAN18 tDAN19 tDAN20 tDAB1 tDAB2 tDAB3 tDAB4 tDAB5 tDAB6 tDAB7 tDAB8 tDAB9 tDAB10 tDAB11 tDAB12 (max) tDAB12 (min) tDAB13 tDAB14 tDAB15 tDAB16 tDAB17 tDAB18 tDAB19 tDAB20 tDAB21 tDAB22 tDAB23 tDAB24 tLAXDA tLAXAH tLAXRD tLAXAL tLARAH tLARAL tTAXDR tTAXRH tTAXAD tTAXRL tTARRH tTARRL tSXD tSXRAL tSXRAH tSXDSU AMD Parameter # 98 97 100 102 96 99 116 103 117 104 113 105 111 106 110 109 108 114 115 107 112 125 119 123 118 122 121 127 126 120 124 128 130 129 131 132 133 134 136 135 137 138 139 140 142 143 141 59 AMD PRELIMINARY PHYSICAL DIMENSIONS* PL 084 Plastic Leaded Chip Carrier (measured in inches) .042 .048 .020 MIN .050 REF .042 .056 .025 R .045 .013 .021 .026 .032 1.185 1.150 1.195 1.156 1.000 1.090 REF 1.130 .007 .013 1.150 1.156 1.185 1.195 .165 .180 TOP VIEW * For reference only. BSC is an ANSI standard for Basic Space Centering. 60 Am53C94/Am53C96 .090 .130 SIDE VIEW 09980B CG08 PL 084 8/14/92 c dc PRELIMINARY AMD PHYSICAL DIMENSIONS* PQR100 Plastic Quad Flatpack Trimmed and Formed (measured in millimeters) PQJ 100 (Plastic Quad Flat Pack; Trimmed and Formed) (measured in millimeters) 17.10 13.90 12.35 REF 17.30 14.10 0.22 0.38 18.85 REF 19.90 20.10 23.00 23.40 0.65 REF Pin 1 I.D. TOP VIEW 2.60 3.35 MAX 3.00 0.70 0.90 0.25 MIN SIDE VIEW Am53C94/Am53C96 15590D BX 45 9/6/91 SG 61 AMD PRELIMINARY PHYSICAL DIMENSIONS* PQR100 Molded Carrier Ring Plastic Quad Flatpack (measured in millimeters) 35.87 36.13 31.37 35.50 35.90 31.63 25.15 25.20 BSC 25.25 27.87 28.13 22.15 13.80 22.25 14.10 50 30 35.50 27.87 22.15 35.90 28.13 22.25 35.87 31.37 25.15 19.80 36.13 31.63 25.25 20.10 Pin 1 I.D. 80 100 0.22 0.38 TOP VIEW .65 NOM .45 Typ .65 Pitch 2.00 4.80 1.80 .65 Typ SIDE VIEW CB 48 6/25/92 SG 62 Am53C94/Am53C96 PRELIMINARY AMD Trademarks Copyright 1993 Advanced Micro Devices, All rights reserved. GLITCH EATER is a trademark of Advanced Micro Devices, Inc. AMD and Am386 are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am53C94/Am53C96 63