FUJITSU MB86606APMT2

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-22420-3E
ASSP Communication Control
CMOS
FAST-20 SCSI Protocol Controller
MB86606A
■ DESCRIPTION
The MB86606A is an intelligent SCSI protocol controller (SPC) conforming to the ANSI (FAST-20) standard
and integrating a PCI local bus interface function. The specification of SCSI controller block is based on the
MB86605’s one which is a Wide SCSI protocol controller, but the device functions/features to achieve the
FAST-20 data transfer rate of maximum 40 Mbyte/sec at 16-bit FAST-20 SCSI, such as the size of internal data
register FIFO, are larged on the MB86606A. As for the SCSI bus pins, a totem pole type single-ended driver/
receiver is incorporated in the device so that it can drive the SCSI bus directly. Furthermore, the MB86606A is
capable of connecting the external differential type driver/receiver.
The SCSI bus sequence is controlled by commands issued via the system interface. So, it supports sequential
commands that perform the phase-to-phase sequences to reduce the overhead of system’s sequence
operations.
As another key feature to reduce the system overhead, the device has a 2 Kbytes user program memory to store
the user program with the commands. Due to this, all the SCSI bus sequences including the data transfer can
be performed automatically.
As the system interface block, it incorporates a 32-bit PCI local bus interface that easily realizes the SCSI
interface on the motherboards of PCI bus based PCs and WSs, in addition to a 16-bit separate MPU and DMA
buses. For the on-chip PCI bus interface, the MB86606A also incorporates a 32-bit DMA controller that is capable
of supporting the scatter-gather function so that the data transfers can be controlled by both user program and
the host system.
The device is fabricated by the advanced CMOS process and is housed in an 144-pin plastic Quad Flat Package
(Suffix: -PMT2).
■ PACKAGE
144 pin plastic LQFP
(FPT-144P-M08)
MB86606A
■ FEATURES
SCSI Protocol Controller Block:
• Operable as initiator and target
• WIDE and FAST-20 data transfers
Synchronous transfer (max. 40 Mbytes/s: Up to 256 offset values can be set.)
Asynchronous transfer (max. 10 Mbytes/s)
• 512-byte FIFO register for data phase
• Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases
(MCS Buffers)
• On-chip totem pole type SCSI single-ended driver/receiver
• Supports external SCSI differential driver/receiver connectivity
• On-chip memory to store transfer parameters for each ID (up to 15 connected devices)
• On-chip 16-bit transfer block counter and 24-bit transfer byte counter
Maximum Transfer Byte : 1 Tbyte at fixed length data transfer
: 16 Mbyte at variable length data transfer
• Supports various control commands:
Sequential Commands
: can perform phase-to-phase sequential operations (functions only when issuing
from a system side.)
Discrete Commands
: can perform any desired sequence to program in the user program memory
Data Transfer Commands : can program the transfer data length at the user program operation.
• On-chip direct control register for SCAM (SCSI Configured AutoMatically) Level-1 Protocol
• Supports Multi Selection/Reselection Responses
Selection and Reselection responses can be done to plural IDs.
• On-chip 2 Kbyte User Program Memory
Two Modes : 2 Kbyte × 1 bank and 1 Kbyte × 2 banks
(While 1 Kbyte × 2 banks are selected, host system can access another bank even if the user
program is executing.)
Access to User program : Burst transfer via I/O access port
: Direct access to 2 Kbyte user program memory (only for PCI bus I/F mode)
• User Selectable Interrupt Report
Unnecessary interrupt reports can be disabled depending on user’s applications to reduce a system ISR
overhead.
• Two automatic receive modes
Initiator : can automatically receive information for new phase to which target switched
Target : can automatically receive attention condition generated by initiator
• Automatic selection/reselection
For command issues
: automatically performs to receive MSG/CMD to the selection/reselection
request from partner device
For user program operation : pauses the program currently executed and automatically jumps to the
specified selection /reselection routine in response to the selection/reselection
request from partner device.
• Operation Clock
System Clock: Max. 40 MHz
Internal Processor Operating Clock: Max. 20 MHz
(Continued)
2
MB86606A
(Continued)
System Interface Block:
• Separate MPU and DMA buses called 16-bit Bus Mode
Directly connectable to 68-series or 80-series MPU
Two transfer modes (Program transfer and DMA transfer (slave mode))
• PCI Bus Interface Mode
Directly connectable to the 32-bit PCI local bus.
On-chip 32-bit DMAC for PCI bus master
Supports the PERR&SERR function
Supports the INTA# Interrupt Signals
Max. 64 bytes burst transfer
PCI system clock: Max. 33 MHz
• Data Bus Parity and Address Bus Parity (only for PCI bus interface mode) generation/check function
Others
• Compact 144-Pin Plastic Quad Flat Package (LQFP, Package Suffix: –PMT2)
• Pin compatible with MB86605
• Supply Voltage: 5V ± 5%
3
D2
D1
D0
V SS
LDP
UDS/BHE
V DD
LDS/WR
V SS
R/W/RD
CS1
CS0
V DD
INT
A4
A3
V SS
SCLK
A2
A1
A0
V SS
MODE1
MODE0
S/DSEL
TARG
V DD
INIT
SELOE
V SS
RSTOE
BSYOE
DBOE11
DBOE10
DBOE9
DBOE8
4
(FPT-144P-M08)
70
65
60
55
50
45
1
40
DMD9
V SS
DMD8
DMD7
DMD6
V DD
DMD5
V SS
DMD4
DMD3
DMD2
V SS
DMD1
DMD0
LDMDP
V SS
UDP
V DD
D15
D14
V SS
D13
D12
D11
V SS
D10
D9
D8
D7
V SS
V DD
D6
D5
D4
V SS
D3
110
115
120
125
130
135
140
144
DMD10
DMD11
DMD12
DMD13
V SS
DMD14
DMD15
V DD
UDMDP
DMR/W/DMRD
V SS
DMLDS/DMWR
DMUDS/DMBHE
V DD
DREQ
DACK
V SS
RESET
TP
DMA0
DBOE12
DBOE13
V SS
DBOE14
DBOE15
UDBOEP
DBOE0
DBOE1
V DD
DBOE2
DBOE3
DBOE4
V SS
DBOE5
DBOE6
DBOE7
MB86606A
■ PIN ASSIGNMENT
• 16-Bit Bus Mode
(TOP VIEW)
5
105
INDEX
10
100
15
95
20
90
25
85
30
80
35
75
LDBOEP
V DD
DB12
DB13
DB14
DB15
V SS
UDBP
DB0
DB1
V SS
DB2
DB3
DB4
DB5
V SS
DB6
DB7
LDBP
ATN
V SS
BSY
ACK
RST
MSG
SEL
V SS
C/D
REQ
I/O
DB8
V SS
DB9
DB10
DB11
V DD
MB86606A
• PCI Bus Interface Mode
110
115
120
125
130
135
1
105
5
INDEX
100
10
95
15
90
20
85
25
80
30
75
70
65
60
55
50
45
40
35
LDBOEP
V DD
DB12
DB13
DB14
DB15
V SS
UDBP
DB0
DB1
V SS
DB2
DB3
DB4
DB5
V SS
DB6
DB7
LDBP
ATN
V SS
BSY
ACK
RST
MSG
SEL
V SS
C/D
REQ
I/O
DB8
V SS
DB9
DB10
DB11
V DD
C/BE0
AD7
AD6
V SS
AD5
AD4
V DD
AD3
V SS
AD2
AD1
AD0
V DD
INT
PO1
PO0
V SS
SCLK
PI1
PI0
N. C.
V SS
MODE1
MODE0
S/DSEL
TARG
V DD
INIT
SELOE
V SS
RSTOE
BSYOE
DBOE11
DBOE10
DBOE9
DBOE8
AD23
V SS
AD22
AD21
AD20
V DD
AD19
V SS
AD18
AD17
AD16
V SS
C/BE2
FRAME
IRDY
V SS
TRDY
V DD
DEVSEL
STOP
V SS
PERR
PAR
C/BE1
V SS
AD15
AD14
AD13
AD12
V SS
V DD
AD11
AD10
AD9
V SS
AD8
140
IDSEL
C/BE3
AD24
AD25
V SS
AD26
AD27
V DD
AD28
AD29
V SS
AD30
AD31
V DD
PREQ
GNT
V SS
RESET
PCLK
SERR
DBOE12
DBOE13
V SS
DBOE14
DBOE15
UDOBEP
DBOE0
DBOE1
V DD
DBOE2
DBOE3
DBOE4
V SS
DBOE5
DBOE6
DBOE7
(TOP VIEW)
(FPT-144P-M08)
5
MB86606A
■ PIN LIST
16-bit bus mode
PCI bus I/F
mode
PCI bus I/F
mode
16-bit bus mode
Pin
Pin
no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F)
I/O Pin name
1
I/O DMD9
2
— VSS
3
I/O DMD8
4
I/O Pin name I/O Pin name
I/O AD23
I/O Pin name I/O Pin name I/O
31
Pin name
— VDD
32 I/O D6
I/O AD11
I/O AD22
33 I/O D5
I/O AD10
I/O DMD7
I/O AD21
34 I/O D4
I/O AD9
5
I/O DMD6
I/O AD20
35
6
— VDD
7
I/O DMD5
8
— VSS
9
I/O DMD4
— VSS
36 I/O D3
I/O AD8
37 I/O D2
I/O C/BE0
38 I/O D1
I/O AD7
I/O AD18
39 I/O D0
I/O AD6
10 I/O DMD3
I/O AD17
40
11 I/O DMD2
I/O AD16
41 I/O LDP
12
I/O AD19
— VSS
42
13 I/O DMD1
I/O C/BE2
43
14 I/O DMD0
I/O FRAME
44
15 I/O LDMDP
I/O IRDY
45
16
— VSS
17 I/O UDP
18
I/O TRDY
— VDD
— VSS
I
UDS
I/O AD5
I
BHE
I/O AD4
I
WR
I/O AD3
I
RD
I/O AD2
— VDD
I
LDS
— VSS
46
I
R/W
47
I
CS1
I/O AD1
48
I
CS0
I/O AD0
19 I/O D15
I/O DEVSEL
49
— VDD
20 I/O D14
I/O STOP
50
O/
OD
INT
51
I
A4
O
PO1
I
A3
O
PO0
21
— VSS
22 I/O D13
I/O PERR
52
23 I/O D12
I/O PAR
53
24 I/O D11
I/O C/BE1
54
25
— VSS
— VSS
I
SCLK
55
IU A2
IU PI1
26 I/O D10
I/O AD15
56
IU A1
IU PI0
27 I/O D9
I/O AD14
57
IU A0
IU N.C.
28 I/O D8
I/O AD13
58
— VSS
29 I/O D7
I/O AD12
59
I
MODE1
60
I
MODE2
30
— VSS
(Continued)
6
MB86606A
(Continued)
16-bit bus mode
PCI bus I/F
mode
16-bit bus mode
PCI bus I/F
mode
Pin
Pin
no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F)
I/O Pin name
I/O Pin name I/O Pin name
I/O Pin name I/O Pin name I/O
61
I
S/DSEL
91
I/O DB7
62
O
TARG
92
I/O DB6
63
— VDD
93
— VSS
64
O
INIT
94
I/O DB5
65
O
SELOE
95
I/O DB4
66
— VSS
96
I/O DB3
67
O
RSTOE
97
I/O DB2
68
O
BSYOE
98
— VSS
69
O
DBOE11
99
I/O DB1
70
O
DBOE10
100 I/O DB0
71
O
DBOE9
101 I/O UDBP
72
O
DBOE8
102 — VSS
73
— VDD
103 I/O DB15
74 I/O DB11
104 I/O DB14
75 I/O DB10
105 I/O DB13
76 I/O DB9
106 I/O DB12
77
107 — VDD
— VSS
78 I/O DB8
108
O
LDBOEP
79 I/O I/O
109
O
DBOE7
80 I/O REQ
110
O
DBOE6
81 I/O C/D
111
O
DBOE5
82
112 — VSS
— VSS
Pin name
83 I/O SEL
113
O
DBOE4
84 I/O MSG
114
O
DBOE3
85 I/O RST
115
O
DBOE2
86 I/O ACK
116 — VDD
87 I/O BSY
117
O
DBOE1
88
— VSS
118
O
DBOE0
89 I/O ATN
119
O
UDBOEP
90 I/O LDBP
120
O
DBOE15
(Continued)
7
MB86606A
(Continued)
16-bit bus mode
PCI bus I/F
mode
PCI bus I/F
mode
16-bit bus mode
Pin
Pin
no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F)
I/O Pin name
I/O Pin name I/O Pin name
121 O DBOE14
133
122 — VSS
134 — VSS
123 O DBOE13
135
124 O DBOE12
136 I/O UDMDP
125
I
DMA0
126
I
TP
127
I
RESET
OD SERR
I
PCLK
129
I
DACK
I
130 O DREQ
GNT
O PREQ
131 — VDD
132
I
DMUDS
I
I
DMLDS
DMR/W
Pin name
I
DMWR
I/O AD30
I
DMRD
I/O AD29
I/O AD28
137 — VDD
138 I/O DMD15
I/O AD27
139 I/O DMD14
I/O AD26
140 — VSS
128 — VSS
I
DMBHE
I : Input pin
O : Output pin
I/O : Input/Output pin
IU : Input pin with pull-up resistor
OD : Open-drain output pin
8
I/O Pin name I/O Pin name I/O
I/O AD31
141 I/O DMD13
I/O AD25
142 I/O DMD12
I/O AD24
143 I/O DMD11
I/O C/BE3
144 I/O DMD10
I
IDSEL
MB86606A
■ PIN DESCRIPTION
1. SCSI Interface
Pin no.
84, 81
89, 79
80, 86
Pin name
I/O
Function
MSG, C/D
ATN, I/O
These are the SCSI control signal input and output
pins.
They can be connected directly to a single-ended
I/O
SCSI connector.
Either open-drain or totem pole output can be
selected.
REQ, ACK
These are the SCSI control signal input and output
pins.
I/O They can be connected directly to a single-ended
SCSI connector.
The output buffer is the totem pole type.
These are used for output control of SCSI control
signals.
They should be used as control signals for the
external differential driver/receiver circuit.
68
65
67
BSYOE
SELOE
RSTOE
O
87
83
85
BSY
SEL
RST
These are the SCSI control signal input and output
pins.
I/O They can be connected directly to a single-ended
SCSI connector.
The output buffer is the open-drain type.
120, 121, 123, 124, 69 to 72
119
109 to 111, 113 to 115, 117,
118
108
103 to 106, 74 to 76, 78
101
91, 92, 94 to 97, 99, 100
90
64
62
DBOE15 to DBOE8
UDBOEP
DBOE7 to DBOE0
LDBOEP
O
DB15 to DB8
UDBP
DB7 to DB0
LDBP
These are used to input and output SCSI data bus
signals.
They can be connected directly to a single-ended
I/O
SCSI connector.
Either open-drain or totem pole output buffer can be
selected.
INIT
TARG
These are used for output control of SCSI data bus
signals.
They should be used as control signals for the
external differential driver/receiver circuit.
O
These are used to output signals indicating the chip
operating status.
They should be used as control signals for the
external differential driver/receiver circuit.
61
S/DESL
I
This is used to input signal for selecting the chip
operation mode.
Single-ended: Input 0
Differential-ended: Input 1
While 0 is input to this pin, all the SCSI control signals,
data bus output control signals, INIT, and TARG
signals are fixed with L level.
54
SCLK
I
This pin is used for a system clock input for SCSI
protocol controller block. (Max. 40 MHz)
9
MB86606A
2. 16-Bit Bus Mode-MPU Interface
Pin no.
I/O
Function
48
CS0
I
This is used to input signals for the MPU to select the SPC
as the I/O device.
47
CS1
I
This is used to input select signals (external circuit select
signals) for the MPU to input and output the DMA data bus
data via the SPC.
19, 20, 22 to 24, 26 to 28
17
D15 to D8
UDP
I/O
Upper byte and parity of data bus
When CS0 input valid: I/O ports for internal registers in SPC
When CS1 input valid: I/O ports for DMA bus data
29, 32 to 34, 36 to 39
41
D7 to D0
LDP
I/O
Lower byte and parity of data bus
When CS0 input valid: I/O ports for internal registers in SPC
When CS1 input valid: I/O ports for DMA bus data
51, 52, 55 to 57
A4 to A0
IU
These are used to input addresses for selecting the Internal
registers.
I
In 80-series mode: This is used to input the read strobe
signal for reading data from the SPC to
the MPU.
In 68-series mode: This is used to input the R/W control
signal for reading and writing data from
the MPU to the SPC.
I
In 80-series mode: This is used to input the write strobe
signal for writing data from the MPU to
the SPC.
In 68-series mode: This is used to input the LDS signal
output by the MPU when the lower byte
of the data bus is valid.
I
In 80-series mode: This is used to input the BHE signal
output by the MPU when the upper byte
of the data bus is valid.
In 68-series mode: This is used to input the UDS signal
output by the MPU when the upper byte
of the data bus is valid.
46
44
42
10
Pin name
RD (R/W)
WR (LDS)
BHE (UDS)
MB86606A
3. 16-Bit Bus Mode – DMA Interface
Pin no.
Pin name
I/O
Function
130
DREQ
O
This is used to output DMA transfer request signals to the
DMAC.
DMA data transfer between the SPC and memory is
requested.
129
DACK
I
This is used to input DMA-enabling signals from the DMAC.
When the DMA enabling signal is active, DMA reading and
writing are executed.
138, 139, 141 to 144, 1, 3 DMD15 to 8
136
UDMDP
4, 5, 7, 9 to 11, 13, 14
15
135
133
DMD7 to 0
LDMDP
DMRD (DMR/W)
DMWR (DMLDS)
Upper byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly
I/O
connected.
When 80-series mode: The 2nd data is input/output.
When 68-series mode: The 1st data is input/output.
Lower byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly
I/O
connected.
When 80-series mode: The 1st data is input/output.
When 68-series mode: The 2nd data is input/output.
I
In 80-series mode: This is used to input the IORD or RD
signal for outputting data from the SPC
to the DMA bus.
In 68-series mode: This is used to input the R/W control
signal for outputting and inputting data
from the DMAC to the SPC.
I
In 80-series mode: This is used to input the IOWR or WR
signal for inputting data from the DMA
bus to the SPC.
In 68-series mode: This is used to input the LDS signal
output by the DMAC when the lower
byte of the DMA data bus is valid.
132
DMBHE (DMUDS)
I
In 80-series mode: This is used to input the BHE signal
output by the DMAC when the upper
byte of the DMA data bus is valid.
In 68-series mode: This is used to input the UDS signal
output by the DMAC when the upper
byte of the DMA data bus is valid.
125
DMA0
I
This is used to input the address data A0 signal output by
the DMAC in the 80-series mode.
In 68-series mode: Connect to power supply pin (VDD).
126
TP
(Transfer
permission)
I
This is used to input DMA-transfer-enabling signals.
When the TP signal is active, the SPC performs the DMA
transfer.
When this signal becomes inactive during DMA transfer, the
transfer stops temporarily at the block boundary.
11
MB86606A
4. PCI Bus Interface Mode
Pin no.
Pin name
Function
130
PREQ
O
This pin is used to request the bus arbiter for use of the bus.
129
GNT
I
This is the response signal input pin to the REQ signal from
the bus arbiter.
132, 133, 135, 136,
138, 139, 141, 142, 1, 3
to 5, 7, 9 to 11, 26 to 29, AD31 to AD0
32 to 34, 36, 38, 39, 41,
42, 44, 46 to 48
143, 13, 24, 37
12
I/O
I/O PCI 32-bit address and data multiplexed pins
C/BE3 to C/BE0
I/O Bus command and Byte Enable signals multiplexed pins.
23
PAR
This is an even parity signal pin for the AD31 to AD0 and C/
I/O BE3 to C/BE0 signals. This PAR signal becomes valid after
one clock.
14
FRAME
I/O
17
TRDY
I/O Data Ready signal of Target side.
15
IRDY
I/O Data Ready signal of Initiator (Bus master) side.
20
STOP
I/O
19
DEVSEL
Device select pin. While the device is a target, this pin
outputs the select signal that indicates the self device is
I/O
selected. While the device is a master this pin functions as
an input pin to indicate that a device on the bus is selected.
144
IDSEL
I
This is a chip select signal that indicates the configuration
access.
126
PCLK
I
PCI bus clock input pin. The maximum clock frequency is 33
MHz.
22
PERR
I/O Data parity error input and output pin.
125
SERR
OD Address parity error output pin.
This is a frame signal pin that indicates data are transferring
on the bus.
This is a stop request signal to stop the data transfer from
target to master.
MB86606A
5. Other Signals
Pin No.
127
Pin name
RESET
I/O
O
Function
This pin is used to input system reset signals.
These pins are used for setting the device operation mode
as listed in the table below.
MODE1 MODE0
59, 60
50
MODE1, MODE0
INT
I
Operation Mode
0
0
16-bit bus mode (68 series mode)
0
1
16-bit bus mode (80 series mode)
1
0
Reserved
1
1
PCI bus interface mode
Interrupt output pin. Either totem pole or open-drain output
O/
buffer can be selected. This pin has an internal pull-up
OD
resistor.
6, 18, 31, 43, 49, 63,
VDD
73, 107, 116, 131, 137
— Power supply pin
2, 8, 12, 16, 21, 25, 30,
35, 40, 45, 53, 58, 66,
77, 82, 88, 93, 98, 102, VSS
112, 122, 128,
134, 140
— Ground pin
51, 52
PO1, PO0
O
General purpose output ports that can control the external
active SCSI bus terminator etc. Initial signal level on each
pin is “L”. Those pins are available only for PCI bus interface
mode.
55, 56
PI1, PI0
IU
General purpose input ports. Available only for PCI bus
interface mode.
N.C.
No connection and unused pins. These pins exist on the only
— PCI bus mode. These are internally pulled-up, and do not
connect to the pins.
57
I : Input pin
O : Output pin
I/O : Input and Output pin
OD : Open-drain output pin
IU : Input pin with pull-up resistor
13
MB86606A
■ BLOCK DIAGRAM
BHE (UDS)
A4 to 0
CS1
CS0
RD (R/W)
WR (LDS)
D15 to 8, UDP
D7 to 0, LDP
INT
1. 16-Bit Bus Mode
MPU Interface
MSG
C/D
1
I/O
ATN
5
Internal
Processor
Various
Registers
BSYOE
BSY
2
SELOE
Timer
6
SEL
DACK
DMBHE (DMUDS)
7
(32 Bytes)
4
DMA0
Send
MSG, CMD,
Status Buffer
Transfer
Controller
INIT
8 (2048 Bytes)
TARG
User
Program
Memory
DB15 to 8,
UDBP
DMA Interface
SCSI Interface
ACK
DREQ
Phase
Controller
RST
REQ
Receive
MSG, CMD,
Status Buffer
3
RSTOE
(32 Bytes)
DMD15 to 8, UDMAP
DMD7 to 0, LDMDP
IOWR (DMLDS)
IORD (DMR/W)
DB7 to 0,
LDBP
9 (512 Bytes)
DBOE15 to 8,
UDBOEP
DBOE7 to 0,
LDBOEP
S/DSEL
14
Data
Register
TP
MB86606A
PCLK
IDSEL
SERR
PERR
DEVSEL
STOP
IRDY
TRDY
FRAME
PAR
C/BE3 to 0
AD31 to 0
GNT
PREQ
2. PCI Bus Interface Mode
PCI Interface
MSG
C/D
1
I/O
ATN
5
Internal
Processor
Various
Registers
BSYOE
BSY
2
SELOE
Timer
6
SEL
Phase
Controller
ACK
SCSI Interface
RST
REQ
Receive
MSG, CMD,
Status Buffer
3
RSTOE
(32 Bytes)
11
7
(32 Bytes)
4
Send
MSG, CMD,
Status Buffer
Transfer
Controller
DMA
Controller
INIT
8 (2048 Bytes)
TARG
User
Program
Memory
DB15 to 8,
UDBP
DB7 to 0,
LDBP
DBOE15 to 8,
UDBOEP
9 (512 Bytes)
10
Data
Register
Burst-FIFO
(64 Bytes)
DBOE7 to 0,
LDBOEP
S/DSEL
15
MB86606A
■ BLOCK FUNCTIONS
1. Internal Processor
This processor provides the sequence control between each phase.
2. Timer
This timer manages the time specified by SCSI and the following time:
•
•
•
•
REQ/ACK assertion time for data at asynchronous transfer
Selection/reselection retry time
Selection/reselection timeout time
REQ/ACK timeout time during transfer
Asynchronous transfer (target)
: Time required for initiator to assert ACK signal after asserting REQ
signal
Asynchronous transfer (initiator)
: Time required for target to negate REQ signal after asserting ACK
signal
Synchronous transfer (target only)
: Time required for target to receive ACK signal for setting offset value
to 0 from initiator after sending REQ signal
3. Phase Controller
This controller controls the arbitration, selection/reselection, data-in/out, command, status, and message-in/out
phases executed on the SCSI bus.
4. Transfer Controller
This controller controls the information (data, command, status, message) transfer phases executed on the SCSI
bus.
There are two types of transfer for executing the information transfer phases.
• Asynchronous transfer
• Synchronous transfer
: Control by interlocking REQ and ACK signals
: Control with maximum of 32-byte offset value in data-in/out phase
Depending on the data migration, there are the following two modes.
• Program transfer : Performed via MPU interface using data registers
• DMA transfer
: Performed via DMA interface using DREQ and DACK pins
At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal
sent from SPC in synchronous transfer, and maximum value between REQ and ACK signals in synchronous
transfer) can be saved for each ID and are automatically set when the data phase is started. The transfer byte
count is determined by block length × number of blocks.
5. Various Registers
• Command register
This register specifies each command with an 8-bit code.
When using the user program, specify “1” at the Bit 7. The lower 7 bits (Bit 6 to Bit 0) are invalid.
• Nexus status register
This register indicates the chip’s operating condition, the nexused partner’s ID, and data register status.
• SCSI control signal status register
This register indicates the status of SCSI control signals.
16
MB86606A
• Interrupt status register
This register indicates the interrupt status with an 8-bit code.
• Command step register
This register indicates the execution status of each command with an 8-bit step code.
Error causes can be analyzed by referencing the interrupt status register and this register.
• Group 6/7 command length setting register
This register sets the group 6/7 command length not defined in the SCSI standard.
Setting this register determines the group 6/7 command length.
6. Receive MSG, CMD, Status Buffer (Receive MCS Buffer)
This is a 32-byte receive-only information buffer that holds the information for the message, command, and
status received from the SCSI bus.
7. Send MSG, CMD, Status Buffer (Send MCS Buffer)
This is a 32-byte send-only information buffer that holds the information for the message, command, and status
sent on the SCSI bus.
8. User Program Memory
This is a 2048-byte program memory that stores programmable commands. It can consist of 1024-byte × 2
banks or 2048-byte × 1 bank.
9. Data Register
This is a 512-byte FIFO data register that holds data in the data phase executed on the SCSI bus.
10.Burst FIFO
64-byte FIFO type data buffer to perform burst transfer during the PCI bus interface mode. The device has total
576-byte FIFO with Data Register and Burst FIFO in the PCI bus interface mode.
11.DMA Controller
This is a 32-bit DMA Controller that performs data transfer. This DMAC is a bus master during the PCI bus
interface mode.
17
MB86606A
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min.
Max.
VDD
VSS –0.5
6.0
V
Input voltage*
VI
VSS –0.5
VDD +0.5
V
Output voltage*
VO
VSS –0.5
VDD +0.5
V
Operating ambient temperature
Top
–25
+85
°C
Storage temperature
Tstg
–40
+125
°C
Supply voltage*
* : The voltages are based on VSS (= 0V)
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Supply voltage*
VDD
4.75
5.0
5.25
V
SCSI clock input frequency
fSCSI
20.0
—
40.0
MHz
PCI clock input frequency
fPCI
—
—
33.0
MHz
Operating temperature
Ta
0
—
+70
°C
* : The voltages are based on VSS (= 0V)
Note: The recommended operating conditions are the recommended values for assuring normal logic operation of
the LSI. Requirements in electrical characteristics (DC and AC characteristics) are assured within the range
of the recommended operating conditions.
18
MB86606A
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VDD = +5 V±5%, VSS = 0 V, Ta = 0 to +70°C)
Value
Symbol
Condition
Unit
Min. Max.
Parameter
SCSI pins
Input
voltage*1
SCLK pins
SDSEL pins
Other pins
SCSI-pin input hysteresis*
1
VIH
—
1.9
—
V
VIL
—
—
1.0
V
VIH
—
2.4
—
V
VIL
—
—
0.8
V
VIH
—
2.0
—
V
VIL
—
—
0.8
V
VHW
—
0.3
—
V
VOH
IOH = –7.0 mA
2.0
3.24
V
VOL
IOL = +48.0 mA
—
0.5
V
VOL
IOL = +48.0 mA
—
0.5
V
VOL
IOL = +48.0 mA
—
0.5
V
VOH
IOH = –7.0 mA
2.0
3.24
V
VOL
IOL = +48.0 mA
—
0.5
V
VOH
IOH = –7.0 mA
2.0
3.24
V
VOL
IOL = +3.2 mA
—
0.4
V
VOH
IOH = –2.0 mA
4.2
—
V
VOL
IOL = +6.0 mA
—
0.55
V
VOH
IOH = –2.0 mA
4.2
—
V
VOL
IOL = +3.2 mA
—
0.4
V
ILI
VIN = 0 to VDD
–10
+10
µA
Input/output leakage current*2
ILOZ
VIN = 0 to VDD
–10
+10
µA
Supply current
IDD
—
150
mA
REQ, ACK
SCSI pins
In single- RST, BSY, SEL
end mode
Non-3ST.
Others
Output
voltage*1
In differential mode
PCI bus interface pins
Other pins
Input leakage current
3ST.
—
3ST. : Three-state mode
*1
: SCSI pins are; UDBP, DB15 to DB8, LDBP, DB7 to DB0, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D and
I/O. (Total 27 pins)
*2
: Leak current when the three-state output pin output and the bidirectional bus pin output are in a high
impedance state.
19
MB86606A
2. Input/Output Pin Capacitance
Parameter
(VDD = VIN = 0 V, f = 1 MHz, Ta = +25°C)
Conditions
Symbol
Unit
Min.
Max.
Pin name
SCLK, PCLK (TP)
Input-pin capacitance
CIN
Other input pins
Output-pin capacitance
COUT
Input/output-pin capacitance
Non-SCSI pins
CI/O
SCSI pins
—
12
pF
—
8
pF
—
10
pF
—
10
pF
—
25
pF
3. Load Conditions for Measurement of AC Characteristics
(1) Non-SCSI pins
(VDD = +5 V±5%, VSS = 0 V, Ta = 0 to +70°C)
16-bit bus mode
Measurement
point
Pin name
MB86606A
Measurement
pin
CL
INT, DREQ
60 pF
D15 to D8, UDP, D7 to D0, LDP,
DMD15 to DMD8, UDMDP,
DMD7 to DMD0, LDMDP
85 pF
PCI bus interface mode
CL
Pin name
PCI bus pins
CL
50 pF
(2) SCSI pins
(VDD = +5 V±5%, VSS = 0 V, Ta = 0 to +70°C)
Measurement
point
MB86606A
Load resistance
R L1
Load capacitance
Measurement
pin
R L2
20
CL
R L1 = 110Ω
R L2 = 165Ω
CL = 200 pF
MB86606A
4. AC Characteristics
(1) System clock
• SCSI clock (SCLK pin)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Clock period
tCLF
25.0
—
50.0
ns
Clock pulse width (Low)
tCLCH
10.0
—
—
ns
Clock pulse width (High)
tCHCL
10.0
—
—
ns
Clock pulse rise time
tCR
—
—
5.0
ns
Clock pulse fall time
tCF
—
—
5.0
ns
Note: When the internal operating clock frequency is the same as the input clock frequency, (when using the device
in divide-by-1 mode), the clock pulse width for L and H levels must have minimum 20.0 ns or longer.
(i.e. When the clock conversion register value is 0Bh (address: 10h in the initial setting registers) and input
clock frequency = 20 MHz.)
t CLCH
t CLF
t CR
t CF
SCLK
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
0.8 V
2.4 V
0.8 V
t CHCL
21
MB86606A
• PCI clock (PCLK pin)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Clock frequency
tPCY
30.0
—
—
ns
Clock pulse width (Low)
tPLO
12.0
—
—
ns
Clock pulse width (High)
tPHI
12.0
—
—
ns
Clock slew rate
tPSR
1.0
—
4.0
V/ns
Clock amplitude
VIHP – VILP
2.0
—
—
V
t PHI
t PCY
V IHP
PCLK
2.0 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
0.8 V
V ILP
t PLO
(2) System reset
Parameter
Reset (RESET) pulse “L” level pulse width
Symbol
tWRSL
t WRSL
RESET
22
Value
Min.
Typ.
Max.
4 tCLF
—
—
Unit
ns
MB86606A
5. MPU Interface
(1) Register write timing for 80 series
Parameter
Symbol
Value
Min.
Max.
Unit
Address (A4 to A0), BHE setup time (1)
tAWS
20
—
ns
Address (A4 to A0) hold time (1)
tAWH
10
—
ns
Address (A4 to A0), BHE setup time (2)
tACS
10
—
ns
Address (A4 to A0) hold time (2)
tACH
5
—
ns
CS0 setup time
tCWS
10
—
ns
CS0 hold time
tCWH
5
—
ns
Data set up time
tDWS
25
—
ns
Data hold time
tDWH
10
—
ns
WR “L” level pulse width
tWR
70
—
ns
A4 to A0
BHE
t AWS
t AWH
tACS
t ACH
CS0
t CWS
t WR
t CWH
WR
t DWS
t DWH
D15 to 8, UDP
Data
D7 to 0, LDP
23
MB86606A
(2) Register read timing for 80 series
Parameter
Symbol
Value
Min.
Max.
Unit
Address (A4 to A0), BHE setup time (1)
tARS
20
—
ns
Address (A4 to A0) hold time (1)
tARH
10
—
ns
Address (A4 to A0), BHE setup time (2)
tACS
10
—
ns
Address (A4 to A0) hold time (2)
tACH
5
—
ns
CS0 setup time
tCRS
10
—
ns
CS0 hold time
tCRH
5
—
ns
RD set Low → data output defined time
tRLD
—
40
ns
RD set High → data output defined time
tRHD
5
—
ns
RD pulse duration at Low
tRD
70
—
ns
Interrupt non-hold mode
tDL
—
50
ns
Interrupt hold mode
tDL2
—
n•tCLF +50
ns
INT signal clear time
A4 to A0
BHE
t ARH
t ARS
t ACS
t ACH
CS0
t CRS
t RD
t CRH
RD
t RLD
t RHD
D15 to 8, UDP
Valid data
D7 to 0, LDP
t DL
INT
t DL2*
(n is the division ratio)
INT
*: t DL2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source.
24
MB86606A
(3) Register write timing for 80 series (for external access)
Parameter
Value
Symbol
Min.
Max.
Unit
Address (A0), BHE setup time (1)
tAWSE
20
—
ns
Address (A0) hold time (1)
tAWHE
10
—
ns
Address (A0), BHE setup time (2)
tACSE
10
—
ns
Address (A0) hold time (2)
tACHD
5
—
ns
CS1 setup time
tCWSE
10
—
ns
CS1 hold time
tCWHE
5
—
ns
WR set Low → DMA bus output delay time
tWHLD
—
40
ns
WR set High → DMA bus output undefined time
tWHHD
5
—
ns
tDHD
—
20
ns
MPU data bus → DMA bus output delay time
A0
BHE
t AWHE
t AWSE
t ACSE
t ACHD
CS1
t CWSE
t CWHE
WR
t WLHD
t WHHD
D15 to 8, UDP
Data
D7 to 0, LDP
t DHD
t DHD
DMD15 to 8, UDMDP
Valid data
DMD7 to 0, LDMDP
25
MB86606A
(4) Register read timing for 80 series (for external access)
Parameter
Symbol
Value
Min.
Max.
Unit
Address (A0), BHE setup time (1)
tARSE
20
—
ns
Address (A0), BHE hold time (1)
tARHE
10
—
ns
Address (A0), BHE setup time (2)
tACSE
10
—
ns
Address (A0), BHE hold time (2)
tACHD
5
—
ns
CS1 setup time
tCRSE
10
—
ns
CS1 hold time
tCRHE
5
—
ns
RD set Low → MPU bus output enable time
tRLNZ
—
40
ns
RD set High → MPU bus output disable time
tRHHZ
5
—
ns
DMA data bus → MPU bus output delay time
tHDD
—
20
ns
A0
BHE
t ARSE
t ARHE
t ACSE
t ACHD
CS1
t CRSE
t CRHE
RD
DMD15 to 8,
UDMDP
Data
DMD7 to 0,
LDMDP
t HDD
t RLNZ
t RHHZ
D15 to 8, UDP
Valid data
D7 to 0, LDP
26
MB86606A
(5) Register write timing for 68 series
Parameter
Value
Symbol
Min.
Max.
Unit
Address (A4 to A0) setup time (1)
tAWS
20
—
ns
Address (A4 to A0) hold time (1)
tAWH
10
—
ns
Address (A4 to A0) setup time (2)
tACS
10
—
ns
Address (A4 to A0) hold time (2)
tACH
5
—
ns
CS0 setup time
tCWS
10
—
ns
CS0 hold time
tCWH
5
—
ns
Data setup time
tDWS
25
—
ns
Data hold time
tDWH
10
—
ns
tDS
70
—
ns
R/W setup time
tRWS
10
—
ns
R/W hold time
tRWH
10
—
ns
UDS/LDS “L” level pulse width
A4 to A0
t AWS
t AWH
t ACS
t ACH
CS0
t CWS
t CWH
R/W
t RWS
t DS
t RWH
UDS/LDS
t DWH
t DWS
D15 to 8, UDP
Data
D7 to 0, LDP
27
MB86606A
(6) Register read timing for 68 series
Parameter
Symbol
Value
Min.
Max.
Unit
Address (A4 to A0) setup time (1)
tARS
20
—
ns
Address (A4 to A0) hold time (1)
tARH
10
—
ns
Address (A4 to A0) setup time (2)
tACS
10
—
ns
Address (A4 to A0) hold time (2)
tACH
5
—
ns
CS0 setup time
tCRS
10
—
ns
CS0 hold time
tCRH
5
—
ns
Data output defined time
tRLD
—
40
ns
Data output disable time
tRHD
5
—
ns
UDS/LDS “L” level pulse width
tDS
70
—
ns
R/W setup time
tRWS
10
—
ns
R/W hold time
tRWH
10
—
ns
tDH
—
50
tDH2
—
n•tCLK+50
INT signal clear time
ns
A4 to A0
t ARS
t ARH
t ACS
t ACH
CS0
t CRS
t CRH
R/W
t RWS
t DS
t RWH
UDS/LDS
t RLD
t RHD
D15 to 8, UDP
Valid data
D7 to 0, LDP
t DH
INT
(n is the division ratio)
t DH2*
INT
*: t DH2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source.
28
MB86606A
(7) Register write timing for 68 series (for external access)
Parameter
Value
Symbol
Min.
Max.
Unit
Address (A0) setup time (1)
tAWSE
20
—
ns
Address (A0) hold time (1)
tAWHE
10
—
ns
Address (A0) setup time (2)
tACSE
10
—
ns
Address (A0) hold time (2)
tACHD
5
—
ns
CS1 setup time
tCWSE
10
—
ns
CS1 hold time
tCWHE
5
—
ns
UDS/LDS set Low → DMA bus output delay time
tWLHD
—
40
ns
UDS/LDS set High → DMA bus output undefined time
tWHHD
5
—
ns
MPU data bus → DMA bus output delay time
tDHD
—
20
ns
R/W setup time
tRWS
10
—
ns
R/W hold time
tRWH
10
—
ns
A0
t AWSE
t AWHE
t ACSE
t ACHD
CS1
t CWSE
t CWHE
R/W
t RWS
t DS
t RWH
UDS/LDS
t WHHD
t WLHD
D15 to 8, UDP
Data
D7 to 0, LDP
t DHD
DMD15 to 8, UDMDP
Valid data
DMD7 to 0, LDMDP
29
MB86606A
(8) Register read timing for 68 series (for external access)
Parameter
Symbol
Value
Min.
Max.
Address (A0) setup time (1)
tARSE
20
—
ns
Address (A0) hold time (1)
tARHE
10
—
ns
Address (A0) setup time (2)
tACSE
10
—
ns
Address (A0) hold time (2)
tACHD
5
—
ns
CS1 setup time
tCRSE
10
—
ns
CS1 hold time
tCRHE
5
—
ns
UDS/LDS set Low → MPU data bus output enable time
tRLNZ
—
40
ns
UDS/LDS set High → MPU data bus output disable time
tRHH
5
—
ns
DMA bus → MPU data bus output delay time
tHDD
—
20
ns
R/W setup time
tRWS
10
—
ns
R/W hold time
tRWH
10
—
ns
A0
t ARSE
t ARHE
t ACHD
t ACSE
CS1
t CRHE
t CRSE
R/W
t RWS
t RWH
UDS/LDS
DMD15 to 8,
UDMDP
Data
DMD7 to 0,
LDMDP
t HDD
t RLNZ
t RHHZ
D15 to 8, UDP
Valid data
D7 to 0, LDP
30
Unit
MB86606A
6. DMA Interface
DMA access timing
The time regulations are not applicable in the following cases:
•
•
•
•
During SCSI input and when data buffer EMPTY, or when one byte held
During SCSI output and when data buffer FULL, or when 511 bytes held
When parity error detected (target)
When error stopping transfer occurs in SCSI interface
(1) Access cycle time (burst mode)
Parameter
Symbol
Address cycle time
Value
Unit
Min.
Max.
tDCY1
2 tCLF
—
ns
tDCY2
3 tCLF
—
ns
tDCY3
4 tCLF
—
ns
tDCY4
1 tCLF
—
ns
t DCY2
IOWR/IORD
DMUDS/DMLDS
t DCY1
t DCY4
t DCY3
31
MB86606A
(2) Write timing (burst mode for 80 series)
Parameter
Symbol
Value
Min.
Max.
DREQ set High → DACK set Low
tDHAL
0
—
ns
IOWR set Low → DREQ set Low
tALDL
—
25
ns
DREQ set Low → DREQ set High
tDLDH
0
—
ns
DACK set Low → IOWR set Low
tALWL
0
—
ns
DMBHE, DMA0 setup time
tDAWS
10
—
ns
IOWR “L” level pulse width
tDWR
25
—
ns
IOWR set High → DACK set High
tWHAH
0
—
ns
DMBHE, DMA0 hold time
tDAWH
10
—
ns
Input data setup time
tDDWS
25
—
ns
Input data hold time
tDDWH
5
—
ns
t DLDH
DREQ
t DHAL
t ALDL
DACK
t ALWL
t WHAH
DMBHE
DMA0
t DAWS
t DWR
t DAWH
IOWR
t DDWS
DMD15 to 0
UDMDP, LDMDP
32
Unit
Data
t DDWH
MB86606A
(3) Read timing (burst mode for 80 series)
Parameter
Symbol
Value
Min.
Max.
Unit
DREQ set High → DACK set Low
tDHAL
0
—
ns
IORD set Low → DREQ set Low
tALDL
—
25
ns
DREQ set Low → DREQ set High
tDLDH
0
—
ns
DACK set Low → IORD set Low
tALRL
0
—
ns
DMBHE, DMA0 setup time
tDARS
10
—
ns
IORD “L” level pulse width
tDRD
25
—
ns
IORD set High → DACK set High
tRHAH
0
—
ns
DMBHE, DMA0 hold time
tDARH
10
—
ns
Data output defined time
tDRLD
—
25
ns
Data output hold time
tDRHD
10
—
ns
t DLDH
DREQ
t DHAL
t ALDL
DACK
t ALRL
t RHAH
DMBHE
DMA0
t DARS
t DRD
t DARH
IORD
t DRLD
DMD15 to 0
UDMDP, LDMDP
t DRHD
Valid data
33
MB86606A
(4) Write timing (burst mode for 68 series)
Parameter
Symbol
Value
Min.
Max.
DREQ set High → DACK set Low
tDHAL
0
—
ns
DMUDS/DMLDS set Low → DREQ set Low
tALDL
—
25
ns
DREQ set Low → DREQ set High
tDLDH
0
—
ns
DACK set Low → DMUDS/DMLDS set Low
tALDL
5
—
ns
R/W setup time
tDRWS
10
—
ns
DMUDS/DMLDS “L” level pulse width
tDDS
25
—
ns
DMUDS/DMLDS set High → DACK set High
tDHAH
0
—
ns
R/W hold time
tDRWH
10
—
ns
Input data setup time
tDDWS
25
—
ns
Input data hold time
tDDWH
5
—
ns
t DLDH
DREQ
t DHAL
t ALDL
DACK
t ALDL
t DHAH
DMR/W
t DRWS
t DDS
t DRWH
DMUDS/DMLDS
t DDWS
DMD15 to 0
UDMDP, LDMDP
34
Unit
Data
t DDWH
MB86606A
(5) Read timing (burst mode for 68 series)
Parameter
Symbol
Value
Min.
Max.
Unit
DREQ set High → DACK set Low
tDHAL
0
—
ns
DMUDS/DMLDS set Low → DREQ set Low
tALDL
—
25
ns
DREQ set Low → DREQ set High
tDLDH
0
—
ns
DACK set Low → DMUDS/DMLDS set Low
tALDL
5
—
ns
R/W setup time
tDRWS
10
—
ns
DMUDS/DMLDS “L” level pulse width
tDDS
25
—
ns
DMUDS/DMLDS set High → DACK set High
tDHAH
0
—
ns
R/W hold time
tDRWH
10
—
ns
Output data valid time
tDRLD
—
25
ns
Output data hold time
tDRHD
10
—
ns
t DLDH
DREQ
t DHAL
t ALDL
DACK
t ALDL
t DHAH
DMR/W
t DRWS
t DDS
t DRWH
DMUDS/DMLDS
t DRLD
DMD15 to 0
UDMDP, LDMDP
t DRHD
Valid data
35
MB86606A
7. PCI Interface
(1) PCI interface signal timing
Parameter
Value
Symbol
Min.
Max.
Output signal valid time
tPVAL
2
11/12*1
ns
Output disable time
tPOFF
—
28
ns
Output enable time
tPON
2
—
ns
Input setup time
tPSU
7/10*2
—
ns
Input hold time
tPHD
0
—
ns
*1: Applicable to PREQ pin
*2: Applicable to GNT pin
2.4 V
1.5 V
PCICLK
0.4 V
OUTPUT
H to I
or L to H
1.5 V
t PVAL
OUTPUT
H/L to Hi-Z
t POFF
OUTPUT
Hi-Z to H/L
t PON
2.4 V
INPUT
1.5 V
1.5 V
0.4 V
t PSU
36
Unit
t PHD
MB86606A
(2) Configuration register read timing
PCICLK
FRAME
IDSEL
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
STOP
(3) Configuration register write timing
PCICLK
FRAME
IDSEL
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
STOP
Note: For the access to the configuration register, only one data transfer possible.
When a master device executes the burst transfer, a target device asserts STOP signal, and performs the target termination.
37
MB86606A
(4) BASIC control register read timing (target mode)
• Byte or word access
Burst read (target termination), single read
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
STOP
Note: Only one data transfer is possible for reading BASIC control regisuter.
When a master device does the burst transfer to the target device, it
asserts STOP signal and performs the target termination.
38
MB86606A
• Long-word access
Single read
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
STOP
Burst read (target termination)
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
STOP
Note: For the read operation of BASIC control registers, only one data transfer possible.
When a master device executes the burst transfer, a target device asserts STOP signal and performs the target termination.
39
MB86606A
(5) Target mode – I/O, memory read timing (except BASIC control registers)
• Byte, word access
Single read
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
Burst read
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
40
MB86606A
• Long-word access
Single read
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
Burst read
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
41
MB86606A
(6) Target Mode – I/O, memory write timing
• Byte, word access
Single write burst write
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
42
MB86606A
• Long-word access
Single write
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
Burst write
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
43
MB86606A
(7) Data read timing (master mode)
• Burst length = 1 and 4
Burst = 1
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
• Burst length = 8
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
• Burst length = 16
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
44
Burst = 4
MB86606A
(8) Data write timing (master mode)
• Burst length = 1 and 4
Burst = 1
Burst = 4
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
• Burst length = 8
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
• Burst length = 16
PCICLK
FRAME
AD31 to 00
C/BE3 to 0
IRDY
TRDY
DEVSEL
45
MB86606A
8. SCSI Interface
(1) Initiator asynchronous input timing (target → initiator)
Parameter
Value
Symbol
Min.
Max.
Unit
ACK set Low → REQ set High
tAOLR
0
—
ns
REQ set High → ACK set High
tRAOH
—
60
ns
ACK set High → REQ set Low
tAOHR
10
—
ns
Data bus valid → REQ set Low
tDTSU
10
—
ns
REQ set Low → data bus hold time
tDHLD
20
—
ns
REQ set Low → ACK set Low
tRAOL
—
40
ns
REQ set High → ACK set Low*
tRACY
—
3 tCLF +40
ns
* : tRACY (REQ set High → ACK set Low) is defined as either longer time of (tRAOH + tAOHR +tRAOL) or tRACY itself
Note: Time requirements in this section do not apply in the following cases;
• When data register FULL in data phase
• When last byte transferred
t RACY
REQ
t AOLR
t RAOH
ACK
t DTSU
DB7 to 0, P
DB15 to 8, P
46
t DHLD
Data
t AOHR
t RAOL
MB86606A
(2) Initiator asynchronous output timing (initiator → target)
Parameter
Symbol
Value
Min.
Max.
Unit
ACK set Low → REQ set High
tAOLR
0
—
ns
REQ set High → ACK set High
tRAOH
—
60
ns
ACK set High → REQ set Low
tAOHR
10
—
ns
Data bus output defined → ACK set Low*
tDVLD
S•tCLF–10
—
ns
REQ set High → data bus hold time
tDIVD
2 tCLF
—
ns
REQ set Low → ACK set Low
tRAOL
—
40
ns
* : The value of S varies with the setting condition of the asynchronous setup time register (address 17h).
Note: This output timing regulations are not applicable when the data register is EMPTY in the data phase.
t RACY*
REQ
t AOLR
t RAOH
t AOHR
t RAOL
ACK
t DVLD
DB7 to 0, P
DB15 to 8, P
t DIVD
Valid data
t DVLD
Valid data
* : The time (tRACY) of REQ set High → ACK set Low is defined by the longer time either (tRAOH + tAOHR +tRAOL)
or (tDIVD + tDVLD).
47
MB86606A
(3) Initiator synchronous transfer REQ/ACK timing
Parameter
Symbol
Value
Min.
Max.
ACK Assertion Period*
tAKAP
A•tCLF–4
—
ns
ACK Negation Period*
tANAP
N•tCLF–6
—
ns
REQ Assertion Period
tRQAP
20
—
ns
REQ Negation Period
tRNAP
20
—
ns
REQ input cycle time (1)
tRQF1
1 tCLF
—
ns
REQ input cycle time (2)
tRQF2
3 tCLF
—
ns
* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).
t AKAP
t ANAP
ACK
t RQAP
t RNAP
REQ
t RQF1
t RQF2
48
Unit
MB86606A
(4) Initiator synchronous transfer input timing (target → initiator)
Parameter
Value
Symbol
Min.
Max.
Unit
Data bus defined → REQ set Low
tDTSU
5
—
ns
REQ set Low → data bus hold time
tDHLD
15
—
ns
REQ
t DTSU
DB7 to 0, P
DB15 to 8, P
t DHLD
t DTSU
Data
t DHLD
Data
(5) Initiator synchronous transfer output timing (initiator → target)
Parameter
Value
Symbol
Min.
Max.
Unit
Data bus defined → ACK set Low*
tDVAK
N•tCLF–10
—
ns
ACK set Low → data bus hold time*
tAKDH
A•tCLF–5
—
ns
* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).
ACK
t DVAK
DB7 to 0, P
DB15 to 8, P
Valid data
t AKDH
t DVAK
t AKDH
Valid data
49
MB86606A
(6) Target asynchronous input timing (initiator → target)
Parameter
Symbol
Value
Min.
Max.
Unit
REQ set Low → ACK set Low
tROLA
0
—
ns
ACK set Low → REQ set High
tAROH
—
60
ns
REQ set High → ACK set High
tROHA
0
—
ns
Data bus defined → ACK set Low
tDTSU
10
—
ns
ACK set Low → data bus hold time
tDHLD
20
—
ns
ACK set High → REQ set Low
tAROL
—
40
ns
ACK set Low → REQ set Low*
tRACY
—
3 tCLF + 40
ns
* : tRACY (ACK set Low → REQ set Low) is defined as either longer time of (tAROH + tROHA +tAROL) or tRACY itself
Note: The input timing regulations are not applicable when the data register is FULL in the data phase.
t RACY
REQ
t ROLA
t AROH
t ROHA
ACK
t DTSU
DB7 to 0, P
DB15 to 8, P
50
t DHLD
Data
t AROL
MB86606A
(7) Target asynchronous input timing (target → initiator)
Parameter
Value
Symbol
Min.
Max.
Unit
REQ set Low → ACK set Low
tROLA
0
—
ns
ACK set Low → REQ set High
tAROH
—
60
ns
REQ set High → ACK set High
tROHA
0
—
ns
Data bus defined → REQ set Low*
tDVLD
S•tCLF – 10
—
ns
ACK set Low → data bus hold time
tDIVD
2 tCLF
—
ns
ACK set High → REQ set Low
tAROL
—
40
ns
* : The value of S varies with the setting condition of the asynchronous setup time register (address 17h).
Note: The output timing regulations are not applicable when the data register is EMPTY in the data phase.
t RACY*
REQ
t ROLA
t AROH
t ROHA
t AROL
ACK
t DVLD
DB7 to 0, P
DB15 to 8, P
t DIVD
Valid data
t DVLD
Valid data
* : The time (tRACY) of ACK set High → REQ set Low is defined by the longer time either (tAROH + tROHA +tAROL)
or (tDIVD + tDVLD).
51
MB86606A
(8) Target synchronous transfer REQ/ACK timing
Parameter
Symbol
Value
Min.
Max.
REQ Assertion Period*
tRQAP
A•tCLF – 4
—
ns
REQ Negation Period*
tRNAP
N•tCLF – 6
—
ns
ACK Assertion Period
tAKAP
20
—
ns
ACK Negation Period
tANAP
20
—
ns
ACK input cycle time (1)
tAKF1
1 tCLF
—
ns
ACK input cycle time (2)
tAKF2
3 tCLF
—
ns
* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).
t RQAP
t RNAP
REQ
t AKAP
t ANAP
ACK
t AKF1
t AKF2
52
Unit
MB86606A
(9) Target synchronous transfer input timing (initiator → target)
Parameter
Value
Symbol
Min.
Max.
Unit
Data bus defined → ACK set Low
tDTSU
5
—
ns
ACK set Low → data bus hold time
tDHLD
15
—
ns
ACK
t DTSU
DB7 to 0, P
DB15 to 8, P
t DHLD
t DTSU
Data
t DHLD
Data
(10) Target synchronous transfer output timing (target → initiator)
Parameter
Value
Symbol
Min.
Max.
Unit
Data bus defined → REQ set Low*
tDVRQ
N•tCLF – 10
—
ns
REQ set Low → data bus hold time*
tRQDH
A•tCLF – 5
—
ns
* : The values of A and N vary with the setting condition of the transfer period register (address 0Ch).
REQ
t DVRQ
DB7 to 0, P
DB15 to 8, P
Valid data
t RQDH
t DVRQ
t RQDH
Valid data
53
MB86606A
(11) A, N, and S values in SCSI interface timing specifications
• Set value for transfer period register and A, N values
Transfer period register
A
N
Transfer period register
A
N
1
9
8
1
0
9
9
0
1
1
10
9
0
1
0
0
10
10
1
0
1
0
1
11
10
3
1
0
1
1
0
11
11
4
3
1
0
1
1
1
12
11
0
4
4
1
1
0
0
0
12
12
0
1
5
4
1
1
0
0
1
13
12
0
1
0
5
5
1
1
0
1
0
13
13
1
0
1
1
6
5
1
1
0
1
1
14
13
0
1
1
0
0
6
6
1
1
1
0
0
14
14
0
1
1
0
1
7
6
1
1
1
0
1
15
14
0
1
1
1
0
7
7
1
1
1
1
0
15
15
0
1
1
1
1
8
7
1
1
1
1
1
16
15
1
0
0
0
0
8
8
0
0
0
0
0
16
16
4
3
2
1
0
4
3
2
1
0
0
0
0
0
1
(inhibited)
(inhibited)
1
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
1
1
2
1
1
0
0
0
1
0
0
2
2
1
0
0
1
0
1
3
2
0
0
1
1
0
3
0
0
1
1
1
0
1
0
0
0
1
0
0
1
0
Note: The A and N values in the register setting represent the assertion and negation periods (in clock-cycle units).
The numerical value is applicable to the A and N values in AC characteristics.
54
MB86606A
• Set value for asynchronous setup time register and S value
Asynchronous setup time setting register
S
3
2
1
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
0
0
0
0
16
Note: The S (setup time) value of the setup time setting register in asynchronous data transfer represents the time
required to assert the REQ or ACK signal after setting data at the data bus (in clock-cycle units).
The numerical value is applicable to the S value in AC characteristics.
55
MB86606A
■ SYSTEM CONFIGURATION
1. 80-Series Separate Bus Type
MB86606A
OSC
RESET
circuit
CLK
DB15 to 8 RESET
UDBP
DB7 to 0 MODE0
LDBP
MODE1
DBOE15 to 8
UDBOEP
DBOE7 to 0
LDBOEP
INT
CS0
ACK
MPU
ADDRESS
DECODE
CS1
DIFFERENTIAL
ATN
INIT
A4 to A0
ADDRESS BUS
REQ
D15 to D0
UDP
LDP
MSG
DATA BUS
C/D
BHE
RD
WR
I/O
DR/REV
TARG
BSY
DMD15 to 0
UDMDP
LDMDP
DMA BUS
BSYOE
SEL
SELOE
DREQ
DACK
DMBHE
IORD
IOWR
RST
RSTOE
DMA0
TP
SDSEL
56
DMA
CONTROL
ADDRESS
DATA
BUFFER
MEMORY
MB86606A
2. 68-Series Separate Bus Type
MB86606A
OSC
RESET
circuit
CLK
DB15 to 8 RESET
UDBP
DB7 to 0 MODE0
LDBP
MODE1
DBOE15 to 8
UDBOEP
DBOE7 to 0
LDBOEP
INT
MPU
A0
CS0
ACK
ADDRESS
DECODE
DIFFERENTIAL
CS1
ATN
INIT
A4 to A1
ADDRESS BUS
REQ
D15 to D0
UDP
LDP
MSG
DATA BUS
C/D
R/W
UDS
LDS
I/O
DR/REV
TARG
BSY
DMD15 to 0
UDMDP
LDMDP
DMA BUS
BSYOE
SEL
SELOE
DREQ
DACK
DMR/W
DMUDS
DMLDS
DMA
CONTROL
ADDRESS
DATA
BUFFER
MEMORY
RST
RSTOE
DMA0
TP
SDSEL
57
MB86606A
3. 80-Series Common Bus Type
MB86606A
OSC
RESET
circuit
CLK
DB15 to 8 RESET
LDBP
DB7 to 0 MODE0
UDBP
MODE1
DBOE15 to 8
UDBOEP
DBOE7 to 0
LDBOEP
INT
CS1
ACK
MPU
ADDRESS
DECODE
CS0
DIFFERENTIAL
ATN
INIT
A4 to A0
ADDRESS BUS
REQ
D15 to D0
UDP
LDP
MSG
DATA BUS
C/D
BHE
RD
WR
I/O
DR/REV
TARG
BSY
DMD15 to 0
UDMDP
LDMDP
DMA BUS
BSYOE
SEL
SELOE
DREQ
DACK
DMBHE
IORD
IOWR
RST
RSTOE
DMA0
TP
SDSEL
58
DMA CONTROL
MB86606A
4. 68-Series Common Bus Type
MB86606A
OSC
RESET
circuit
CLK
DB15 to 8 RESET
LDBP
DB7 to 0 MODE0
UDBP
MODE1
DBOE15 to 8
UDBOEP
DBOE7 to 0
LDBOEP
INT
MPU
A0
CS1
ACK
ADDRESS
DECODE
CS0
DIFFERENTIAL
ATN
INIT
A4 to A1
ADDRESS BUS
REQ
D15 to D0
UDP
LDP
MSG
DATA BUS
C/D
R/W
UDS
LDS
DR/REV
I/O
TARG
BSY
DMD15 to 0
UDMDP
LDMDP
DMA BUS
BSYOE
SEL
SELOE
DREQ
DACK
DMR/W
DMUDS
DMLDS
DMA CONTROL
RST
RSTOE
DMA0
TP
SDSEL
59
MB86606A
5. Example of Connection in Differential Mode (Example of Driver/Receiver Connection)
(TOP VIEW)
RO 1
8 V CC
R
RE 2
7 DO, RI
DE 3
6 DO, RI
DI 4
D
5 GND
MB561
MB86606A
18
DB15 to 0
UDBP
LDBP
R
(+) SIGNAL
18
DBOE15 to 0
UDBOEP
LDBOEP
(−) SIGNAL
D
2
ACK, ATN
R
INIT
(+) SIGNAL
(−) SIGNAL
SCSI BUS
D
4
REQ, MSG
C/D, I/O
R
(+) SIGNAL
TARG
(−) SIGNAL
D
BSY, SEL
RST
BSYOE, SELOE
RSTOE
3
R
3
(−) SIGNAL
D
SDSEL
60
(+) SIGNAL
MB86606A
6. Example of Connection in Single-end Mode
MB86606A
DB15 to 0
UDBP
LDBP
18
18
(OPEN)
DBOE15 to 0
UDBOEP
LDBOEP
2
ACK, ATN
INIT
SCSI BUS
(OPEN)
4
REQ, MSG
C/D, I/O
TARG
BSY, SEL
RST
BSYOE, SELOE
RSTOE
(OPEN)
3
3
(OPEN)
SDSEL
61
MB86606A
■ ORDERING INFORMATION
Part number
MB86606APMT2
62
Package
144-pins, Plastic LQFP
(FPT-144P-M08)
Remarks
MB86606A
■ PACKAGE DIMENSION
144-pin plastic LQFP
(FPT-144P-M08)
22.00±0.30(.866±.012)SQ
1.70(.67)MAX
(Mounting height)
20.00±0.10(.787±.004)SQ
108
0(0)MIN
(STAND OFF)
73
109
72
17.50
(.686)
REF
21.00
(.827)
NOM
Details of "A" part
0.15(.006)
0.15(.006)
INDEX
0.15(.006)MAX
144
37
0.40(.016)MAX
"A"
LEAD No.
1
36
0.50(.0197)TYP
0.20±0.10
(.008±.004)
0.08(.003)
Details of "B" part
M
0.15±0.05
(.006±.002)
0
0.10(.004)
C
1995 FUJITSU LIMITED F144019S-1C-2
10°
0.50±0.20(.020±.008)
"B"
Dimensions in mm (inches)
63
MB86606A
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9904
 FUJITSU LIMITED Printed in Japan
64
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.