FUJITSU MB86604L

FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
DS04-22415-1E
Communication Control
CMOS
SCSI-II Protocol Controller
(with single-ended driver/receiver)
MB86604L
■ DESCRIPTION
The Fujitsu MB86604L is a single-ended transmission type SCSI-II Protocol Controller (SPC) with a single-ended
driver/receiver. The MB86604L facilitates interface control between small/medium host computer and peripheral
devices (such as a hard disk and printer). The specifications conform to the SCSI-II Standard.
The MB86604L supports high-speed synchronous transfer, the MPU/DMA independent system data bus, and
user programmable command set to enable configuration of high-performance systems.
It can also have the phase-to-phase sequence control function to reduce the program overhead of the host MPU.
The MB86604L incorporate with a single-ended type SCSI driver/receiver which can drive 48 mA of large-current,
and so, the device can be directly connected with the SCSI bus.
The device can operate with +5 V single-power supply and in up to 40 MHz clock frequency. As for package, a
100-pin plastic small quad flat package is available.
■ FEATURES
SCSI Bus Interface:
• Conforming to the SCSI-II standard
• Operatable as Initiator and target
(Continued)
■ PACKAGE
100 pin, Plastic LQFP
(FPT-100P-M05)
MB86604L
(Continued)
• Two types of high-speed data transfer:
– Synchronous data transfer (Max. 10 Mbytes/s, max. 32 offsets, 32-step transfer rate)
– Asynchronous data transfer (Max. 5 Mbyte/s)
• Transfer parameters (transfer mode, transfer rate, transfer offset) can be set for up to 7 connected devices.
• Single-ended transmission type (Maximum cable length: 6 m):
– On-chip single-ended driver/receiver which can drive 48 mA of "L" level output current
– Directly connectable with the SCSI bus
• On-chip three-state bidirectional I/O buffers for SCSI REQ and ACK pins (DB7-DB0, DBP, ATN, MSG, C/D, I/
O pins can be selected from either three-state or open-drain buffer by controlling the TEST pins input.)
Transfer Operation:
• Automatic response to selection/reselection (Preset receiving operation can perform at the selection/
reselection.):
– Initiator: Automatically operates until message received without command issue.
– Target: Automatically operates until command received without command issue.
• Automatic receiving:
– Initiator: Automatically receives information for new phase to which target transited without command issue.
– Target: Automatically receives message from initiator when initiator generates attention condition.
• On-chip 32-byte data register (FIFO) for data phase
• On-chip two (send-only and receive-only) 32-byte data buffers for message, command, and status phases
• On-chip 16-bit transfer block register and 24-bit transfer byte register enabling 1 Tbytes transfer (1 Tbytes: 16
Mbytes × 64 k blocks)
• On-chip independent data transfer bus enabling the MPU operation during the data transfer
• Parity through/generate can be specified.
System Bus Interface:
• 8-bit or 16-bit separate MPU and DMA buses
• Directly connectable with a 80 series or 68 series MPU
• Two types of transfer operation:
– Program transfer
– DMA transfer (Burst/Handshake)
Command Set:
• Supports sequential commands and programmable commands in addition to ordinary commands
• Command queuing (Command can be continuously issued by putting tags to commands in command phase.)
• On-chip 256-byte memory for command programming memory and command queuing buffer
Others
• Process: CMOS process
• Supply Voltage: Single +5 V
• Input System Clock: 20 MHz/30 MHz/40 MHz
• Package: 100-pin plastic LQFP
2
MB86604L
■ PIN ASSIGNMENT
(TOP VIEW)
WR
RD
V DD
V SS
CLK
RESET
INT
MODE
DBP
V SS
DB 7
DB 6
DB 5
V DD
V SS
V SS
DB 4
DB 3
DB 2
DB 1
V SS
DB 0
TEST 1
TMOUT
(OPEN)
INDEX
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I OWR
I ORD
V DD
V SS
DMA 0
LDMDP
DMD 0
DMD 1
DMD 2
DMD 3
DMD 4
DMD 5
DMD 6
DMD 7
V SS
DMD 8
DMD 9
DMD 10
DMD 11
DMD 12
DMD 13
DMD 14
DMD 15
UDMDP
DMBHE
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
BHE
UDP
D 15
D 14
D 13
D 12
D 11
D 10
D9
D8
V SS
D7
D6
D5
D4
D3
D2
D1
D0
LDP
CS 1
V SS
V DD
CS 0
A4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A3
A2
A1
A0
ATN
V SS
BSY
ACK
RST
V SS
V SS
V DD
MSG
SEL
C/D
REQ
V SS
I/O
TEST2
(OPEN)
TP
V SS
V DD
DREQ
DACK
(FPT-100P-M05)
3
MB86604L
■ PIN DESCRIPTION
1. SCSI Interface
Pin
number
Symbol
Pin name
I/O
Function
60
REQ
Request
I/O
Transfer request signal in the information transfer phases from
target to initiator. The input signal to this pin is used for the timing
control of data transfer sequence. This is a three-state I/O pin
and an active low pin.
68
ACK
Acknowledge
I/O
This pin is for the acknowledge signal from initiator to target for
the REQ signal in the information transfer phases. The input
signal to this pin is used for the timing control of data transfer
sequence. This is a three-state I/O pin and an active low pin.
71
ATN
Attention
I/O
This pin is for the attention signal that initiator requests target for
the message transfer phase. This is an active-low pin.
63
MSG*
Message
I/O
This pin is for the message signal that specifies type of
information transferred on the data bus. This is an active-low pin
and becomes “L” when message phase is specified.
61
C/D*
Control/data
I/O
This pin is for the control/data signal that specifies type of
information transferred on the data bus. This an active-low pin
and becomes “L” level when command, status, or message
phase is specified.
58
I/O*
Input/output
I/O
This pin is for the input/output signal that specifies direction of
information transferred on the data bus. This is an active-low pin.
When this pin is “L” level, the information is transferred from
target to initiator. When this pin is “H” level, the information is
transferred from initiator to target.
69
BSY
Busy
I/O
This pin is for the SCSI bus busy signal. In the arbitration phase,
this is for the request signal for the use of bus acquisition. This is
an active-low pin.
62
SEL
Select
I/O
This pin is for the select signal used by initiator to select target
during the selection phase and by target to reselect initiator
during the reselection phase. This is an active-low pin.
67
RST
Reset
I/O
This pin is for the reset signal used by any device on the bus.
When the device is an input operation, the reset signal is input to
this pin. When output operation, the reset signal is output from
this pin. This is an active-low pin.
Data bus 7
to
data bus 0
I/O
These pins are for the bidirectional 8-bit SCSI data bus and 1-bit
odd parity line.
11, 12, 13, DB7
17, 18, 19, to
DB0
20, 22
9
DBP
Data bus
parity
* : Regarding the status of information transfer which is indicated by MSG, C/D, and I/O pins, See Table Phase Status.
4
MB86604L
Phase name
Transfer direction
MSG
C/D
I/O
Data-out phase
H
H
H
→
Data-in phase
H
H
L
←
Command phase
H
L
H
→
Status phase
H
L
L
←
Message-out phase
L
L
H
→
Message-in phase
L
L
L
←
Initiator
Target
Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus.
2. MPU Interface
Pin
number
Symbol*
Pin name
I/O
Function
77
CS0
Chip select 0
I
This is a chip select 0 pin used by MPU to select the SPC as an
I/O device. This is an active-low pin.
80
CS1
Chip select 1
I
This is a chip select 1 pin to select when MPU inputs/outputs the
data on DMA bus through SPC. This is an active-low pin.
I/O
These pins are for the upper byte and parity bit of MPU data bus.
When the CS0 input is valid, these pins serve as I/O ports for the
SPC internal registers. When the CS1 input is valid, these pins
serve as I/O ports for the DMA bus data.
I/O
These pins are for the lower byte and parity bit of the MPU data
bus. When the CS0 input is valid, these pins serve as I/O ports
for the SPC internal registers. When the CS1 input is valid, these
pins serve as I/O ports for the DMA bus data.
98, 97, 96, D15
95, 94, 93, to
92, 91
D8
99
UDP
89, 88, 87, D7
86, 85, 84, to
83, 82
D0
81
LDP
76, 75, 74, A4
73, 72
to
A0
Data 15
to
data 8
Upper data
parity
Data 7
to
data 0
Lower data
parity
Address 4
to
address 0
I
These are address input pins to select the SPC internal
registers.
2
RD
(R/W)
Read
(read/write)
I
In the 80-series mode, this is a read signal input pin (IORD or
RD) that MPU reads the SPC. This read signal pin is an activelow. In the 68-series mode, this pin functions as the control
signal input (R/W) to control the read/write operation to the SPC.
In the read operation, this pin is an active-high. In the write
operation, this pin is an active-low.
1
WR
(LDS)
Write
(lower data
strobe)
I
In the 80-series mode, this pin is a write signal input pin (IOWR
or WR) that MPU writes to the SPC. This write signal input pin is
active-low. In the 68-series mode, this pin function as the lower
data strobe signal input (LDS) that MPU outputs when the lower
byte of data bus is valid. The LDS pin is an active-low.
(Continued)
5
MB86604L
(Continued)
Pin
number
Symbol*
Pin name
I/O
Function
100
BHE
(UDS)
Bus high
enable
(strobe)
I
In the 80-series mode, this pin is used for input of the bus high
enable signal (BHE) output from the MPU when the upper byte of
the data bus is valid. The BHE pin is an active-low. In the 68series mode, this pin functions as the upper data strobe signal
input pin (UDS) output from the MPU when the upper byte of the
data bus is valid. The UDS pin is also an active-low.
7
INT
(INT)
Interrupt
request
O
The INT and INT pins are the interrupt request signal output. The
INT pins is used for the 80-series mode (an active-high pin), and
the INT signal is used for the 68-series mode (an active-low pin).
8
MODE
Mode
I
This input pin is used to select the type of the MPU and DMA
buses. In the 80-series mode, a high level is input. In the 68series mode, a low level is input.
* : The pin symbols in parenthesis are the ones when the MODE input is “L”.
3. DMA Interface
Pin
number
Symbol*
Pin name
I/O
Function
52
DREQ
DMA request
O
This is an output pin of DMA transfer request signal to the DMA
controller. The data transfer between the SPC and memory via
the DMA bus is requested. This pin is an active-high.
51
DACK
DMA
acknowledge
I
This is a DMA acknowledge signal input pin output from the
DMA controller that enables the DMA transfer. This pin is an
active-low. When this pin is an active state, the DMA cycle (read/
write) is valid.
DMA data 15
to
DMA data 8
I/O
These pins are the input/output pins of the upper byte and parity
bit of the DMA data bus. When the signal input to the CS1 pin
(pin 80) is valid, these pins are connected directly to the MPU
data bus.
I/O
These pins are the input/output pins of the lower byte and parity
bit of the DMA data bus. When the CS1 (pin 80) input is valid,
these pins are connected directly to the MPU data bus.
48, 47, 46, DMD15
45, 44, 43, to
42, 41
DMD8
49
UDMDP
39, 38, 37, DMD7
36, 35, 34, to
33, 32
DMD0
Upper DMA
data parity
DMA data 7
to
DMA data 0
31
LDMDP
Lower DMA
data parity
27
IORD
(DMR/W)
I/O read
(DMA read/
write)
I
In the 80-series mode, this pin (IORD or RD) is used for the input
pin to output the data from the SPC to the DMA bus. This is an
active-low pin. In the 68-series mode, this pin functions as a
control signal input pin (DMR/W) to input/output the data to the
SPC by the DMA controller. In the output operation, this pin is on
the high-state (active-high state). In the input operation, this pin
is on the low-state (active-low state).
26
IOWR
(DMLDS)
I/O write
(DMA lower
data strobe)
I
In the 80-series mode, this (IOWR or WR) is used for the input
pin to input the DMA bus data to the SPC. In the 68-series mode,
this pin functions as a DMA lower data strobe input (DMLDS)
that DMA controller outputs when the lower byte of the DMA bus
data is valid. Both IOWR and DMLDS pins are an active-low.
(Continued)
6
MB86604L
(Continued)
Pin
number
Symbol*
Pin name
50
DMBHE
(DMUDS)
30
55
I/O
Function
DMA bus
high enable
(DMA upper
data strobe)
I
In the 80-series mode, this pin is for the DMA bus high enable
signal input pin (DMBHE) output from the DMA controller when
the upper byte of the DMA data bus is valid. This is an active-low
pin. In the 68-series mode, this pin functions as the DMA upper
data strobe signal input pin (DMUDS) output from the DMA
controller when the upper byte of data bus is valid. The DMUDS
pin is also an active-low.
DMA0
DMA
address 0
I
In the 80-series mode, this pin is used for the DMA address 0
input pin output from the DMA controller. In the 68-series mode,
a high level should be input to this pin.
TP
Transfer
permission
I
This is a DMA transfer permission signal input pin. When this pin
is in active-state, the SPC does the DMA transfer. In case that
this pin becomes inactive during the DMA transfer, the DMA
transfer is paused on the block boundary. This pin is an active
high.
* : The pin symbols in parenthesis are the ones when the MODE input is “L”.
4. Others
Pin
number
Symbol*
Pin name
I/O
Function
6
RESET
Reset
I
System reset input pin. The input reset active pulse width must
have 4 times of the clock cycle at least. This is an active-low pin.
5
CLK
Clock
I
Clock signal input pin. 20 MHz, 30 MHz, or 40 MHz can be
applied as the input clock frequency.
3, 14, 28
53, 64, 78
VDD
Power supply
—
+5 V power supply pins.
4, 10, 15
16, 21, 29
40, 54, 59
65, 66, 70
79, 90
VSS
Ground
—
Ground pins.
23
TEST1
TEST
I
This pin is used to select the type of I/O buffer on SCSI data bus
pins. In case that DBP, DB7 – DB0 pins are used as an opendrain I/O, connect this pin to VSS. In case of three-state I/O,
connect to VDD.
57
TEST2
TEST
I
This pin is used to select the type of I/O buffer on SCSI pins. In
case that MSG, C/D, I/O, and ATN pins are used as an opendrain I/O, connect this pin to VSS. In case of three-state I/O,
connect to VDD.
24
TMOUT
TIMEOUT
O
This is a SCSI Timeout pin that indicates the SPC has been
busy longer than the specified time. A high level is output on this
pin if the SPC busy time exceeds the specified time.
This pin can be used for the timeout counter.
25, 26
(OPEN)
(Open)
—
These are open pins. Those pins are not connected with the
device internally. Those pins must be left open.
* : The pin symbols in parenthesis are the symbols when the MODE input is “L”.
7
MB86604L
■ BLOCK DIAGRAM
TMOUT
D15 to D8, UDP
INT D7 to D0, LDP WR
RD
CS0
CS1
A4 to A0 BHE MODE
MPU interface
Internal
processor
MSG
Registers
DREQ
DACK
C/D
DMBHE
I/O
ATN
Timer
BSY
DMA0
Receive MCS buffer
(32 bytes)
REQ
ACK
DB7 to DB0
DBP
8
Phase
controller
Send MCS buffer
(32 bytes)
Transfer
controller
Command user
program memory
(256 bytes)
Data register
(32 bytes)
DMA interface
RST
SCSI interface
SEL
DMD15
to DMD8
UDMDP
DMD7
to DMD0
LDMDP
IOWR
IORD
TP
MB86604L
■ BLOCK DESCRIPTION
1. International Processor (Sequencer)
Performs sequence control between the SCSI bus phases.
Bus free phase
Information transfer
phase
Information transfer phase:
•
•
•
•
Arbitration phase
Command phase
Data phase
Status phase
Message phase
Selection phase
2. Timer
Manages the SCSI time standards.
Also, conducts the following time managements.
• Time until the REQ or ACK signal is asserted for asychronous transfer data
• Time until selection or reselection is retried
• REQ and ACK timeout time during transfers:
Asychronous transfer case
Target: After the REQ is asserted, the time until the initiator asserts the ACK
Initiator: After the ACK is asserted, the time until the target negates the REQ
Synchronous transfer case
Target: After the REQ is sent, the time until an ACK signal which makes the offset 0 is received from the
initiator
• SPC Timeout
Manages the SPC timeout indicating the SPC busy time longer than the specified time.
3. Phase Controller
Controls the various phases executed by SCSI such as arbitration, selection/reselection, data in/out, command,
status, and message in/out.
4. Transfer Controller
Controls the information (data, command, status, message) transfer phases executed by SCSI.
The following two types of transfer phases are used.
Asychronous transfer: Controls interlock (response confirmation format) between the REQ and ACK signals.
Synchronous transfer: Controls a maximum 32-byte offset value for the data in or data out phase.
The following two modes exist for the data phase.
Program transfer: Uses data register (address 00/01) via the MPU interface
DMA transfer: Uses DREQ and DACK signals via the DMA interface.
The transfer parameter setting values for synchronous transfer (Transfer mode, transfer rate, transfer offset) can be
strobe for individual ID device and are automatically established when the data phase is initiated.
The number of transfer bytes is defined as block length × number of blocks.
9
MB86604L
5. Register
The main registers are listed.
• Command register
Command is specified by an 8-bit code.
Specifies the program head address assigned to the user program memory for user program applications.
• Chip status register
Shows the chip's operating state, nexus counterpart ID, and data register state.
• SCSI bus status register
Shows the SCSI control signal state.
• Interrupt status register
Shows 8-bit code.
• Command step register
Shows 8-bit code indicating the command execution state.
Error analysis can be performed by referring to the information in this register and the interrupt status register.
• Group 6/7 command length setting register
Sets the group 6/7 command length which is undefined by the SCSI standard.
By setting the command length in this register, the SPC can determine the command length.
6. Receive-MCS Buffer
A receive only, 32-byte data buffer which stores information received via SCSI (message, command, status)
M: Message, C: Command, S: Status
7. Send-MCS Buffer
A send only, 32-byte data buffer which stores information sent via SCSI (message, command, status)
8. Command User Program Memory
Program memory used for establishing programmable commands (256 bytes).
9. Data Register
FIFO-type data register which stores data in SCSI data phase (32 bytes).
10
MB86604L
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Symbol
Rating
Unit
Min.
Max.
VDD
VSS – 0.5
6.0
V
Input voltage*
VI
VSS – 0.5
VDD + 0.5
V
Output voltage*
VO
VSS – 0.5
VDD + 0.5
V
Operating ambient temperature
Top
–25
+85
°C
Storage temperature
Tstg
–40
+125
°C
Power supply voltage*
* : VSS = 0 V
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD
Power supply voltage *1
CLK
“H” level
input voltage *1
Except SCSI and CLK pins
VIH
SCSI pins
“L” level
input voltage *1
CLK
Except CLK pin
VIL
Except SCSI pins
“H” level
output current *2
“L” level
output current *2
SCSI pins
Three-state
Open-drain
Except SCSI pins
SCSI pins
Operating ambient temperature
IOH
IOL
Ta
Value
Unit
Min.
Typ.
Max.
4.75
5.0
5.25
V
3.5
—
—
V
2.2
—
—
V
2.0
—
—
V
—
—
1.5
V
—
—
0.8
V
—
—
–2.0
mA
—
—
–8.0
mA
—
—
—
mA
—
—
+3.2
mA
—
—
+48
mA
0
—
+70
°C
*1: VSS = 0 V
*2: SCSI pins are DB7 to DB0, DBP, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, I/O
Note: The recommended operating conditions are the values recommended to ensure correct logic operation of
the LSI. The standard values of the electrical characteristics (DC and AC characteristics) are guaranteed
within the range of the recommended operating conditions.
11
MB86604L
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VDD = +5 V±5%, VSS = 0 V, Ta = 0°C to +70°C)
Parameter
Condition
Symbol
CLK
“H” level
input voltage
Except SCSI and
CLK pins
CLK
Except CLK pin
Input hysteresis of SCSI pins *
1
V
2.2
—
V
2.0
—
V
—
1.5
V
—
0.8
V
0.3
—
V
IOH = –2.0 mA
4.2
VDD
V
IOH = –8.0 mA
2.0
—
V
—
—
V
IOL = +3.2 mA
VSS
0.4
V
IOL = +48.0 mA
—
0.5
V
VSS ≤ VI ≤ VDD
–10
+10
µA
VSS ≤ VI ≤ VDD, See Note below
–10
+10
µA
CLK input = 20 MHz
SPC operating clock = 10 MHz
45
mA
CLK input = 30 MHz
SPC operating clock = 10 MHz
48
mA
55
mA
65
mA
CLK input = 20 MHz
SPC operating clock = 20 MHz
60
mA
CLK input = 40 MHz
SPC operating clock = 20 MHz
70
mA
—
VIL
—
VHW
—
VOH
Except SCSI pins
“L” level
1
output voltage * SCSI pins
VOL
Input leakage current
Input/output leakage current
Power supply current
—
ILI
ILOZ
IDD
All output
pins
opened
CLK input = 40 MHz
SPC operating clock = 13.3 MHz
CLK input = 30 MHz
SPC operating clock = 15 MHz
*1: SCSI pins are DB7 to DB0, DBP, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, I/O
Note: Leakage current in the above spec indicates the following currents.
(1) Leakage current at the high-Z state on the three-state output pins.
(2) Leakage current at the output high-Z state (input state) on the bidirectional bus pins.
12
Unit
—
VIH
Except SCSI pins
“H” level
Three-state
output voltage *1 SCSI
pins Open-drain
Min. Max.
3.5
SCSI pins
“L” level
input voltage
Value
—
MB86604L
2. I/O Pin Capacitance
(VDD = VI = 0 V, f = 1 MHz, Ta = +25°C)
Parameter
Symbol
Input pin capacitance
Output pin capacitance
I/O pin capacitance
Except SCSI pins
Unit
Min.
Max.
CIN
—
6
pF
COUT
—
6
pF
—
6
pF
—
25
pF
CI/O
SCSI pins
Value
3. Load Conditions for AC Characteristics
(VDD = +5 V±5%, VSS = 0 V, Ta = 0°C to +70°C)
Non-SCSI pins
Measurement
point
CL
Pin Symbol
INT, DREQ
60 pF
D15 to D8, UDP, D7 to D0, LDP
DMD15 to DMD8, UDMDP
85 pF
MB86604L
Measurement pin
DMD7 to DMD0, LDMDP
CL
CL: Load capacitance
SCSI pins
Measurement
point
V DD
RL1 = 110 Ω
MB86604L
Load resistance
R L1
Load capacitance
Measurement pin
R L2
RL2 = 165 Ω
RL = 200 pF
CL
13
MB86604L
4. AC Characteristics
(1) System clock
Value
Parameter
Symbol
Unit
Position*
Min.
Max.
Clock cycle time (CLK)
tCLK
A
25.0
50.0
ns
Clock “H” pulse width
twCKH
B
10.0
—
ns
Clock “L” pulse width
twCKL
C
10.0
—
ns
Clock rise time
tCR
D
—
10.0
ns
Clock fall time
tCF
E
—
10.0
ns
* : The position number indicates the position in the waveform.
Note: In case that the internal clock frequency and the input clock frequency are the same (i.e. when using the
divided-by-one mode), the clock pulse width (for “H” and “L”) must have at least 20 ns or longer.
B
t wCKH
A
t CLK
t CF
E
D
t CR
3.5 V
CLK
1.5 V
C
t wCKL
(2) System reset
Value
Parameter
Symbol
RESET “L” level pulse width
twRSL
t wRSL
RESET
14
Unit
Min.
Max.
4 tCLK
—
ns
MB86604L
(3) MPU interface (80 series)
• Register write timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Address (A4 to A0), BHE set up time
WR “L”
tsuA
A
40
—
ns
Address (A4 to A0), hold time
WR “H”
thA
B
20
—
ns
CS0 set up time
WR “L”
tsuCS0
C
20
—
ns
CS0 hold time
WR “H”
thCS0
D
10
—
ns
—
twWRL
E
70
—
ns
Data set up time
WR “H”
tsuD
F
40
—
ns
Data hold time
WR “H”
thD
G
10
—
ns
WR “L” level pulse width
* : The position number indicates the position in the waveform.
A4 to A0
BHE
B
t hA
A
t suA
CS0
t suCS0
C
D
E
t wWRL
t hCS0
WR
F
t suD
G
t hD
D15 to D8, UDP
Data
D7 to D0, LDP
15
MB86604L
• Register read timing
Value
Parameter
Symbol
Unit
Base signal
Position*
Min.
Max.
Address (A4 to A0), BHE set up time
RD “L”
tsuA
A
40
—
ns
Address (A4 to A0), Hold time
RD “H”
thA
B
20
—
ns
CS0 set up time
RD “L”
tsuCS0
C
20
—
ns
CS0 hold time
RD “H”
thCS0
D
10
—
ns
RD “L” level pulse width
—
twRDL
E
70
—
ns
Data output defined time
RD “L”
tvD
F
—
70
ns
Data output disable time
RD “H”
tDZ
G
10
—
ns
for INT non-hold mode
RD “L”
tDL
H
—
50
ns
for INT hold mode
RD “H”
tDL2
I
—
n tCLK + 50
ns
INT signal
clear time
* : The position number indicates the position in the waveform.
A4 to A0
BHE
B
t hA
A
t suA
CS0
t suCS0
E
t wRDL
C
D
t hCS0
RD
G
t DZ
F
t vD
D15 to D8, UDP
Valid data
D7 to D0, LDP
t DL
H
INT
t DL2*
I
INT
*: t DL2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source.
Also, “n” indicates the division ratio.
16
MB86604L
• Register write timing (for external access)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Address (A0), BHE set up time
WR “L”
tsuAE
A
40
—
ns
Address (A0), BHE hold time
WR “H”
thAE
B
20
—
ns
CS1 set up time
WR “L”
tsuCS1
C
20
—
ns
CS1 hold time
WR “H”
thCS1
D
10
—
ns
DMA data bus output delay time
WR “L”
tvDMD
E
—
70
ns
DMA data bus output undefined time
WR “H”
tWRDMD
F
10
—
ns
—
tDDMD
G
—
40
ns
MPU data → DMA data bus output delay time
* : The position number indicates the position in the waveform.
A0
BHE
A
t suAE
B
t hAE
CS1
WR
C
t vDMD
D15 to D8, UDP
D
,
+
*
)
6
5
4
"
!
6
+,
!
t suCS1
t hCS1
E
F
t WRDMD
Data
D7 to D0, LDP
t DDMD
G
DMD15 to DMD8, UDMDP
Valid data
DMD7 to DMD0, LDMDP
17
MB86604L
• Register read timing (for external access)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Address (A0), BHE set up time
RD “L”
tsuAE
A
40
—
ns
Address (A0), BHE hold time
RD “H”
thAE
B
20
—
ns
CS1 set up time
RD “L”
tsuCS1
C
20
—
ns
CS1 hold time
RD “H”
thCS1
D
10
—
ns
MPU data bus output enable time
RD “L”
tZD
E
—
70
ns
MPU data bus output disable time
RD “H”
tDZ
F
10
—
ns
—
tDMDD
G
—
40
ns
DMA data → MPU data bus output delay time
* : The position number indicates the position in the waveform.
A0
BHE
A
t suAE
B
t hAE
CS1
t suCS1
D
C
RD
DMD15 to DMD8, UDMDP
t hCS1
Data
DMD7 to DMD0, LDMDP
G
t DMDD
E
t DZ
D15 to D8, UDP
F
t ZD
Valid data
D7 to D0, LDP
18
MB86604L
(4) MPU interface (68 series)
• Register write timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Address (A4 to A0) set up time
UDS/LDS “L”
tsuA
A
40
—
ns
Address (A4 to A0) hold time
UDS/LDS “H”
thA
B
20
—
ns
CS0 set up time
UDS/LDS “L”
tsuCS0
C
20
—
ns
CS0 hold time
UDS/LDS “H”
thCS0
D
10
—
ns
R/W set up time
UDS/LDS “L”
tsuRW
E
20
—
ns
R/W hold time
UDS/LDS “H”
thRW
F
20
—
ns
—
twDS
G
70
—
ns
Data set up time
UDS/LDS “H”
tsuD
H
40
—
ns
Data hold time
UDS/LDS “H”
thD
I
10
—
ns
UDS/LDS “L” level pulse width
* : The position number indicates the position in the waveform.
A4 to A0
B
t hA
A
t suA
CS0
C
D
t suCS0
t hCS0
R/W
E
t suRW
F
t hRW
G
t wDS
UDS/LDS
H
t suD
I
t hD
D15 to D8, UDP
Data
D7 to D0, LDP
19
MB86604L
• Register read timing
Parameter
Base signal
Value
Symbol
Position*
Min.
Max.
Address (A4 to A0) set up time
UDS/LDS “L”
tsuA
A
40
—
ns
Address (A4 to A0) hold time
UDS/LDS “H”
thA
B
20
—
ns
CS0 set up time
UDS/LDS “L”
tsuCS0
C
20
—
ns
CS0 hold time
UDS/LDS “H”
thCS0
D
10
—
ns
R/W set up time
UDS/LDS “L”
tsuRW
E
20
—
ns
R/W hold time
UDS/LDS “H”
thRW
F
20
—
ns
UDS/LDS “L” level pulse time
—
twDS
G
70
—
ns
Data output confirmation time
UDS/LDS “L”
tvD
H
—
70
ns
Data output disable time
UDS/LDS “H”
tDZ
I
10
—
ns
for INT non-hold mode
UDS/LDS “L”
tDH
J
—
50
ns
for INT hold mode
UDS/LDS “H”
tDH2
K
—
n tCLK + 50
ns
INT signal
clear time
* : The position number indicates the position in the waveform.
A4 to A0
B
t hA
A
t suA
CS0
C
D
t suCS0
t hCS0
R/W
E
t suRW
F
t hRW
G
t wDS
UDS/LDS
H
t vD
t DZ
I
D15 to D8, UDP
Valid data
D7 to D0, LDP
t DH
INT
J
K
*
t DH2
INT
*: t DH2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source.
Also, “n” indicates the division ratio.
20
Unit
MB86604L
• Register write timing (for external access)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Address (A0) set up time
UDS/LDS “L”
tsuAE
A
40
—
ns
Address (A0) hold time
UDS/LDS “H”
thAE
B
20
—
ns
CS1 set up time
UDS/LDS “L”
tsuCS1
C
20
—
ns
CS1 hold time
UDS/LDS “H”
thCS1
D
10
—
ns
R/W set up time
UDS/LDS “L”
tsuRW
E
20
—
ns
R/W hold time
UDS/LDS “H”
thRW
F
20
—
ns
DMA data bus output delay time
UDS/LDS “L”
tvDMD
G
—
70
ns
DMA data bus output undefined time
UDS/LDS “H”
tDSDMD
H
10
—
ns
—
tDDMD
I
—
40
ns
MPU data → DMA data bus output delay time
* : The position number indicates the position in the waveform.
A0
B
t hAE
A
t suAE
CS1
C
D
t suCS1
t hCS1
R/W
E
UDS/LDS
,
+
*
)
(
'
6
5
4
3
2
!
,
+
*
6
5
"
!
G
D15 to D8, UDP
F
t hRW
t suRW
H
t DSDMD
t vDMD
Data
D7 to D0, LDP
I
t DDMD
DMD15 to DMD8, UDMDP
Valid data
DMD7 to DMD0, LDMDP
21
MB86604L
• Register read timing (for external access)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Address (A0) set up time
UDS/LDS “L”
tsuAE
A
40
—
ns
Address (A0) hold time
UDS/LDS “H”
thAE
B
20
—
ns
CS1 set up time
UDS/LDS “L”
tsuCS1
C
20
—
ns
CS1 hold time
UDS/LDS “H”
thCS1
D
10
—
ns
R/W set up time
UDS/LDS “L”
tsuRW
E
20
—
ns
R/W hold time
UDS/LDS “H”
thRW
F
20
—
ns
Data output enable time
UDS/LDS “L”
tZD
G
—
70
ns
Data output disable time
UDS/LDS “H”
tDZ
H
10
—
ns
—
tDMDD
I
—
40
ns
DMA data → MPU data bus output delay time
* : The position number indicates the position in the waveform.
A0
A
t suAE
B
t hAE
CS1
C
D
t suCS1
t hCS1
R/W
E
UDS/LDS
DMD7 to DMD0,
LDMDP
DMD15 to DMD8,
UDMDP
F
t hRW
t suRW
+7
*
6
5
A
@
!
,
Data
I
t DMDD
H
t DZ
G
t ZD
D15 to D8, UDP
Valid data
D7 to D0, LDP
22
MB86604L
(5) DMA interface
The DMA access timing described in this section is not applicable in the following cases.
During SCSI input, when the data buffer is EMPTY or when one byte is stored
During SCSI output, when the data buffer is FULL or when 31 bytes are stored
When a parity error is detected (target)
When an error which pauses the transfer occurs at the SCSI interface
• 80 series handshake mode
(a) Write timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
DACK “L”
tAKRQ
B
—
40
ns
DREQ “H” assert time (8 bit)
DACK “H”
tAKRQ1
C
—
50
ns
DREQ “H” assert time (16 bit)
DACK “H”
tAKRQ2
C
—
2 tCLK + 40
ns
IOWR “L” assert time
DACK “L”
tAKWR
D
0
—
ns
DMBHE, DMA0 set up time
IOWR “L”
tsuDA
E
20
—
ns
DMBHE, DMA0 hold time
IOWR “H”
thDA
F
20
—
ns
IOWR “L” level pulse width
—
twWRL
G
40
—
ns
IOWR “L”
tWRAK1
H
1 tCLK
—
ns
IOWR “H”
tWRAK2
I
0
—
ns
Input data set up time
IOWR “H”
tsuDMD
J
30
—
ns
Input data hold time
IOWR “H”
thDMD
K
5
—
ns
DACK “H” negate time
* : The position number indicates the position in the waveform.
23
MB86604L
DREQ
t RQAK
A
B
t AKRQ
C
DACK
D
t AKWR
H
t WRAK1
I
t WRAK2
DMBHE
DMA0
E
t suDA
F
t hDA
G
t wWRL
IOWR
J
t suDMD
DMD15 to DMD0
Data
UDMDP, LDMDP
24
K
t hDMD
t AKRQ1/2
MB86604L
(b) Read timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
DACK “L”
tAKRQ
B
—
40
ns
DREQ “H” assert time (8 bit)
DACK “H”
tAKRQ1
C
—
50
ns
DREQ “H” assert time (16 bit)
DACK “H”
tAKRQ2
C
—
2 tCLK + 40
ns
IORD “L” assert time
DACK “L”
tAKRD
D
0
—
ns
DMBHE, DMA0 set up time
IORD “L”
tsuDA
E
20
—
ns
DMBHE, DMA0 hold time
IORD “H”
thDA
F
20
—
ns
IORD “L” level pulse width
—
twRDL
G
40
—
ns
IORD “L”
tRDAK1
H
1 tCLK
—
ns
IORD “H”
tRDAK2
I
0
—
ns
Data output defined time
IORD “L”
tvDMD
J
—
40
ns
Data output hold time
IORD “H”
thDMD
K
10
—
ns
DACK “H” negate time
* : The position number indicates the position in the waveform.
DREQ
t RQAK
A
B
t AKRQ
C
t AKRQ1/2
DACK
H
t RDAK1
D
t AKRD
I
t RDAK2
DMBHE
DMA0
E
t suDA
G
t wRDL
F
t hDA
IORD
t vDMD
J
K
t hDMD
DMD15 to DMD0
Valid data
UDMDP, LDMDP
25
MB86604L
• 68 series handshake mode
(a) Write timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
DACK “L”
tAKRQ
B
—
40
ns
DREQ “H” assert time (8 bit)
DACK “H”
tAKRQ1
C
—
50
ns
DREQ “H” assert time (16 bit)
DACK “H”
tAKRQ2
C
—
2 tCLK + 40
ns
DMUDS/DMLDS “L” assert time
DACK “L”
tAKDS
D
0
—
ns
DMR/W set up time
DMUDS/DMLDS “L”
tsuRW
E
20
—
ns
DMR/W hold time
DMUDS/DMLDS “H”
thRW
F
20
—
ns
—
twDSL
G
40
—
ns
DMUDS/DMLDS “L”
tDSAK1
H
1 tCLK
—
ns
DMUDS/DMLDS “H”
tDSAK2
I
0
—
ns
Input data set up time
DMUDS/DMLDS “H”
tsuDMD
J
30
—
ns
Input data hold time
DMUDS/DMLDS “H”
thDMD
K
5
—
ns
DMUDS/DMLDS “L” level pulse width
DACK “H” negate time
* : The position number indicates the position in the waveform.
DREQ
A
t RQAK
B
t AKRQ
C
DACK
D
t AKDS
H
t DSAK1
I
t DSAK2
DMR/W
E
t suRW
F
t hRW
G
t wDSL
DMUDS/DMLDS
J
t suDMD
DMD15 to DMD0
Data
UDMDP, LDMDP
26
K
t hDMD
t AKRQ1/2
MB86604L
(b) Read timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
DACK “L”
tAKRQ
B
—
40
ns
DREQ “H” assert time (8 bit)
DACK “H”
tAKRQ1
C
—
50
ns
DREQ “H” assert time (16 bit)
DACK “H”
tAKRQ2
C
—
2 tCLK + 40
ns
DMUDS/DMLDS “L” assert time
DACK “L”
tAKDS
D
0
—
ns
DMR/W set up time
DMUDS/DMLDS “L”
tsuRW
E
20
—
ns
DMR/W hold time
DMUDS/DMLDS “H”
thRW
F
20
—
ns
—
twDSL
G
40
—
ns
DMUDS/DMLDS “L”
tDSAK1
H
1 tCLK
—
ns
DMUDS/DMLDS “H”
tDSAK2
I
0
—
ns
Data output defined time
DMUDS/DMLDS “L”
tvDMD
J
—
40
ns
Data output hold time
DMUDS/DMLDS “H”
thDMD
K
10
—
ns
DMUDS/DMLDS “L” level pulse width
DACK “H” negate time
* : The position number indicates the position in the waveform.
DREQ
t RQAK
A
B
t AKRQ
C
t AKRQ1/2
DACK
H
t DSAK1
D
t AKDS
I
t DSAK2
DMR/W
E
t suRW
G
t wDSL
F
t hRW
DMUDS/DMLDS
t vDMD
J
K
t hDMD
DMD15 to DMD0
Valid data
UDMDP, LDMDP
27
MB86604L
• Burst mode (80 series/68 series common)
(a) Data register access cycle time (8 bit)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Data register access cycle time 1
—
tDCY1
A
tCLK
—
ns
Data register access cycle time 2
—
tDCY2
B
3 tCLK
—
ns
Data register access cycle time 3
—
tDCY3
C
4 tCLK
—
ns
* : The position number indicates the position in the waveform.
IOWR/IORD
DMUDS/DMLDS
A
t DCY1
B
t DCY2
C
t DCY3
(b) Data register access cycle time (16 bit)
Value
Parameter
Symbol
Base signal
Min.
Max.
Data register access cycle time 1
—
tDCY1
A
4 tCLK
—
ns
Data register access cycle time 2
—
tDCY2
B
3 tCLK
—
ns
* : The position number indicates the position in the waveform.
IOWR/IORD
DMUDS/DMLDS
B
t DCY2
A
t DCY1
28
Unit
Position*
MB86604L
• 80 series burst mode
(a) Write timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
IOWR “L”
tWRRQ
B
—
55
ns
—
tRQLH
C
0
—
ns
IOWR “L” assert time
DACK “L”
tAKWR
D
0
—
ns
DMBHE, DMA0 set up time
IOWR “L”
tsuDA
E
20
—
ns
DMBHE, DMA0 hold time
IOWR “H”
thDA
F
20
—
ns
IOWR “L” level pulse width
—
twWRL
G
40
—
ns
DACK “H” negate time
IOWR “H”
tWRAK
H
0
—
ns
Input data set up time
IOWR “H”
tsuDMD
I
30
—
ns
Input data hold time
IOWR “H”
thDMD
J
5
—
ns
DREQ “L” → DREQ “H” return time
* : The position number indicates the position in the waveform.
DREQ
t RQAK
C
B
t WRRQ
A
t RQLH
DACK
D
t AKWR
H
t WRAK
DMBHE
DMA0
E
t suDA
F
t hDA
G
t wWRL
IOWR
I
t suDMD
J
t hDMD
DMD15 to DMD0
Data
UDMDP, LDMDP
29
MB86604L
(b) Read timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
IORD “L”
tRDRQ
B
—
55
ns
—
tRQLH
C
0
—
ns
IORD “L” assert time
DACK “L”
tAKRD
D
0
—
ns
DMBHE, DMA0 set up time
IORD “L”
tsuDA
E
20
—
ns
DMBHE, DMA0 hold time
IORD “H”
thDA
F
20
—
ns
IORD “L” level pulse width
—
twRDL
G
40
—
ns
DACK “H” negate time
IORD “H”
tRDAK
H
0
—
ns
Data output defined time
IORD “L”
tvDMD
I
—
40
ns
Data output hold time
IORD “H”
thDMD
J
10
—
ns
DREQ “L” → DREQ “H” return time
* : The position number indicates the position in the waveform.
DREQ
t RQAK
A
C
B
t RDRQ
t RQLH
DACK
D
t AKRD
H
t RDAK
DMBHE
DMA0
E
t suDA
G
t wRDL
F
t hDA
IORD
t vDMD
J
I
DMD15 to DMD0
UDMDP, LDMDP
30
Valid data
t hDMD
MB86604L
• 68 series burst mode
(a) Write timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
DMUDS/DMLDS “L”
tDSRQ
B
—
55
ns
—
tRQLH
C
0
—
ns
DACK “L”
tAKDS
D
0
—
ns
DMR/W set up time
DMUDS/DMLDS “L”
tsuRW
E
20
—
ns
DMR/W hold time
DMUDS/DMLDS “H”
thRW
F
20
—
ns
—
twDSL
G
40
—
ns
DACK “H” negate time
DMUDS/DMLDS “H”
tDSAK
H
0
—
ns
Input data set up time
DMUDS/DMLDS “H”
tsuDMD
I
30
—
ns
Input data hold time
DMUDS/DMLDS “H”
thDMD
J
5
—
ns
DREQ “L” → DREQ “H” return time
DMUDS/DMLDS “L” assert time
DMUDS/DMLDS “L” level pulse width
* : The position number indicates the position in the waveform.
DREQ
t RQAK
B
t DSRQ
A
C
t RQLH
DACK
D
t AKDS
H
t DSAK
DMR/W
E
t suRW
F
t hRW
G
t wDSL
DMUDS/DMLDS
I
t suDMD
DMD15 to DMD0
UDMDP, LDMDP
J
t hDMD
Data
31
MB86604L
(b) Read timing
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
DACK “L” assert time
DREQ “H”
tRQAK
A
0
—
ns
DREQ “L” negate time
DMUDS/DMLDS “L”
tDSRQ
B
—
55
ns
—
tRQLH
C
0
—
ns
DACK “L”
tAKDS
D
0
—
ns
DMR/W set up time
DMUDS/DMLDS “L”
tsuRW
E
20
—
ns
DMR/W hold time
DMUDS/DMLDS “H”
thRW
F
20
—
ns
—
twDSL
G
40
—
ns
DACK “H” negate time
DMUDS/DMLDS “H”
tDSAK
H
0
—
ns
Data output defined time
DMUDS/DMLDS “L”
tvDMD
I
—
40
ns
Data output hold time
DMUDS/DMLDS “H”
thDMD
J
10
—
ns
DREQ “L” → DREQ “H” return time
DMUDS/DMLDS “L” assert time
DMUDS/DMLDS “L” level pulse width
* : The position number indicates the position in the waveform.
DREQ
t RQAK
A
B
t DSRQ
C
t RQLH
DACK
D
t AKDS
H
t DSAK
DMR/W
F
t hRW
E
t suRW
G
t wDSL
DMUDS/DMLDS
t vDMD
I
J
DMD15 to DMD0
UDMDP, LDMDP
32
Valid data
t hDMD
MB86604L
(6) SCSI interface (as initiator)
• Asynchronous transfer mode
(a) Input timing (target → initiator)
Value
Parameter
Symbol
Base signal
Unit
Position*1
Min.
Max.
REQ “H” negate time
ACK “L”
tAKRQH
A
0
—
ns
ACK “H” negate time
REQ “H”
tRQAKH
B
—
60
ns
REQ “L” assert time
ACK “H”
tAKRQL
C
10
—
ns
Input data set up time
REQ “L”
tsuDB
D
10
—
ns
Input data hold time
REQ “L”
thDB
E
20
—
ns
ACK “L” assert time 1
REQ “L”
tRQAK1
F
—
40
ns
ACK “L” assert time 2 *2
REQ “H”
tRQAK2
G
—
3 tCLK + 40
ns
*1: The position number indicates the position in the waveform.
*2: The REQ “H” → ACK “L” time (tRQAK2) is compared with (tRQAKH + tAKRQL + tRQAK1) and the longer value is chosen.
Note: The input timing definition is not applied in the following cases.
• When the data register is FULL in the data phase
• When the final byte is being transferred
G
t RQAK2
REQ
A
t AKRQH
B
t RQAKH
C
t AKRQL
F
t RQAK1
ACK
D
t suDB
E
t hDB
DB7 to DB0
DBP
Data
33
MB86604L
(b) Output timing (initiator → target)
Value
Parameter
Symbol
Base signal
Unit
Position*1
Min.
Max.
REQ “H” negate time
ACK “L”
tAKRQH
A
0
—
ns
ACK “H” negate time
REQ “H”
tRQAKH
B
—
60
ns
REQ “L” assert time
ACK “H”
tAKRQL
C
10
—
ns
—
tDBAK
D
S • tCLK – 10
—
ns
Output data hold time
REQ “H”
thDB
E
2 tCLK
—
ns
ACK “L” assert time
REQ “L”
tRQAK1
F
—
40
ns
Time from output data valid to ACK “L” assert
*2
*1: The position number indicates the position in the waveform.
*2: “S” value is based on the asychronous set up time setting register (address 17h).
Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
(
'
&
%
t RQAK2
*
REQ
t AKRQH
A
B
t RQAKH
C
t AKRQL
F
t RQAK1
ACK
E
t hDB
D
t DBAK
DB7 to DB0
Valid data
D
t DBAK
Valid data
DBP
*: The REQ “H” → ACK “L” time (tRQAK2) is defined by either longer of (tRQAKH + tAKRQL + tRQAK1) or (thDB +
tDBAK) (see the output timing waveform).
34
MB86604L
• Synchronous transfer mode
(a) REQ/ACK signal period
Value
Parameter
Symbol
Base signal
Unit
Position*1
Min.
Max.
ACK assert time *2
—
tAKAP
A
A • tCLK – 12
—
ns
ACK negate time *2
—
tAKNP
B
N • tCLK + 2
—
ns
REQ assert time
—
tRQAP
C
20
—
ns
REQ negate time
—
tRQNP
D
20
—
ns
REQ input cycle time 1
—
tRQCY1
E
1 tCLK
—
ns
REQ input cycle time 2
—
tRQCY2
F
3 tCLK
—
ns
*1: The position number indicates the position in the waveform.
*2: “A” and “N” values are based on the transfer period register (address 0Dh) setting.
A
t AKAP
B
t AKNP
ACK
C
t RQAP
D
t RQNP
REQ
E
t RQCY1
F
t RQCY2
35
MB86604L
(b) Input timing (target → initiator)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Input data set up time
REQ “L”
tsuDB
A
5
—
ns
Input data hold time
REQ “L”
thDB
B
15
—
ns
* : The position number indicates the position in the waveform.
REQ
A
t suDB
B
t hDB
t suDB
A
B
t hDB
DB7 to DB0
Data
DBP
Data
(c) Input timing (target → initiator)
Value
Parameter
Symbol
Base signal
Time from output data valid to ACK “L” assert
*2
—
Unit
Position*1
Min.
Max.
A
N • tCLK + 2
—
tDBAK
,
+
*
)
6
5
4
!
,
+
*
)
(
6
5
4
3
!
,
+
*
)
(
6
5
4
3
%
$
#
"
!
0
/
.
ACK “L”
Output data hold time *2
thDB
B
A • tCLK – 12
*1: The position number indicates the position in the waveform.
*2: “A” and “N” values are based on the transfer period register (address 0Dh) setting.
ACK
A
t DBAK
DB7 to DB0
DBP
36
ns
B
t hDB
Valid data
A
t DBAK
B
t hDB
Valid data
—
ns
MB86604L
(7) SCSI interface (as initiator)
• Asynchronous transfer mode
(a) Input timing (initiator → target)
Value
Parameter
Symbol
Base signal
Unit
Position*1
Min.
Max.
ACK “L” assert time
REQ “L”
tRQAKL
A
0
—
ns
REQ “H” negate time
ACK “L”
tAKRQH
B
—
60
ns
ACK “H” negate time
REQ “H”
tRQAKH
C
0
—
ns
Input data set up time
ACK “L”
tsuDB
D
10
—
ns
Input data hold time
ACK “L”
thDB
E
20
—
ns
ACK “L” assert time 1
ACK “H”
tAKRQ1
F
—
40
ns
ACK “L” assert time 2 *2
ACK “H”
tALRQ2
G
—
3 tCLK + 40
ns
*1: The position number indicates the position in the waveform.
*2: The REQ “L” → REQ “L” time (tAKRQ2) is compared with (tAKRQH + tRQAKH + tAKRQ1) and the longer value is chosen.
Note: The input timing definition is not applied in the following cases.
• When the data register is FULL in the data phase
• When the final byte is being transferred
G
t AKRQ2
REQ
A
B
t RQAKL
t AKRQH
C
t RQAKH
F
t AKRQ1
ACK
t suDB
DB7 to DB0
D
E
t hDB
Data
DBP
37
MB86604L
(b) Output timing (target → initiator)
Value
Parameter
Symbol
Base signal
Unit
Position*1
Min.
Max.
ACK “L” assert time
REQ “L”
tRQAKL
A
0
—
ns
REQ “H” negate time
ACK “L”
tAKRQH
B
—
60
ns
ACK “H” negate time
REQ “H”
tRQAKH
C
0
—
ns
—
tDBRQ
D
S • tCLK – 10
—
ns
Output data hold time
ACK “L”
thDB
E
2 tCLK
—
ns
REQ “L” assert time
ACK “H”
tAKRQ1
F
—
40
ns
Time from output data valid to
REQ “L” assert *2
*1: The position number indicates the position in the waveform.
*2: “S” value is based on the asychronous set up time setting register (address 17h).
Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
+7
*
)
(
6
5
4
3
A
@
?
>
!
,
t AKRQ2
*
REQ
A
t RQAKL
B
t AKRQH
C
t RQAKH
F
t AKRQ1
ACK
E
t hDB
D
t DBRQ
DB7 to DB0
Valid data
D
t DBRQ
Valid data
DBP
*: The ACK “L” → REQ “L” time (tAKRQ2) is defined by either longer of (tAKRQH + tRQAKH + tAKRQ1) or (thDB + tDBRQ).
38
MB86604L
• Synchronous transfer mode
(a) REQ/ACK signal period
Value
Parameter
Symbol
Unit
Position*1
Min.
Max.
REQ assert time *2
tRQAP
A
A • tCLK – 12
—
ns
REQ negate time *2
tRQNP
B
N • tCLK + 2
—
ns
ACK assert time
tAKAP
C
20
—
ns
ACK negate time
tAKNP
D
20
—
ns
ACK input cycle time 1
tAKCY1
E
1 tCLK
—
ns
ACK input cycle time 2
tAKCY2
F
3 tCLK
—
ns
*1: The position number indicates the position in the waveform.
*2: “A” and “N” values are based on the transfer period register (address 0Dh). See (8) for more setting values.
A
t RQAP
B
t RQNP
REQ
C
t AKAP
D
t AKNP
ACK
E
t AKCY1
F
t AKCY2
39
MB86604L
(b) Input timing (initiator → target)
Value
Parameter
Symbol
Base signal
Unit
Position*
Min.
Max.
Input data set up time
ACK “L”
tsuDB
A
5
—
ns
Input data hold time
ACK “L”
thDB
B
15
—
ns
* : The position number indicates the position in the waveform.
ACK
t suDB
A
B
t hDB
t suDB
B
t hDB
A
DB7 to DB0
Data
Data
DBP
(c) Output timing (target → initiator)
Value
Parameter
Symbol
Base signal
Time from output data valid to
REQ “L” assert *2
—
Unit
Position*1
Min.
Max.
A
N • tCLK + 2
—
tDBRQ
ns
!
+
*
)
!
+
*
)
(
!
+
*
)
(
%
$
#
"
REQ “L”
Output data hold time *2
thDB
B
A • tCLK – 12
—
ns
*1: The position number indicates the position in the waveform.
*2: “A” and “N” values are based on the transfer period register (address 0Dh). See (8) for more setting values.
REQ
A
t DBRQ
DB7 to DB0
DBP
40
B
t hDB
Valid data
A
t DBRQ
B
t hDB
Valid data
MB86604L
(8) A/N/S values in the SCSI interface timing specification
• Transfer period register (address 0Dh) and A/N values
Transfer period register
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
N
Transfer period register
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
N
0
0
0
0
1
Prohibit
Prohibit
1
0
0
0
1
9
8
0
0
0
1
0
1
1
1
0
0
1
0
9
9
0
0
0
1
1
2
1
1
0
0
1
1
10
9
0
0
1
0
0
2
2
1
0
1
0
0
10
10
0
0
1
0
1
3
2
1
0
1
0
1
11
10
0
0
1
1
0
3
3
1
0
1
1
0
11
11
0
0
1
1
1
4
3
1
0
1
1
1
12
11
0
1
0
0
0
4
4
1
1
0
0
0
12
12
0
1
0
0
1
5
4
1
1
0
0
1
13
12
0
1
0
1
0
5
5
1
1
0
1
0
13
13
0
1
0
1
1
6
5
1
1
0
1
1
14
13
0
1
1
0
0
6
6
1
1
1
0
0
14
14
0
1
1
0
1
7
6
1
1
1
0
1
15
14
0
1
1
1
0
7
7
1
1
1
1
0
15
15
0
1
1
1
1
8
7
1
1
1
1
1
16
15
1
0
0
0
0
8
8
0
0
0
0
0
16
16
Note: The A and N values set in the register are the assert period and the negate period respectively (unit is clock
cycles)
For the AC characteristics, A/N use numerals.
• Asynchronous setup time register (address 17h) setting and the S value.
Asynchronous setup
time register
S
Bit 3 Bit 2 Bit 1 Bit 0
Asynchronous setup
time register
S
Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
1
1
1
0
0
1
9
0
0
1
0
2
1
0
1
0
10
0
0
1
1
3
1
0
1
1
11
0
1
0
0
4
1
1
0
0
12
0
1
0
1
5
1
1
0
1
13
0
1
1
0
6
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
0
0
0
8
0
0
0
0
16
Note: The S (setup time) value established in the set up time register during asynchronous data transfers indicates
the time from setting data in the data bus until the REQ/ACK signals are asserted.
For the AC characteristics, S uses numerals.
41
MB86604L
■ LIST OF REGISTERS
1. BASIC Control Registers (for write)
Address
Hex. A4 A3 A2 A1 A0
00
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0A
0
1
0
1
0
0B
0C
0D
0E
0F
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Register name
Output data register (first)
Output data register (second)
Direct control register
(Reserved)
SEL/RESEL ID register
Command register
Data block register (MSB)
Data block register (LSB)
Data byte register (MSB)
Data byte register
Data byte register (LSB)
MC byte register
Diagnostic control register
Transfer mode register
Transfer period register
Transfer offset register
Window address register
Bit assignment
Bit 5 Bit 4 Bit 3 Bit 2
DO5 DO4 DO3 DO2
DO13 DO12 DO11 DO10
0
DO4
0
0
0
0
0
0
0
0
0
SI2
CM5 CM4 CM3 CM2
BL13 BL12 BL11 BL10
BL5 BL4 BL3 BL2
BY21 BY20 BY19 BY18
BY13 BY12 BY11 BY10
Bit 7
DO7
DO15
DC7
0
SI7
CM7
BL15
BL7
BY23
BY15
Bit 6
DO6
DO14
0
0
0
CM6
BL14
BL6
BY22
BY14
Bit 1
DO1
DO9
0
0
SI1
CM1
BL9
BL1
BY17
BY9
Bit 0
DO0
DO8
0
0
SI0
CM0
BL8
BL0
BY16
BY8
BY7
BY6
BY5
BY4
BY3
BY2
BY1
BY0
DG7
TM7
0
0
WA7
DG6
0
0
0
WA6
DG5
0
0
0
0
0
0
TP4
TO4
0
DG3
0
TP3
TO3
WA3
DG2
0
TP2
TO2
WA2
DG1
0
TP1
TO1
WA1
DG0
0
TP0
TO0
WA0
Bit 6
DI6
DI14
SS6
NS6
IS6
CS6
BL14
BL6
BY22
BY14
Bit assignment
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DI5
DI4
DI3
DI2
DI1
DI0
DI13 DI12 DI11 DI10 DI9
DI8
SS5 SS4
X
SS2 SS1 SS0
NS5
X
X
NS2 NS1 NS0
IS5
IS4
IS3
IS2
IS1
IS0
CS5 CS4 CS3 CS2 CS1 CS0
BL13 BL12 BL11 BL10 BL9 BL8
BL5 BL4 BL3 BL2 BL1 BL0
BY21 BY20 BY19 BY18 BY17 BY16
BY13 BY12 BY11 BY10 BY9 BY8
BY6
BY5
BY4
BY3
BY2
BY1
BY0
SC6
X
X
X
X
SC5
X
X
X
MB5
SC4
X
TP4
TO4
BM4
SC3
X
TP3
TO3
MB3
SC2
X
TP2
TO2
MB2
SC1
X
TP1
TO1
MB1
SC0
X
TP0
TO0
MB0
2. BASIC Control Registers (for read)
Address
Bit 7
0 Input data register (first)
DI7
1 Input data register (second) DI15
0 SPC status register
SS7
1 Nexus status register
NS7
0 Interrupt status register
IS7
1 Command step register
CS7
0 Data block register (MSB)
BL15
1 Data block register (LSB)
BL7
0 Data byte register (MSB)
BY23
1 Data byte register
BY15
Data byte register (LSB)
0
BY7
MC byte register
1 SCSI control signal status register SC7
0 Transfer mode register
TM7
1 Transfer period register
X
0 Transfer offset register
X
1 Modified byte register
X
Hex. A4 A3 A2 A1 A0
00
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0A
0
1
0
1
0B
0C
0D
0E
0F
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
Register name
Note: X indicates data is undefined. (0 or 1).
42
MB86604L
3. Initial Setting Window (for read/write)
Address
Bit assignment
Register name
Hex. A4 A3 A2 A1 A0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
10
1
0
0
0
0 Clock conversion setting
CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0
11
1
0
0
0
1 Self ID setting
12
1
0
0
1
0 Response mode setting
13
1
0
0
1
1 Selection/reselection mode setting SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0
14
1
0
1
0
0 Selection/reselection retry setting
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
15
1
0
1
0
1 Selection/reselection timeout setting
ST7
16
1
0
1
1
0 REQ/ACK timeout setting
RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0
17
1
0
1
1
1 Asynchronous setup time setting
18
1
1
0
0
0 Parity error detection setting
PE7 PE6 PE5 PE4 PE3
19
1
1
0
0
1 Interrupt enable setting
IE7
1A
1
1
0
1
0 Group 6/7 command length setting GL7 GL6 GL5 GL4 GL3 GL2 GL1 GL0
1B
1
1
0
1
1 DMA system setting
1C
1
1
1
0
0 Automatic operation mode setting
OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0
1D
1
1
1
0
1 SPC Timeout setting
TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0
1F
1
1
1
1
1 Device revision indication
RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0
0
0
0
0
AM7 AM6 AM5 AM4
0
0
ST6
0
0
0
ST5
0
IE5
ST4
0
IE4
DM5 MD4
0
OI2
0
0
ST3
AT3
IE3
0
ST2
AT2
0
IE2
0
OI1
OI0
AM1 AM0
ST1
AT1
ST0
AT0
PE1 PE0
IE1
0
IE0
0
4. MCS Buffer Window
Address
For write
For read
0
SEND MCS buffer
RECEIVE MCS buffer
0
1
SEND MCS buffer
RECEIVE MCS buffer
0
1
0
SEND MCS buffer
RECEIVE MCS buffer
0
0
1
1
SEND MCS buffer
RECEIVE MCS buffer
1
0
1
0
0
SEND MCS buffer
RECEIVE MCS buffer
15
1
0
1
0
1
SEND MCS buffer
RECEIVE MCS buffer
16
1
0
1
1
0
SEND MCS buffer
RECEIVE MCS buffer
17
1
0
1
1
1
SEND MCS buffer
RECEIVE MCS buffer
18
1
1
0
0
0
SEND MCS buffer
RECEIVE MCS buffer
19
1
1
0
0
1
SEND MCS buffer
RECEIVE MCS buffer
1A
1
1
0
1
0
SEND MCS buffer
RECEIVE MCS buffer
1B
1
1
0
1
1
SEND MCS buffer
RECEIVE MCS buffer
1C
1
1
1
0
0
SEND MCS buffer
RECEIVE MCS buffer
1D
1
1
1
0
1
SEND MCS buffer
RECEIVE MCS buffer
1E
1
1
1
1
0
SEND MCS buffer
RECEIVE MCS buffer
1F
1
1
1
1
1
SEND MCS buffer
RECEIVE MCS buffer
Hex.
A4
A3
A2
A1
A0
10
1
0
0
0
11
1
0
0
12
1
0
13
1
14
43
MB86604L
5. User Program Memory Window
Address
44
For write
For read
0
User program memory
User program memory
0
1
User program memory
User program memory
0
1
0
User program memory
User program memory
0
0
1
1
User program memory
User program memory
1
0
1
0
0
User program memory
User program memory
15
1
0
1
0
1
User program memory
User program memory
16
1
0
1
1
0
User program memory
User program memory
17
1
0
1
1
1
User program memory
User program memory
18
1
1
0
0
0
User program memory
User program memory
19
1
1
0
0
1
User program memory
User program memory
1A
1
1
0
1
0
User program memory
User program memory
1B
1
1
0
1
1
User program memory
User program memory
1C
1
1
1
0
0
User program memory
User program memory
1D
1
1
1
0
1
User program memory
User program memory
IE
1
1
1
1
0
User program memory
User program memory
1F
1
1
1
1
1
User program memory
User program memory
Hex.
A4
A3
A2
A1
A0
10
1
0
0
0
11
1
0
0
12
1
0
13
1
14
MB86604L
■ LIST OF COMMANDS
SPC commands can be specified in the command register or the user program memory and divided into the following
main groups.
• Sequential commands
Commands that perform a consecutive (including phase transitions) sequence operation. Can only be specified
in the command register (1-byte).
• Discrete commands
Commands which perform operations from disassembled sequential commands. Can be specified in the
command register (1-byte command) or the user program memory (1/2-byte command).
• Special commands
Can only be specified in the user program memory (1/2-byte command).
1. Initiator Commands
(1) Sequential commands
No
Command code
Operand (for program)
Command name
1
00H
0
0
0
0
0
0
0
0
(not possible)
Select & CMD
2
01H
0
0
0
0
0
0
0
1
(not possible)
Select & 1-MSG & CMD
3
02H
0
0
0
0
0
0
1
0
(not possible)
Select & N-Byte-MSG & CMD
4
03H
0
0
0
0
0
0
1
1
(not possible)
Select & 1-MSG
5
04H
0
0
0
0
0
1
0
0
(not possible)
Select & N-Byte-MSG
6
05H
0
0
0
0
0
1
0
1
(not possible)
Send N-Byte-MSG
7
06H
0
0
0
0
0
1
1
0
(not possible)
Send N-Byte-CMD
8
07H
0
0
0
0
0
1
1
1
(not possible)
Receive N-Byte-MSG
45
MB86604L
(2) Discrete commands
No
46
Command code
Operand (for program)
Command name
9
08H
0
0
0
0
1
0
0
0
—
Select
10
09H
0
0
0
0
1
0
0
1
—
Select with ATN
11
0AH
0
0
0
0
1
0
1
0
—
Set ATN
12
0BH
0
0
0
0
1
0
1
1
—
Reset ATN
13 0CH 0
0
0
0
1
1
0
0
—
Set ACK
14 0DH 0
0
0
0
1
1
0
1
—
Reset ACK
15
10H
0
0
0
1
0
0
0
0
—
Send Data from MPU
16
11H
0
0
0
1
0
0
0
1
—
Send Data from DMA
17
12H
0
0
0
1
0
0
1
0
—
Receive Data to MPU
18
13H
0
0
0
1
0
0
1
1
—
Receive Data to DMA
19
14H
0
0
0
1
0
1
0
0
—
Send DATA from MPU Padding
20
15H
0
0
0
1
0
1
0
1
—
Send DATA from DMA Padding
21
16H
0
0
0
1
0
1
1
0
—
Receive Data to MPU Padding
22
17H
0
0
0
1
0
1
1
1
—
Receive Data to DMA Padding
23
18H
0
0
0
1
1
0
0
0 Address of MSG sent
Send 1-MSG
24
19H
0
0
0
1
1
0
0
1 Address of MSG sent
Send 1-MSG with ATN
25
1AH
0
0
0
1
1
0
1
0 SAVE address of MSG
Receive MSG
26
1BH
0
0
0
1
1
0
1
1 Address of CMD sent
Send CMD
27 1CH 0
0
0
1
1
1
0
0 SAVE address of STATUS Receive STATUS
MB86604L
2. Target Commands
(1) Sequential commands
No
Command code
Operand (for program)
Command name
1
20H
0
0
1
0
0
0
0
0
(not possible)
Reselect & 1-MSG
2
21H
0
0
1
0
0
0
0
1
(not possible)
Reselect & N-Byte-MSG
3
22H
0
0
1
0
0
0
1
0
(not possible)
Reselect & 1-MSG & Terminate
4
23H
0
0
1
0
0
0
1
1
(not possible)
Reselect & 1-MSG & Link-Terminate
5
24H
0
0
1
0
0
1
0
0
(not possible)
Terminate
6
25H
0
0
1
0
0
1
0
1
(not possible)
Link-Terminate
7
26H
0
0
1
0
0
1
1
0
(not possible)
Disconnect-Sequence
8
27H
0
0
1
0
0
1
1
1
(not possible)
Send N-Byte-MSG
9
28H
0
0
1
0
1
0
0
0
(not possible)
Receive N-Byte-CMD
10
29H
0
0
1
0
1
0
0
1
(not possible)
Receive N-Byte-MSG
11
2AH
0
0
1
0
1
0
1
0
(not possible)
Reselect & N-Byte-MSG & Terminate
12
2BH
0
0
1
0
1
0
1
1
(not possible)
Reselect & N-Byte-MSG & Link-Terminate
13 2CH 0
0
1
0
1
1
0
0
(not possible)
Disconnect-Sequence 2
47
MB86604L
(2) Discrete commands
No
Command code
Operand (for program)
Command name
14
30H
0
0
1
1
0
0
0
0
—
Reselect
15
31H
0
0
1
1
0
0
0
1
—
Set REQ
16
32H
0
0
1
1
0
0
1
0
—
Reset REQ
17
33H
0
0
1
1
0
0
1
1
—
Disconnect
18
34H
0
0
1
1
0
1
0
0
—
Send Data from MPU
19
35H
0
0
1
1
0
1
0
1
—
Send Data from DMA
20
36H
0
0
1
1
0
1
1
0
—
Receive Data to MPU
21
37H
0
0
1
1
0
1
1
1
—
Receive Data to DMA
22
38H
0
0
1
1
1
0
0
0 Address of MSG sent
Send 1 MSG
23
39H
0
0
1
1
1
0
0
1 SAVE address of MSG
Receive MSG
24
3AH
0
0
1
1
1
0
1
0 Send-status address
Send Status
25
3BH
0
0
1
1
1
0
1
1 SAVE address of CDB
Receive CMD
3. Common Commands
No
48
Command code
Operand (for program)
Command name
1
40H
0
1
0
0
0
0
0
0
(not possible)
SOFTWARE RESET
2
41H
0
1
0
0
0
0
0
1
(not possible)
TRANSFER RESET
3
42H
0
1
0
0
0
0
1
0
(not possible)
SCSI RESET
4
43H
0
1
0
0
0
0
1
1
(not possible)
SET UP REG
5
44H
0
1
0
0
0
1
0
0
(not possible)
INIT DIAG START
6
45H
0
1
0
0
0
1
0
1
(not possible)
TARG DIAG START
7
46H
0
1
0
0
0
1
1
0
(not possible)
DIAG END
8
47H
0
1
0
0
0
1
1
1
(not possible)
COMMAND PAUSE
9
48H
0
1
0
0
1
0
0
0
(not possible)
SET RST
10
49H
0
1
0
0
1
0
0
1
(not possible)
RESET RST
MB86604L
4. Programmable Commands
The user program is stored in the user program memory and begins operation when the user program head address
is written in the command register.
Programmable commands are composed of discrete and special commands and have a command length of one
(1) or two (2) bytes.
• Command field assign
Command type
Discrete commands
Special commands
Command code (1st byte)
Operand (2nd byte)
Message, command, or status phases
send command
Memory address of the data to be sent.
Message, command, or status phases
receive command
Memory address of received data being
stored.
Data phase receive/send command or
do not perform transfer command
—
AND command
Data for AND operation or memory
address of data for AND operation.
TEST AND command
Data for AND operation or memory
address of data for AND operation.
COMPARE command
Data for COMPARE operation or
memory address of data for COMPARE
operation.
Conditional branch command
Jump head address
MOVE command
Memory address to be moved.
STOP command
User status code
NOP command
—
49
MB86604L
■ SYSTEM CONFIGURATION EXAMPLE
1. 80-Series, Separate Bus Type
MB86604L
Oscillation
circuit
RESET
circuit
CLK
RESET
DB7 to 0
DBP
MODE
INT
MPU
TMOUT
CS0
ACK
CS1
Address
decoder
ATN
A4 to A0
Address bus
SCSI bus
REQ
D15 to D0
MSG
C/D
Data bus
UDP
LDP
BHE
I/O
RD
WR
DMD15 to 0
UDMDP
LDMDP
DMA bus
BSY
DREQ
SEL
DACK
DMBHE
IORD
RST
IOWR
DMA0
TP
50
DMA
controller
Address
DATA
buffer
memory
MB86604L
2. 80-Series, Common Bus Type
MB86604L
Oscillation
circuit
RESET
circuit
CLK
RESET
DB7 to 0
DBP
MODE
INT
MPU
TMOUT
CS1
ACK
CS0
Address
decoder
ATN
A4 to A0
Address bus
SCSI bus
REQ
D15 to D0
MSG
C/D
Data bus
UDP
LDP
BHE
I/O
RD
WR
DMD15 to 0
UDMDP
LDMDP
DMA bus
BSY
DREQ
SEL
DACK
DMBHE
DMA
controller
IORD
RST
IOWR
DMA0
TP
51
MB86604L
3. 68-Series, Separate Bus Type
Oscillation
circuit
MB86604L
RESET
circuit
CLK
RESET
DB7 to 0
DBP
MODE
INT
MPU
TMOUT
A0
CS0
ACK
CS1
Address
decoder
ATN
A4 to A1
Address bus
SCSI bus
REQ
D15 to D0
MSG
C/D
Data bus
UDP
LDP
R/W
I/O
UDS
LDS
DMD15 to 0
UDMDP
LDMDP
DMA bus
BSY
DREQ
SEL
DACK
DMR/W
DMUDS
RST
DMLDS
DMA0
TP
52
DMA
controller
Address
DATA
buffer
memory
MB86604L
4. 68-Series, Common Bus Type
MB86604L
Oscillation
circuit
RESET
circuit
CLK
RESET
DB7 to 0
DBP
MODE
INT
MPU
TMOUT
A0
CS1
ACK
CS0
Address
decoder
ATN
A4 to A1
Address bus
SCSI bus
REQ
D15 to D0
MSG
C/D
Data bus
UDP
LDP
R/W
I/O
UDS
LDS
DMD15 to 0
UDMDP
LDMDP
DMA bus
BSY
DREQ
SEL
DACK
DMR/W
DMA
controller
DMUDS
RST
DMLDS
DMA0
TP
53
MB86604L
■ ORDERING INFORMATION
Part number
MB86604LPFV
54
Package
100 pin Plastic LQFP
(FPT-100P-M05)
Remarks
MB86604L
■ PACKAGE DIMENSION
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 −0.10 (MOUNTING HEIGHT)
+.008
.059 −.004
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
"B"
25
1
0.40(.016)MAX
"A"
0.50(.0197)TYP
+0.08
0.18 −0.03
+.003
.007 −.001
+0.05
0.08(.003)
M
0.127 −0.02
+.002
.005 −.001
Details of "B" part
0.10±0.10
(STAND OFF)
(.004±.004)
0.10(.004)
C
1995 FUJITSU LIMITED F100007S-2C-3
0.50±0.20(.020±.008)
0~10˚
Dimensions in mm (inches)
55
MB86604L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any
license under the copyrights, patent rights or trademarks claimed
and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications
without notice.
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9702
 FUJITSU LIMITED Printed in Japan
56