FINAL COM’L: -7/10/15 Advanced Micro Devices PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS ■ As fast as 7.5-ns propagation delay and 91 MHz fMAX (external) ■ 10 Macrocells programmable as registered or combinatorial, and active high or active low to match application needs ■ Varied product term distribution allows up to 16 product terms per output for complex functions ■ Global asynchronous reset and synchronous preset for initialization ■ Power-up reset for initialization and register preload for testability ■ Extensive third-party software and programmer support through FusionPLD partners ■ 24-Pin SKINNYDIP, 24-pin Flatpack and 28-pin PLCC and LCC packages save space GENERAL DESCRIPTION The PAL22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PAL22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to 16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be pro- grammed as registered or combinatorial, and active high or active low. The output configuration is determined by two fuses controlling two multiplexers in each macrocell. AMD’s FusionPLD program allows PAL22V10 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar. BLOCK DIAGRAM I1 - I11 CLK/I0 1 11 Programmable AND Array (44 x 132) 8 10 12 OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL 14 16 16 14 OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL 12 10 8 RESET OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL PRESET I/O0 Publication# 16559 Rev. C Issue Date: February 1996 I/O1 I/O2 Amendment /0 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 16559C-1 2-197 AMD CONNECTION DIAGRAMS Top View 2 1 CLK/I0 1 24 I1 2 23 I/O9 I2 3 22 I/O8 I3 4 21 I/O7 I3 5 25 I/O7 I4 5 20 I/O6 I4 6 24 I/O6 I5 6 19 I/O5 I5 7 23 I/O5 I6 7 18 I/O4 NC 8 22 NC I7 8 17 I/O3 I6 9 21 I/O4 I8 9 16 I/O2 20 10 15 I7 10 I9 I/O3 I/O1 I10 19 14 I8 11 11 I/O2 I/O0 GND 12 13 I11 VCC PIN DESIGNATIONS = Clock GND = Ground = Input I/O = Input/Output NC = No Connect VCC = Supply Voltage 2-198 PAL22V10 Family I/O1 I/O0 I11 NC GND I10 I9 Note: Pin 1 is marked for orientation. I 28 27 26 12 13 14 15 16 17 18 16559C-2 CLK I/O8 NC 3 I/O9 CLK/I0 4 VCC I1 PLCC/LCC I2 SKINNYDIP/FLATPACK 16559C-3 AMD ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL 22 V 10 -7 P C FAMILY TYPE PAL or AmPAL = Programmable Array Logic OPTIONAL PROCESSING Blank = Standard Processing NUMBER OF ARRAY INPUTS OPERATING CONDITIONS C = Commercial (0°C to +75°C) OUTPUT TYPE V = Versatile PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) NUMBER OF OUTPUTS SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD A = 25 ns tPD Valid Combinations PAL22V10-7 PAL22V10-10 PAL22V10-15 PC, JC Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AmPAL22V10A PAL22V10-7/10/15, AmPAL22V10A (Com’l) 2-199 AMD FUNCTIONAL DESCRIPTION The PAL22V10 allows the systems engineer to implement a design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required timeconsuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. Product terms with all fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PAL22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations; registered output or combinatorial I/O, active high or active low (see Figure 2). The configuration choice is made according to the user’s design AR 1 0 1 1 D Q 0 0 Q 0 1 CLK SP specification and corresponding programming of the configuration bits S0 – S1. Multiplexer controls initially are connected to ground (0) through a programmable fuse, selecting the “0” path through the multiplexer. Programming the fuse disconnects the control line from GND and it is driven to a high level, selecting the “1” path. The device is produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Variable Input/Output Pin Ratio The PAL22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. I/On S1 S0 0 1 S1 S0 Output Configuration 0 0 1 1 0 1 0 1 Registered/Active Low Registered/Active High Combinatorial/Active Low Combinatorial/Active High 0 = Unprogrammed fuse 1 = Programmed fuse 16559C-4 Figure 1. Output Logic Macrocell Diagram 2-200 PAL22V10 Family AMD Registered Output Configuration Combinatorial I/O Configuration Each macrocell of the PAL22V10 includes a D-type flipflop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration the feedback is from the pin. S0 = 0 S1 = 0 AR D S0 = 0 S1 = 1 Q Q CLK SP Combinatorial/Active Low Registered/Active Low S0 = 1 S1 = 0 AR D S0 = 1 S1 = 1 Q Q CLK SP Combinatorial/Active High Registered/Active High 16559C-5 Figure 2. Macrocell Configuration Options Programmable Three-State Outputs Preset/Reset Each output has a three-state output buffer with threestate control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always disabled. For initialization, the PAL22V10 has Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock. Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL22V10 will depend on the programmed output polarity. The VCC rise must be monotonic and the reset delay time is 1000 ns maximum. PAL22V10 Family 2-201 AMD Register Preload Quality and Testability The register on the PAL22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The PAL22V10 offers a very high level of built-in quality. Extra programmable fuses, test words and test columns provide a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Security Fuse After programming and verification, a PAL22V10 design can be secured by programming the security fuse. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed, and preload will be disabled. Programming Technology The AmPAL22V10A is fabricated with AMD’s diffusionisolated bipolar process. The array connections are formed with highly reliable PtSi fuse. The PAL22V10-15, -10 and -7 are fabricated with AMD’s diffusion-isolated bipolar process. This process reduces parasitic capacitances and minimum geometries to provide higher performance. The array connections are formed with PtSi fuses on the -15, and TiW fuses on the -7 and -10 for reliable operation. The PAL22V10 can be programmed on standard logic programmers. Approved programmers are listed at the end of this data book. 2-202 PAL22V10 Family AMD LOGIC DIAGRAM SKINNYDIP (PLCC/LCC) Pinouts CLK/I 0 1 (2) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 24 (28) VCC 43 AR 0 1 1 D AR 9 Q Q 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 23 I/O 9 (27) SP 0 1 10 D AR Q 20 Q 22 I/O 8 (26) SP I1 0 1 2 (3) 21 D AR Q Q 33 I2 3 (4) 21 I/O 7 (25) SP 0 1 34 D AR Q Q 20 I/O 6 (24) SP 48 I3 4 (5) 0 1 49 D AR Q Q 19 I/O 5 (23) SP 65 I4 5 (6) 0 1 66 D AR Q Q 18 I/O 4 (21) SP 82 I5 6 (7) 0 1 83 D AR Q Q 17 I/O 3 (20) SP 97 I6 7 (9) 0 1 98 D AR Q Q SP 110 I7 8 (10) 0 1 111 D AR Q Q 121 I8 9 (11) 16 I/O 2 (19) 15 I/O 1 (18) SP 0 1 122 D AR Q 130 Q 14 I/O 0 (17) SP I9 10 (12) I 11 (13) 10 0 1 SP 131 13 GND I11 (16) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 12 (14) 16559C-6 PAL22V10 Family 2-203 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –1.2 V to VCC + 0.5 V DC Output or I/O Pin Voltage . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current VIN = 2.7 V, VCC = Max (Note 2) IIL II Input LOW Current Min Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.2 V 25 µA VIN = 0.4 V, VCC = Max Input –100 µA (Note 2) CLK –150 Maximum Input Current VIN = 5.5 V, VCC = Max 1 mA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 220 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-204 PAL22V10-7 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ VCC = 5.0 V TA = 25°C f = 1 MHz Unit 6 5 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min (Note 3) Max Unit 7.5 ns tPD Input or Feedback to Combinatorial Output 1 tS Setup Time from Input, Feedback or SP to Clock 5 ns tH Hold Time 0 ns Clock to Output 1 tCO tSKEWR tAR 6 ns Skew Between Registered Outputs (Note 5) 1 ns Asynchronous Reset to Registered Output 12 ns tARW Asynchronous Reset Width 8 ns tARR Asynchronous Reset Recovery Time 8 ns tSPR Synchronous Preset Recovery Time 5 ns LOW 4 ns HIGH 4 ns tWL Clock Width tWH fMAX Maximum Frequency (Note 4) External Feedback 1/(tS + tCO) 91 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 6) 100 MHz No Feedback 1/(tWH + tWL) 125 MHz tEA Input to Output Enable Using Product Term Control 8 ns tER Input to Output Disable Using Product Term Control 7.5 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums are measured under best-case conditions. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. Skew is measured with all outputs switching in the same direction. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL22V10-7 (Com’l) 2-205 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –1.2 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current VIN = 2.7 V, VCC = Max (Note 2) IIL Input LOW Current II Min Max 2.4 V 0.5 2.0 0.8 V –1.2 V 25 µA µA VIN = 0.4 V, VCC = Max Input –100 CLK –150 VIN = 5.5 V, VCC = Max IOZH Off-State Output Leakage Current HIGH IOZL V V (Note 2) Maximum Input Current Unit 1 mA VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 180 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-206 PAL22V10-10 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ VCC = 5.0 V TA = 25°C f = 1 MHz Unit 6 5 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min (Note 3) Max Unit 10 ns tPD Input or Feedback to Combinatorial Output 1 tS Setup Time from Input, Feedback or SP to Clock 7 ns tH Hold Time 0 ns tCO Clock to Output 1 tAR Asynchronous Reset to Registered Output 7 ns 15 ns tARW Asynchronous Reset Width 10 ns tARR Asynchronous Reset Recovery Time 8 ns tSPR Synchronous Preset Recovery Time 8 ns LOW 5 ns HIGH 5 ns tWL tWH fMAX Clock Width Maximum Frequency (Note 4) External Feedback 1/(tS + tCO) 71 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) 80 MHz No Feedback 1/(tWH + tWL) 100 MHz tEA Input to Output Enable Using Product Term Control 11 ns tER Input to Output Disable Using Product Term Control 9 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums are measured under best-case conditions. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL22V10-10 (Com’l) 2-207 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Input Current . . . . . . . . . . . . . –30 mA to +5 mA Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.2 V VIN = 2.7 V, VCC = Max (Note 2) 25 µA Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –100 µA Maximum Input Current VIN = 5.5 V, VCC = Max 1 mA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 180 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-208 PAL22V10-15 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit 9 6 5 pF VCC = 5.0 V TA = 25°C f = 1 MHz Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Min (Note 3) Parameter Description Max Unit 15 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 10 ns tH Hold Time 0 ns tCO Clock to Output 10 ns tAR Asynchronous Reset to Registered Output 20 ns tARW Asynchronous Reset Width 15 ns tARR Asynchronous Reset Recovery Time 10 ns tSPR Synchronous Preset Recovery Time 10 ns LOW 6 ns HIGH 6 ns tWL Clock Width tWH fMAX Maximum Frequency (Note 4) External Feedback 1/(tS + tCO) 50 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) 80 MHz No Feedback 1/(tWH + tWL) 83 MHz tEA Input to Output Enable Using Product Term Control 15 ns tER Input to Output Disable Using Product Term Control 15 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums are measured under best-case conditions. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL22V10-15 (Com’l) 2-209 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . . . . –0.5 V to +5.5 V DC Input Current . . . . . . . . . . . . . . –30 mA to +5 mA Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . –0.5 V to VCC Max Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL Input LOW Current II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.2 V VIN = 2.7 V, VCC = Max (Note 2) 25 µA VIN = 0.4 V, VCC = Max (Note 2) –100 µA Maximum Input Current VIN = 5.5 V, VCC = Max 1 mA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –90 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 180 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-210 AmPAL22V10A (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit 11 6 pF VCC = 5.0 V TA = 25°C f = 1 MHz 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Unit 25 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 20 ns tH Hold Time 0 ns tCO Clock to Output 15 ns tAR Asynchronous Reset to Registered Output 30 ns tARW Asynchronous Reset Width 25 ns tARR Asynchronous Reset Recovery Time 35 ns tSPR Synchronous Preset Recovery Time 20 ns LOW 15 ns HIGH 15 ns 28.5 MHz tWL Clock Width tWH fMAX Maximum Frequency (Note 3) External Feedback 1/(tS + tCO) tEA Input to Output Enable Using Product Term Control 25 ns tER Input to Output Disable Using Product Term Control 25 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. AmPAL22V10A (Com’l) 2-211 AMD SWITCHING WAVEFORMS Input or Feedback VT tS Input or Feedback VT tH Clock VT tCO tPD Combinatorial Output Registered Output VT VT 16559C-8 16559C-7 Combinatorial Output Registered Output Input or Feedback tWH VT tER Clock VT tEA VOH - 0.5V Output VT VOL + 0.5V tWL 16559C-10 16559C-9 Clock Width Input Asserting Asynchronous Reset Input to Output Disable/Enable Input Asserting Synchronous Preset tARW VT tS tAR Registered Output VT VT tH tSPR VT Clock tARR Clock VT tCO Registered Output VT 16559C-11 Asynchronous Reset Synchronous Preset Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns – 4 ns typical. 2-212 16559C-12 PAL22V10 Family AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 16559C-13 Commercial Specification tPD, tCO tEA tER S1 CL R1 Closed Z → H: Open Z → L: Closed 50 pF H → Z: Open 5 pF 300 Ω L → Z: Closed PAL22V10 Family R2 Measured Output Value All except -7: 1.5 V 390 Ω 1.5 V -7: H → Z: VOH – 0.5 V 300 Ω L → Z: VOL + 0.5 V 2-213 AMD MEASURED SWITCHING CHARACTERISTICS for the PAL22V10-10 VCC = 4.75 V, TA = 75°C (Note 1) 10 9 tPD, ns 8 7 1 2 3 4 5 6 7 8 9 10 Number of Outputs Switching tPD vs. Number of Outputs Switching 16559C-14 13 12 11 10 tPD, ns 9 8 7 0 40 80 120 160 200 CL, pF tPD vs. Load Capacitance 16559C-15 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tPD may be affected. 2-214 PAL22V10-10 AMD INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC Input Program/Verify Circuitry 16559C-16 Typical Input VCC 40 Ω NOM Output Input, I/O Pins Program/Verify/ Test Circuitry Preload Circuitry 16559C-17 Typical Output PAL22V10 Family 2-215 AMD POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC Parameter Symbol can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: ■ The VCC rise must be monotonic. ■ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description Max Unit tPR Power-up Reset Time 1000 ns tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC Power 4V tPR Registered Active-Low Output tS Clock 16559C-18 tWL Power-Up Reset Waveform 2-216 PAL22V10 Family