May 2001 AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0 Preliminary ® 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank select) • High speed - 143/125/100 MHz - 7/8/10 ns clock access time - 400 mil, 44-pin TSOP 2 (2M × 8) - 400 mil, 50-pin TSOP 2 (1M × 16) • Low power consumption • Read/write data masking • Programmable burst length (1/2/4/8/ full page) • Programmable burst sequence (sequential/interleaved) • Programmable CAS latency (1/2/3) - Active: 576 mW max - Standby: 7.2 mW max, CMOS I/O • 2048 refresh cycles, 32 ms refresh interval • 4096 refresh cycles, 64 ms refresh interval Pin arrangement Pin designation LEGEND Configuration Refresh Count Row Address Bank Address Column Address VSS DQ7 VSSQ DQ6 VCCQ DQ5 VSSQ DQ4 VCCQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TSOP 2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 AS4LC1M16S0 and AS4LC1M16S1 DQ1 VCCQ DQ2 VSSQ DQ3 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AS4LC2M8S1 and AS4LC2M8S0 TSOP 2 VCC DQ0 VSSQ • Auto refresh and self refresh • PC100 functionality • Automatic and direct precharge including concurrent autoprecharge • Burst read, write/Single write • Random column address assertion in every cycle, pipelined operation • LVTTL compatible I/O • 3.3V power supply • JEDEC standard package, pinout and function 2M × 8 1M × 8 × 2 banks 2K/4K (A0 – A10) 2 (BA) 512 (A0 – A8) VSS DQ15 DQ14 VSSQ DQ13 DQ12 VCCQ DQ11 DQ10 VSSQ DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS Pin(s) Description DQM (2M × 8) UDQM/LDQM (1M × 16) Output disable/write mask A0 to A10 RA0 – 10 Address inputs CA0 – 7 (×16) CA0 – 8 (×8) A11 Bank address (BA) DQ0 to DQ7 (2M × 8) DQ0 to DQ15 (1M × 16) Input/output RAS Row address strobe CAS Column address strobe WE Write enable CS Chip select VCC, VCCQ Power (3.3V ± 0.3V) VSS, VSSQ Ground CLK Clock input CKE Clock enable 1M × 16 512K × 16 × 2 banks 2K/4K (A0 – A10) 2 (BA) 256 (A0 – A7) Selection guide Symbol –7 –8 –10 Unit Bus frequency (CL = 3) fMax 143 125 100 MHz Maximum clock access time (CL = 3) tAC 5.5 6 6 ns Minimum input setup time tS 2 2 2 ns Minimum input hold time tH 1.0 1.0 1.0 ns Row cycle time (CL = 3, BL = 1) tRC 70 80 80 ns Maximum operating current ([×16], RD or WR, CL = 3), BL = 2 ICC1 130 100 100 mA Maximum CMOS standby current, self refresh ICC6 1 1 1 mA 5/21/01; v.1.1 Alliance Semiconductor P. 1 of 29 Copyright ©Alliance Semiconductor. All rights reserved. AS4LC2M8S1 AS4LC1M16S1 ® Functional description The AS4LC2M8S1, AS4LC2M8S0, and AS4LC1M16S1, AS4LC1M16S0 are high-performance 16-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 1,048,576 words × 8 bits × 2 banks (2048 rows × 512 columns) and 524,288 words × 16 bits × 2 banks (2048 rows × 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data (512 bytes for 2M × 8 and 256 bytes for 1M × 16) without selecting a new column address. The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless operation; and (3) the capability to change column-address randomly on every clock cycle during burst access. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. SDRAM commands and functions are decoded from control inputs. Basic commands are as follows: • Mode register set • Deactivate bank • Deactivate all banks • Select row; activate bank • Select column; write • Select column; read • Deselect; power down • CBR refresh • Auto precharge with read/write • Self-refresh Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1/ AS4LC2M8S0 have 44 pins, and the AS4LC1M16S1/ AS4LC1M16S0 have 50 pins. All devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL compatible. Logic block diagram CLK Clock generator CKE A11 A[10:0] Row address buffer Mode register Refresh counter Row decoder Bank select Bank A† 512K × 16 (2048 × 256 × 16) Bank B† 512K × 16 (2048 × 256 × 16) Burst counter Data control circuit Input and output buffer WE Column address buffer DQMU/DQML Column decoder and latch circuit Latch circuit CAS Control logic RAS Command decoder Sense amplifier CS DQ † For AS4LC2M8S1/AS4LC2M8S0, Banks A and B will read 1M × 8 (2048 × 512 × 8). 5/21/01; v.1.1 Alliance Semiconductor P. 2 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Pin descriptions Pin Name Description CLK System clock All operations synchronized to rising edge of CLK. CKE Clock enable Controls CLK input. If CKE is high, the next CLK rising edge is valid. If CKE is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. If both banks are idle and CKE goes low, the SDRAM will enter power down mode from the next clock cycle. When in power down mode and CKE is low, no input commands will be acknowledged. To exit power down mode, raise CKE high before the rising edge of CLK. CS Chip select Enables or disables device operation by masking or enabling all inputs except CLK, CKE, UDQM/LDQM (×16), DQM (×8). A0~A10 Address Row and column addresses are multiplexed. Row address: A0~A10. Column address (2M × 8): A0~A8. Column address (1M × 16): A0~A7. A11 Bank select Memory cell array is organized in 2 banks. A11 selects which internal bank will be active. A11 is latched during bank activate, read, write, mode register set, and precharge operations. Asserting A11 low selects Bank A; A11 high selects Bank B. RAS CAS WE Row address strobe Column address strobe Write enable ×8: DQM ×16: UDQM, LDQM Output disable/ write mask DQ0~DQ15 Data input/output VCC/VSS Power supply/ground VCCQ/VSSQ Data output power/ground 5/21/01; v.1.1 Command inputs. RAS, CAS, and WE, along with CS, define the command being entered. Controls I/O buffers. When DQM is high, output buffers are disabled during a read operation and input data is masked during a write operation. DQM latency is 2 clocks for Read and 0 clocks for Write. For ×16, LDQM controls the lower byte (DQ0 – 7) and UDQM controls the upper byte (DQ8 – 15). UDQM and LDQM are considered to be in the same state when referred to jointly as DQM. Data inputs/outputs are multiplexed. Power and ground for core logic and input buffers. Power and ground for data output buffers. Alliance Semiconductor P. 3 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Operating modes Command CKEn-1 CKEn WE DQM A11 A10 A9–A0 Note X L L L L X Op code 1,2 Auto refresh H H L L L H X X 3 Entry H L L L L H X X 3 Exit L H L H H H X X 3 H X X X X X 3 H X L L H H X V* H X L H L H X V H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X X L V V V X Exit L H X X X X X Entry H L H X X X X L H H H X H X X X X L H H H X X X X X V H X X X X L H H H X Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable Burst stop Precharge CAS H Bank activate Write RAS Mode register set Self refresh Read CS Selected bank Both banks Clock suspend or active power down Precharge power down mode Exit L H DQM H X No operation command H X row address L H L H column address column address X V L X H 4 4,5 4 4,5 6 X X X X X X 7 X * V = Valid. 1 2 3 4 5 6 7 OP= operation code. A0~A11 see page 5. MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS. Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after both banks are precharged. A11: bank select address. If low during read, write, row active and precharge, bank A is selected. If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge. A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after tRP from the end of the burst. Burst stop command valid at every burst length except full-page burst. DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2). 5/21/01; v.1.1 Alliance Semiconductor P. 4 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Mode register fields Address Function † Register programmed with MRS A9 A8 A7 A6 A5 A4 WBL TM CAS latency A11~A10 RFU† A3 BT A2 A1 A0 Burst length RFU = 0 during MRS cycle. Write burst length A9 Length Programmed 0 burst length 1 A3 0 1 Burst type Type Sequential Interleaved Single burst A8 0 0 1 1 A7 0 1 0 1 A6 0 0 0 0 1 A5 0 0 1 1 X Test mode Type Mode register set Reserved Reserved Reserved CAS latency A4 Latency 0 Reserved 1 1 0 2 1 3 X Reserved A2 0 0 0 0 1 1 1 1 Burst length A0 BT = 0 0 1 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Full page A1 0 0 1 1 0 0 1 1 BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Burst sequence (burst length = 4) Initial address A1 0 0 1 1 A0 0 1 0 1 Sequential 1 2 2 3 3 0 0 1 0 1 2 3 Interleave 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 Burst sequence (burst length = 8) A2 0 0 0 0 1 1 1 1 Initial address A1 0 0 1 1 0 0 1 1 5/21/01; v.1.1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 Alliance Semiconductor 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 4 2 5 1 6 0 7 7 0 6 1 5 2 4 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 P. 5 of 29 7 6 5 4 3 2 1 0 AS4LC2M8S1 AS4LC1M16S1 ® Recommended operating conditions Parameter Supply voltage Input voltage Output voltage‡ Ambient operating temperature Symbol Min Nominal Max Unit VCC,VCCQ 3.0 3.3 3.6 V GND 0.0 0.0 0.0 V VIH 2.0 – VCC + 0.3 V 8 – 0.8 V 8 † VIL –0.3 VOH 2.4 – – V VOL – – 0.4 V TA 0 70 °C Notes † VIL Min = –1.5V for pulse widths less than 5 ns. IOH = –2mA, and IOL = 2mA. Recommended operating conditions apply throughout this document unless otherwise specified. ‡ Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage VIN,VOUT –1.0 +4.6 V Power supply voltage VCC,VCCQ –1.0 +4.6 V TSTG –55 +150 °C PD – 1 W Storage temperature (plastic) Power dissipation Notes – 50 mA Short circuit output current IOUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5/21/01; v.1.1 Alliance Semiconductor P. 6 of 29 AS4LC2M8S1 AS4LC1M16S1 ® DC electrical characteristics –7 Parameter Symbol Input leakage current IIL 0V ≤ VIN ≤ VCC, Pins not under test = 0V Output leakage current IOL DOUT disabled, 0V ≤ VOUT ≤ VCCQ Operating current (one bank active) ICC1 tRC ≥ min, IO = 0mA, burst length = 1 ICC2P Precharge standby current (power down mode) Precharge standby current (non-powerdown mode) Active standby current (powerdown mode) Active standby current (non-powerdown mode, one bank active) Operating current (burst mode) Test conditions –8 –10 Min Max Min Max Min Max Unit Notes –5 +5 –5 +5 –5 +5 µA –10 +10 –10 +10 –10 +10 µA 1,3, 4,5 – 140 – 100 – 100 mA CKE ≤ VIL(max), tCK = 15 ns – 2.0 – 2.0 – 2.0 mA ICC2PS CKE and CLK ≤ VIL(max), tCK = ∞ – 2.0 – 2.0 – 2.0 mA ICC2N CS ≥ VIH(min), CKE ≥ VIH(min), tCK = 15 ns; input signals changed once during 30 ns – 30 – 30 – 30 mA 1,2,3 ICC2NS CLK ≤ VIL(max), CKE ≥ VIH(min), tCK = ∞; input signals stable – 6 – 6 – 6 mA 1,2,3 ICC3P CKE ≤ VIL(max), tCK = 15 ns – 2 – 2 – 2 mA 1,2,3 ICC3PS CLK, CKE ≤ VIL(max), tCK = ∞ – 2 – 2 – 2 mA 1,2,3 ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15 ns; input signals changed once during 30 ns – 35 – 35 – 35 mA 1,2,3 ICC3NS CKE ≥ VIH(min), CLK ≥ VIL(max), tCK = ∞; input signals stable – 10 – 10 – 10 mA 1,2,3 CL =3 140 – 130 – 120 ICC4 IO = 0 mA Page burst All banks activated tCCD = tCCD(min) CL =2 125 – 115 – 100 mA CL =1 80 – 70 – 70 100 – 90 – 80 mA 2 – 2 – 2 mA 1 – 1 – 1 mA Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 CKE ≤ 0.2 V CL =3 1,2, 3,5 1,2, 3,5 CL = CAS latency. 5/21/01; v.1.1 Alliance Semiconductor P. 7 of 29 15 AS4LC2M8S1 AS4LC1M16S1 ® AC parameters common to all waveforms Sym Parameter tAC CLK to valid output delay CAS latency 3 2 1 tAH Address hold time tAS Address setup time tBDL Last data-in to burst stop Read/write command to tCCD read/write command Last data-in to new tCDL column address delay tCH CLK high-level width tCK CLK cycle time tCMS CKE to CLOCK disable or power-down entry mode CKE hold time CKE setup time CLK low-level width CS, RAS, CAS, WE, DQM hold time CS, RAS, CAS, WE, DQM setup time tDAL Data-in to ACTIVE command tCKED tCKH tCKS tCL tCMH 3 2 1 3 2 1 tDH Data in hold time tDPL Data in to PRECHARGE tDQD DQM to input data delay DQM to data mask during tDQM writes DQM to data high Z tDQZ during reads tDS Data in setup time Write command to input tDWD data delay tHZ Data-out high-impedance time tLZ Data-out low-impedance time 5/21/01; v.1.1 3 2 1 –7 –8 –10 Min – – – – 2 0 Max 5.5 8.5 18 1 – – Min – – – – 2 0 Max 6 7 22 1 – – Min – – – – 2 0 Max 6 6 22 1 – – Unit ns ns ns ns ns tCK Notes 6 6,8 6,8 7 7 9 1 – 1 – 1 – tCK 9 1 – 1 – 1 – tCK 9 2.75 7 8.7 20 – 1000 1000 1000 3 8 10 25 – 1000 1000 1000 3 10 12 25 – 1000 1000 1000 ns ns ns ns 7 10 10 10 1 – 1 – 1 – tCK 1 2 2.75 – – – 1 2 3 – – – 1 2 3.5 – – – ns ns ns 1 – 1 – 1 – ns 2 – 2 – 2 – ns 5 5 4 1 2 1 – – – – – – 5 5 4 1 2 1 – – – – – – 5 5 4 1 2 1 – – – – – – tCK tCK tCK ns tCK tCK 5,11 5,11 5,11 0 – 0 – 0 – tCK 9 2 – 2 – 2 – tCK 9 2 – 2 – 2 – ns 0 – 0 – 0 – tCK 9 – – – 5.5 8.5 18 – – – 6 9 22 – – – 9 9 22 ns ns ns 13 13 13 1 – 1 – 1 – ns Alliance Semiconductor 7 12 9 P. 8 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Sym tMRD Parameter Load mode register to active/refresh command tOH Output data hold time @ 30 pF tPED tRAS tRC tRCAR tRCD tREF tROH tRP tRRD tT tWR tXSR CKE to CLOCK enable or power-down exit mode Active to precharge command Active command period Auto refresh period Active to read or write delay Refresh period—2048 rows Data-out high Z from precharge/burst stop command Precharge command period Active Bank A to Active Bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command CAS latency –7 –8 –10 Min Max Min Max Min Max Unit Notes 2 – 2 – 2 – tCK 5 2 2 2 – – – 2.5 2.5 2.5 – – – 3 3 3 – – – ns ns ns 6 6 6 1 – 1 – 1 – tCK 42 120,000 48 120,000 50 120,000 ns 70 70 – – 80 80 – – 80 80 – – ns ns 8 3 – 3 – 3 – tCK 8 – 64 – 64 – 64 ms 3 2 1 3 2 1 – – – 3 2 1 – – – 3 2 1 – – – tCK tCK tCK 9 9 9 3 3 – 3 – 3 – tCK 8 14 – 16 – 20 – ns 0.3 2 1.0 – 0.3 2 1.0 – 0.3 2 1.0 – ns tCK 70 – 80 – 80 – ns 3 2 1 3 20 Notes 1 IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 2 Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 3 Address transitions average one transition every two-clock period. 4 The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced. 5 tCK = 7 ns for –7, 8 ns for –8, and 10 ns for –10. 6 If clock tr > 1 ns, (tr/2 – 0.5)ns should be added to the parameter. 7 If clock (tr and tf) > 1 ns, [(tr + tf)/2 – 1] ns should be added to the parameter. 8 VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL(min) = –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate. 9 Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter. 10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be used to reduce the data rate. 11 Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 12 Timing actually specified by tWR. 13 tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going to HIGH-Z. 14 CLK must be toggled a minimum of two times during this period. 15 Enables on-chip refresh and address counters. 16 All voltages referenced to VSS. 17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0° C ≤ TA ≤ 70° C) is endured. 5/21/01; v.1.1 Alliance Semiconductor P. 9 of 29 AS4LC2M8S1 AS4LC1M16S1 ® 18 A proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at the same potential.)Two AUTOREFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 19 AC characteristics assume tT = 1 ns. 20 In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 21 AC timing and IDD tests have VIL = 0V and VIH = 3.0 V with timing referenced to 1.4V crossover point. 22 IDD specifications are tested after the device is properly initialized. 23 Minimum clock cycles = (minimum time/clock cycle time) rounded up. Device operation Command Pin settings Power up Mode register set CS = RAS = CAS = WE = low; A0~A11 = opcode Device deselect and no operation CS = high, or RAS, CAS, WE = high Bank activation CS = RAS = low; CAS = WE = high; A0~A10 = row address; A11 = bank select Burst read CS = CAS = A10 = low; RAS = WE = high; A11 = bank select, A0~A8 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) 5/21/01; v.1.1 Description The following sequence is recommended prior to normal operation. 1 Apply power, start clock, and assert CKE and DQM high. All other signals are NOP. 2 After power-up, pause for a minimum of 200µs. CKE/DQM = high; all others NOP. 3 Precharge both banks. 4 Perform Mode Register Set command to initialize mode register. 5 Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (Steps 4 and 5 may be interchanged.) The mode register stores the user selected opcode for the SDRAM operating modes. The CAS latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during the Mode Register Set command cycle. The default setting of the mode register is not defined after power-up. Therefore, it is recommended that the power-up and mode register set cycle be executed prior to normal SDRAM operation. Refer to the Mode Register Set table and timing for details. The SDRAM performs a “no operation” (NOP) when RAS, CAS, and WE = high. Since the NOP performs no operation, it may be used as a wait state in performing normal SDRAM functions. The SDRAM is deselected when CS is high. CS high disables the command decoder such that RAS, CAS, WE and address inputs are ignored. Device deselection is also considered a NOP. The SDRAM is configured with two internal banks. Use the Bank Activate command to select a row in one of the two idle banks. Initiate a read or write operation after tRCD(min) from the time of bank activation. Use the Burst Read command to access a consecutive burst of data from an active row in an active bank. Burst read can be initiated on any column address of an active row. The burst length, sequence and latency are determined by the mode register setting. The first output data appears after the CAS latency from the read command. The output goes into a high impedance state at the end of the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. A full-page burst does not terminate automatically at the end of the burst. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write Alliance Semiconductor P. 10 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Command Pin settings Burst write CS = CAS = WE = A10 = low; RAS = high; A0~A9 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) UDQM/LDQM (×16) DQM (×8) operation Burst stop CS = WE = low; RAS = CAS = high Bank precharge CS = A10 = RAS = WE = low; CAS = high; A11 = bank select; A0~A9 = don’t care Description Use the Burst Write command to write data into the SDRAM on consecutive clock cycles to adjacent column addresses. The burst length and addressing mode is determined by the mode register opcode. Input the initial write address in the same clock cycle as the Burst Write command. Burst terminate behavior for write is the same as that for read. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. DQM can also be used to mask the input data. Use DQM to mask input and output data. It disables the output buffers in a read operation and masks input data in a write operation. The output data is invalid 2 clocks after DQM assertion (2 clock latency). Input data is masked on the same clock as DQM assertion (0 clock latency). Use burst stop to terminate burst operation. This command may be used to terminate all legal burst lengths. The Bank Precharge command precharges the bank specified by A11. The precharged bank is switched from active to idle state and is ready to be activated again. Assert the precharge command after tRAS(min) of the bank activate command in the specified bank. The precharge operation requires a time of tRP(min) to complete. CS = RAS = WE = low; CAS = The Precharge All command precharges both banks simultaneously. A10 = high; A11, A0~A9 = Both banks are switched to the idle state on precharge completion. don’t care During auto precharge, the SDRAM adjusts internal timing to satisfy t (min) and tRP for the programmed CAS latency and burst length. Write: CS = CAS = WE = low ; RAS Couple the auto precharge with a burst read/write operation by Read: CS = CAS = low; asserting A10 to a high state at the same time the burst read/write A10 = high; A11 = bank select; commands are issued. At auto precharge completion, the specified Auto precharge A0~A9 = column address; bank is switched from active to idle state. Note that no new commands (A9 = don’t care for 2M × 8; A8, (RD/WR/DEAC) can be issued to the same bank until the specified A9 = don’t care for 1M × 16) bank achieves the idle state. Auto precharge does not work with fullpage burst. When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. If both banks are idle and CKE goes low, the SDRAM enters Clock suspend/power power down mode at the next clock cycle. When in power down CKE = low down mode entry mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Resume internal clock operation by asserting CKE high before the Clock suspend/power CKE = high rising edge of CLK. Subsequent commands can be issued one clock down mode exit cycle after the end of the Exit command. Precharge all 5/21/01; v.1.1 Alliance Semiconductor P. 11 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Command Pin settings Auto refresh CS = RAS = CAS = low; WE = CKE = high; A0~A11 = don’t care Self refresh CS = RAS = CAS = CKE = low; WE = high; A0~A11 = don’t care Description SDRAM storage cells must be refreshed every 64 ms to maintain data integrity. Use the auto refresh command to accomplish the refreshing of all rows in both banks of the SDRAM. The row address is provided by an internal counter which increments automatically. Auto refresh can only be asserted when both banks are idle and the device is not in the power down mode. The time required to complete the auto refresh operation is tRC(min). Use NOPs in the interim until the auto refresh operation is complete. Both banks will be in the idle state after this operation. Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh address and timing are provided internally. Self refresh entry is allowed only when both banks are idle. The internal clock and all input buffers with the exception of CKE are disabled in this mode. Exit self refresh by restarting the external clock and then asserting CKE high. NOPs must follow for a time of tRC(min) for the SDRAM to reach the idle state where normal operation is allowed. If burst auto refresh is used in normal operation, burst 2048 auto refresh cycles immediately after exiting self refresh. Initialize and load mode register T0 T1 Tn tCK CLK tCL Tm Tp+1 Tp+2 Tp+3 NOP ACTIVE tCH tCKH tCKS CKE tCMH COMMAND NOP tCMS PRECHARGE ALL AUTO REFRESH NOP NOP AUTO REFRESH NOP NOP LOAD MODE REGISTER DQM* tAS ADDRESS A10=HIGH tAH CODE BANK ROW High Z DQ T=200µs (min) Power up: VDD and CLK stable. tRP Precharge all banks. tRCAR (8 AUTO REFRESH CYCLES) tMRD Program Mode Register†ƒ AUTO REFRESH * DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. † The Mode Register may be loaded prior to the auto refresh cycles if desired. ƒ Outputs are guaranteed High-Z after command is issued. 5/21/01; v.1.1 Alliance Semiconductor P. 12 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Read—DQM operation* T0 tCK*†ƒ CLK T1 T2 tCL T3 T4 tCL T6 T5 T7 T8 NOP NOP tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ NOP NOP NOP NOP tCMH tCMS DQMƒ tDQZ tAS A0–A9 tAH tAS A10 tAH ROW ENABLE AUTOPRECHARGE ROW tAS BA Column m (A0-A7)3 ROW DISABLE AUTOPRECHARGE tAH BANK BANK tAC*†ƒ DQ DOUT m tHZ tLZ tRCD tAC*†ƒ tOH tAC*†ƒ tOH DOUT m+2 tOH DOUT m+3 tLZ tHZ CAS latency * For this example, the burst length = 4, and the CAS latency = 2. † A8 and A9 = “Don’t care.” ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Write—DQM operation* T0 tCK*†ƒ T1 CLK T3 T2 tCL T5 T4 T6 T7 tCH tCKS tCKH CKE tCMS COMMAND tCMH ACTIVE NOP WRITE tCMS NOP NOP NOP NOP NOP tCMH DQMƒ tAS A0–A9 tAS A10 Column m (A0-A7)† tAH ENABLE AUTOPRECHARGE ROW tAS BA tAH ROW DISABLE AUTOPRECHARGE tAH BANK BANK tDS DQ tRCD tDH DIN m tDS tDH DIN m+2 tDS tDH DIN m+3 * For this example, the burst length = 4. A8 and A9 = “Don’t care.” ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. † 5/21/01; v.1.1 Alliance Semiconductor P. 13 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Write—full-page burst T0 tCL CLK T1 T2 tCK*†ƒ T3 T5 T4 Tn+1 Tn+3 Tn+2 tCH tCKS tCKH CKE tCMS COMMAND tCMH ACTIVE NOP WRITE NOP NOP NOP NOP NOP BURST TERM tCMH tCMS DQM† tAS A0–A9 tAH Column m (A0-A7)* ROW tAS A10 tAH ROW tAS BA tAH BANK BANK tDS DQ tRCD tDH tDS tDS tDH DIN m+2 D IN m+1 DIN m tDS tDH tDH tDS DIN m+3 tDH tDS tDH DIN m+255 256 locations within same row Full page completedFull-page burst does not self terminate. Can use ƒ BURST TERMINATE command. * A8 and A9 = Don’t care. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. ƒPage left open; no t . RP † Read—full-page burst* T0 T1 tCL T2 T3 T4 T5 T6 READ NOP NOP NOP NOP Tn+1 Tn+2 Tn+3 Tn+4 tCK CLK tCH tCMS tCMH CKE tCMS tCMH ACTIVE NOP BURST TERM NOP Command NOP NOP DQM† tAS A0–A9 tAH COLUMN†m (A0-A7) ROW tAS tAH A10 ROW tAS BA tAH BANK BANK tAC*†ƒ DQ tAC*†ƒ tOH DOUT m tAC*†ƒ tOH tAC*†ƒ tOH DOUT m+2 DOUT m+1 256 locations within same row tRCD tLZ CAS Latency Full page completed tAC*†ƒ tOH DOUT m+255 tAC*†ƒ tOH DOUT m tOH DOUT m+1 tHZ*†ƒ Full-page burst does not self-terminate. ** Can use BURST TERMINATE command. * For this example, the CAS latency = 2. A8 and A9 = “Don’t care.” ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. ** Page left open; no t . RP † 5/21/01; v.1.1 Alliance Semiconductor P. 14 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Mode register set command waveform CLK CMD PRE MRS ACT tRP Or Auto Refresh tRSC(min) tMRD MRS can be issued only when both banks are idle. Precharge waveforms Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP . The earliest assertion of the precharge command without losing any burst data is show below. (normal write; BL = 4) CLK CMD WE DQ PRE D2 D1 D0 D3 (normal read; BL = 4) CLK CMD PRE Read data DQ(CL1) Q0 DQ(CL2) Q1 Q2 Q0 Q3 Q1 DQ(CL3) Q2 Q0 Q3 Q1 Q2 Q3 Auto precharge waveforms A10 controls the selection of auto precharge during the read or write command cycle. (write with auto precharge; BL = 4) CLK CMD WE DQ D0 D1 D2 D3 Auto precharge starts* (read with auto precharge; BL = 4) CLK CMD DQ(CL1) DQ(CL2) DQ(CL3) Read data Q0 Q1 Q0 Q2 Q1 Q0 Q3 Q2 Q1 Q3 Q2 Q3 Auto precharge starts* *The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. 5/21/01; v.1.1 Alliance Semiconductor P. 15 of 29 AS4LC2M8S1 AS4LC1M16S1 ® DQM waveforms: read (CL = 3, BL = 4) CLK CMD Read data DQM tDQZ DQ(CL = 3) DQ(CL = 2) Q0 Q0 Q2 Q1 Q3 tDQZ DQM waveforms: write (BL = 4) CLK CMD Write data Ext DIN D0 D1 D2 D3 DQM Data written D0 D3 D1ignored D2 ignored Concurrent Auto-P Waveforms According to Intel™’s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst. (A) RD-P interrupted by RD in another bank (CL = 3, BL = 4) CLK CMD RD-P(A) RD (B) DQ A0 A1 B0 B1 B2 B3 tRP(A) Bank A precharge starts (B) RD-P interrupted by WR in another bank (CL = 3, BL = 8) CLK CMD RD-P (A) WR (B) DQM DQ QA0 QA1 DN(B0) D(B1) D(B2) D(B7) tRP Bank A precharge starts 5/21/01; v.1.1 Alliance Semiconductor P. 16 of 29 AS4LC2M8S1 AS4LC1M16S1 ® (C) WR-P interrupted by RD in another bank (CL = 2, BL = 4) CLK CMD WRP (A) DQ D(A0) RD (B) D(A1) QB0 QB1 QB2 QB3 tRP Bank A precharge starts (D) WR-P Interrupted by WR in another bank (CL = 3, BL = 4) CLK Bank A precharge starts CMD WRP (A) DQ DA0 WR (B) DA1 DA2 DB0 DB1 DB2 DB3 Clock suspension read waveforms (BL = 8) CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 OPEN Q6 OPEN Q7 CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 tCKED Q4 Q6 tPED CLK external CLK internal CKE DQM DQ 5/21/01; v.1.1 Q1 Q2 Q3 Q4 Alliance Semiconductor Q5 Q6 P. 17 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Clock suspension write waveforms CLK external CLK internal tCKH CKE tCKS DQM DQ D1 D2 D3 D6 D5 DQM Mask CKE Mask CLK external CLK internal CKE DQM DQ D1 D2 D3 DQM Mask D5 D6 D5 D6 CKE Mask CLK external CLK internal CKE tCMS tCMH DQM DQ D1 D2 D4 D3 CKE Mask Read/write interrupt timing read interrupted by read (BL = 4) CLK CMD ADD tCMS tCMH Read data Read data A B DQ (CL1) QA0 DQ (CL2) QB0 QA0 DQ (CL3) tCCD QB1 QB0 QA0 QB2 QB3 QB1 QB2 QB3 QB1 QB2 QB0 QB3 tCCD = CAS to CAS delay (= 1 CLK). 5/21/01; v.1.1 Alliance Semiconductor P. 18 of 29 AS4LC2M8S1 AS4LC1M16S1 ® write interrupted by write (BL = 4) tCK tCL tCH CLK tCCD CMD Write data ADD Write data A0 DQ B0 DA0 DB0 DB1 DB2 DB3 tCDL tDS tDH tCCD = CAS to CAS delay (= 1 CLK). tCDL = last address in to new column addres delay (= 1 CLK). write interrupted by read (BL = 4) CLK tCCD CMD Write data Read data ADD A B DQ (CL1) DA0 DQ (CL2) DA0 DQ (CL3) DA0 QB0 QB1 QB2 QB0 QB3 QB1 QB2 QB3 QB0 QB1 QB2 QB3 tCDL tCCD = CAS to CAS delay (= 1 CLK). tCDL = last address in to new column addres delay (= 1 CLK). Interrupting RD/WR can be for either the same or different banks. read interrupted by write (CL = 1, BL = 4) CLK CMD1 Read data Write data DQM1 DQ1 tLZ CMD2 tHZ D0 Read data D1 D2 D3 D1 D2 Write data DQM2 DQ2 CMD3 D0 Read data D3 Write data DQM3 DQ3 Q0 Q1 D0 D1 D2 D3 To prevent bus contention, maintain a gap between data in and data out. 5/21/01; v.1.1 Alliance Semiconductor P. 19 of 29 AS4LC2M8S1 AS4LC1M16S1 ® read interrupted by write (CL = 2, BL = 4) CLK CMD1 Read data Write data DQM1 DQ1 CMD2 D0 D1 Read data D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 Write data DQM2 DQ2 CMD3 D0 Read data Write data DQM3 DQ3 CMD4 D0 Read data Write data DQM4 DQ4 Q0 D0 D3 To prevent bus contention, maintain a gap between data in and data out. read interrupted by write (CL = 3, BL = 4) tCCD CLK CMD1 Read data Write data DQM1 DQ1 CMD2 DQM2 D0 Read data DQ2 CMD3 D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 Write data D0 Read data Write data DQM3 DQ3 CMD4 D0 Read data Write data DQM4 DQ4 D0 D3 To prevent bus contention, maintain a gap between data in and data out. Burst termination Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously. 5/21/01; v.1.1 Alliance Semiconductor P. 20 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Burst stop command waveform read cycle tT CLK CMD Read data Burst stop tOH DQ (CL = 1) Q0 DQ (CL = 2) Q1 Q2 Q0 Q1 Q2 Q0 Q1 DQ (CL = 3) Q2 write cycle (BL = 8) CLK CMD Write data DQ (CL = 1,2,3) Burst stop DQ D1 D2 D3 Precharge termination A Precharge command terminates a burst read/write operation during the read cycle. The same bank can be activated after meeting tRP. If an RD-burst is terminated, o/p will go to High Z after the number of cycles = CAS latency. read cycle (CL = 1) CLK CMD Read data DQ PRE Q0 Q1 Q2 ACT Q3 tRP read cycle (CL = 2) tRP CLK CMD Read data DQ PRE Q0 Q1 ACT Q2 Q3 tROH (CL = 2) read cycle (CL = 3) tRP CLK CMD DQ Read data PRE Q0 Q1 ACT Q2 Q3 tROH (CL = 3) 5/21/01; v.1.1 Alliance Semiconductor P. 21 of 29 AS4LC2M8S1 AS4LC1M16S1 ® write cycle tWR CLK CMD Write data DQ PRE D1 D0 D2 D3 ACT Q4 tRP Write recovery (BL = 4) tDPL CLK CMD tRP Write data PRE ACT tDAL DQ D1 D0 D3 D2 This precharge is implicit in case of Auto-P Write. Auto refresh waveform CLK tRP CS tRC tRC RAS CAS WE A10 A0–A9 DQM CKE DQ Precharge both banks Auto refresh 5/21/01; v.1.1 Auto refresh Alliance Semiconductor Auto refresh P. 22 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Self refresh waveform CLK CS RAS CAS WE A11 A0–A10 DQM CKE DQ Self refresh Precharge both banks Self refresh entry cycle tRC Arbitrary cycle Self refresh exit Clock stable before self refresh exit Power down mode waveform (CL = 3) CLK CS RAS CAS WE A11 A10 RAa A0–A9 RAa RAa RAa CAa CAx DQM CKE DQ Bank activate Active standby Power down mode Power down mode entry Data burst NOP Power down mode exit Precharge standby Power down mode Power down mode entry NOP Bank activate Power down mode exit Enter power down mode by pulling CKE low. All input/output buffers (except CKE buffer) are turned off in power down mode. When CKE goes high, command input must be equal to no operation at next CLK rising edge. 5/21/01; v.1.1 Alliance Semiconductor P. 23 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Read/write waveform (BL = 8, CL = 3) CLK tRAS CS RAS CAS WE A11 tRCD A10 RAa A0–A9 RAa RAb CAa RAb CAb DQM CKE tRP DQ Aa0 Bank activate Read Q Aa1 Q Aa2 Aa3 Aa4 Aa5 Q Q Q Q Ab0 D Write Ab1 Ab2 Ab3 Ab4 D D D D Ab5 D Bank activate Precharge Burst read/single write waveform (BL = 4, CL = 3) CLK CS RAS CAS WE A11 A10 RAa A9 RAa CAa CAb CAc CAd DQM CKE DQ Activate Read Aa0 Aa1 Aa2 Aa3 Q Q Q Q Ab D 5/21/01; v.1.1 Ac Single Write D Alliance Semiconductor Read Ad0 Ad1 Ad2 Ad3 Q Q Q Q P. 24 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Interleaved bank read waveform (BL = 4, CL = 3) CLK tCCD tCCD tCCD CS tRAS RAS CAS WE A11 tRCD A10 RAa A0–A9 RAa tRCD RBa CAa RBa CAb CBa CBb CAc tRAS DQM CKE DQ Bank A: Bank B: QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2 QBb0 QBb1 QBb2 QBb3 Read Read Active Read Precharge Active Read Read Interleaved bank read waveform Precharge (BL = 4, CL = 3, Autoprecharge) CLK CS tRC tRC RAS tRAS tRAS tRP CAS tRP tRP tRAS WE A11 tRCD A10 A9 tRCD RAa tRCD RBb RAa CAa RAc CBb RBb RBd CAc RAc RBd DQM CKE tRRD tRRD DQ Bank A: Bank B: tRRD QAa0 QAa1 QAa2 QAa3 Active Read AP Active Active Read QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 Read AP AP Active AP = internal precharge begins 5/21/01; v.1.1 Alliance Semiconductor P. 25 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Interleaved bank read waveform (BL = 8, CL = 3) CLK CS tRC RAS tRAS tRP tRP tRAS CAS WE A11 tRCD A10 RAa A9 RAa tRCD tRCD RBb RAc RBb CAa CBb RAc CAc DQM CKE DQ Bank A: Bank B: QAa0 QAa1 Active QAa2 QAa3 QAa4 QAa5 QAa6 QBb0 QBb1 Precharge Read Precharge Active QBb4 QBb5 QBb6 QBb7 Active QAc0 QAc1 Read Read Precharge Interleaved bank read waveform (BL = 8, CL = 3, Autoprecharge) CLK tRC CS RAS tRP tRAS tRAS CAS WE A11 tRCD A10 RAa A9 RAa tRCD tRCD RBb CAa RAc RBb RAc CAb CAc DQM CKE QAa0 QAa1 QAa2 DQ Bank A Active Bank B Read tRRD Active QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1 AP Read tRRD Active QBb4 QBb5 QBb6 QAc0 QAc0 Read AP AP = internal precharge begins 5/21/01; v.1.1 Alliance Semiconductor P. 26 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Interleaved bank write waveform (BL = 8) CLK CS tRC RAS tRAS tRP tRAS CAS tRCD tRCD tRCD WE A11 A10 RAa A9 RAa RBb CAa RAc RBb RAc CAb CAc DQM CKE DQ DAa0 Bank A Active Bank B DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 DBb4 Precharge Write Active DBb5 DBb6 Active DAc2 Write Precharge Write Interleaved bank write DBb7 DAc0 DAc1 (BL = 8, Autoprecharge) CLK CS tRC RAS tRAS tRP tRAS CAS WE tRCD tRCD tRCD A11 A10 RAa A9 RAa RBb RBb CAa RAc RAc CAb CAc DQM CKE DQ Bank A Active Bank B DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 AP Bank A Write Active Write DBb4 DBb5 Active DBb6 DBb7 DAc0 DAc1 DAc2 Write AP Bank B AP = internal precharge begins 5/21/01; v.1.1 Alliance Semiconductor P. 27 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Package dimensions c 50 494847 4645 444342 4140 393837 36 35343332 3130 29 28 2726 TSOP 2 E He 1 2 3 4 5 6 7 8 9 1011 12 13 14 1516171819 20 21 2223 2425 D l A2 A A1 b 0–5° e 44-pin TSOP 2 50-pin TSOP 2 Min (mm) Max (mm) Min (mm) A – 1.2 A1 0.05 – 0.05 A2 0.95 1.05 0.95 1.05 b 0.30 0.45 0.30 0.45 c 0.127 (typical) 0.12 0.21 D 18.28 18.54 20.85 21.05 E 10.03 10.29 10.03 10.29 He 11.56 11.96 11.56 11.96 Max (mm) 1.2 e 0.80 (typical) 0.80 (typical) l 0.40 0.40 0.60 0.60 AC test conditions +1.5V - Output reference levels = 1.4V - Input rise and fall times: 2 ns 50Ω DOUT CLOAD = 50 pF Figure A: Equivalent output load Capacitance 15 Parameter Input capacitance I/O capacitance ƒ = 1 MHz, Ta = 25° C, VCC = 3.3V Symbol Signals Max Unit CIN1 A0 to A11 4 pF CIN2 DQM, RAS, CAS, WE, CS, CLK, CKE, 4 pF CI/O DQ0 to DQ7 (2M × 8) DQ0 to DQ15 (1M × 16) 5 pF Ordering information Package \1/ frequency –7 ns –8 ns –10 ns TSOP 2, 400 mil, 44-pin AS4LC2M8S1-7TC AS4LC2M8S1-8TC AS4LC2M8S1-10TC TSOP 2, 400 mil, 44-pin AS4LC2M8S0-7TC AS4LC2M8S0-8TC AS4LC2M8S0-10TC TSOP 2, 400 mil, 50-pin AS4LC1M16S1-7TC AS4LC1M16S1-8TC AS4LC1M16S1-10TC TSOP 2, 400 mil, 50-pin AS4LC1M16S0-7TC AS4LC1M16S0-8TC AS4LC1M16S0-10TC 5/21/01; v.1.1 Alliance Semiconductor P. 28 of 29 AS4LC2M8S1 AS4LC1M16S1 ® Part numbering system AS4 LC XXX SX –XX Device number S1 = 2K refresh DRAM prefix 3.3V CMOS for synchronous 1/frequency S0 = 4K refresh DRAM 5/21/01; v.1.1 Alliance Semiconductor T C Package (device dependent): TSOP 2 400 mil, 44 pin TSOP 2 400 mil, 50 pin Commercial temperature range: 0° C to 70° C P. 29 of 29 © Copyright Alliance Semiconductor Corporation. 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