January 2001 Advance Information AS7C1024A AS7C31024A ® 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) Features • Latest 6T 0.25u CMOS technology • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages • AS7C1024A (5V version) • AS7C31024A (3.3V version) • Industrial and commercial temperatures • Organization: 131,012 words x 8 bits • High speed - 300 mil SOJ - 400 mil SOJ - 8 × 20mm TSOP I - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption: ACTIVE • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 660 mW (AS7C1024A) / max @ 10 ns - 324 mW (AS7C31024A) / max @ 10 ns • Low power consumption: STANDBY - 55 mW (AS7C1024A) / max CMOS - 36 mW (AS7C31024A) / max CMOS Pin arrangement Input buffer 512×256×8 Array (1,048,576) Sense amp Row decoder I/O7 I/O0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC A15 CE2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 WE OE CE1 CE2 Control circuit A9 A10 A11 A12 A13 A14 A15 A16 Column decoder A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 AS7C1024A AS7C31024A GND A0 A1 A2 A3 A4 A5 A6 A7 A8 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 32-pin TSOP I (8 x 20mm) VCC AS7C1024A AS7C31024A Logic block diagram Selection guide AS7C1024A-10 AS7C31024A-10 AS7C1024A-12 AS7C31024A-12 AS7C1024A-15 AS7C31024A-15 AS7C1024A-20 AS7C31024A-20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 3 3 4 5 ns Maximum operating current ASAS7C1024A 120 110 100 100 mA AS7C31024A 90 80 80 80 mA Maximum CMOS standby current AS7C1024A 10 10 10 15 mA AS7C31024A 10 10 10 15 mA 2/6/01; V.0.9 Alliance Semiconductor P. 1 of 8 Copyright © Alliance Semiconductor. All rights reserved. AS7C1024A AS7C31024A ® Functional description The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,012 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024A is guaranteed not to exceed 36mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter Symbol Min Max Unit AS7C1024A Vt1 –0.50 +7.0 V AS7C31024A Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Both Vt2 –0.50 VCC +0.50 V Power dissipation Both PD – 1.0 W Storage temperature (plastic) Both Tstg –65 +150 °C Ambient temperature with VCC applied Both Tbias –55 +125 °C DC current into outputs (low) Both IOUT – 20 mA Voltage on VCC relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode H X X X High Z Standby (ISB, ISB1) X L X X High Z Standby (ISB, ISB1) L H H H High Z Output disable (ICC) L H H L DOUT Read (ICC) L H L X DIN Write (ICC) Key: X = Don’t Care, L = Low, H = High 2/6/01; V.0.9 Alliance Semiconductor P. 2 of 8 AS7C1024A AS7C31024A ® Recommended operating conditions Parameter Supply voltage Input voltage Device Symbol Min Nominal Max Unit AS7C1024A VCC 4.5 5.0 5.5 V AS7C31024A VCC 3.0 3.3 3.6 V ASAS7C1024A VIH 2.2 – VCC + 0.5 V AS7C31024A VIH 2.0 – VCC + 0.5 V VIL† –0.5 – 0.8 V commercial TA 0 – 70 °C industrial TA –40 – 85 °C Ambient operating temperature † VILmin. = –3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -10 -12 -15 -20 Unit Parameter Sym Test conditions Device Input leakage current |ILI| VCC = Max, VIN = GND to VCC Both – 1 – 1 – 1 – 1 µA Output leakage current |ILO| VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC Both – 1 – 1 – 1 – 1 µA VCC = Max, CE1 = VIL, CE2 = VIH, f = fMax, IOUT = 0 mA AS7C1024A – 120 – 110 – 100 – 100 ICC AS7C31024A – 90 – 80 – 80 – 80 VCC = Max, CE1 ≥ VIH and/or CE2 ≤ VIL, VIN = VIH or VIL, f = fMax, IOUT = 0mA AS7C1024A – 30 – 25 – 20 – 20 ISB AS7C31024A – 30 – 25 – 20 – 20 VCC = Max, CE1 ≥ VCC–0.2V VIN ≤ GND + 0.2V or VIN ≥ VCC –0.2V, f = 0 AS7C1024A – 10 – 10 – 10 – 15 ISB1 AS7C31024A – 10 – 10 – 10 – 15 VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – V AS7C1024A - 1 - 1 - 1 - 5 mA ICCDR VCC = 2.0V CE1 ≥ VCC–0.2V or CE2 ≤ 0.2V VIN ≥ VCC–0.2V or VIN ≤ 0.2V AS7C31024A - 1 - 1 - 1 - 5 mA Operating power supply current Standby power supply current Output voltage Data retention current Min Max Min Max Min Max Min Max mA mA mA Capacitance (f = 1 MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE1, CE2, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 2/6/01; V.0.9 Alliance Semiconductor P. 3 of 8 AS7C1024A AS7C31024A ® Read cycle (over the operating range)3,9,12 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 – 12 – 15 – 20 – ns Address access time tAA – 10 – 12 – 15 – 20 ns 3 Chip enable (CE1) access time tACE1 – 10 – 12 – 15 – 20 ns 3, 12 Chip enable (CE2) access time tACE2 – 10 – 12 – 15 – 20 ns 3, 12 Output enable (OE) access time tOE – 3 – 3 – 4 – 5 ns Output hold from address change tOH 2 – 3 – 3 – 3 – ns 5 CE1 Low to output in low Z tCLZ1 0 – 0 – 0 – 0 – ns 4, 5, 12 CE2 High to output in low Z tCLZ2 0 – 0 – 0 – 0 – ns 4, 5, 12 CE1 Low to output in high Z tCHZ1 – 3 – 3 – 4 – 5 ns 4, 5, 12 CE2 Low to output in high Z tCHZ2 – 3 – 3 – 4 – 5 ns 4, 5, 12 OE Low to output in low Z tOLZ 0 – 0 – 0 – 0 – ns 4, 5 OE High to output in high Z tOHZ – 3 – 3 – 4 – 5 ns 4, 5 Power up time tPU 0 – 0 – 0 – 0 – ns 4, 5, 12 Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5, 12 Key to switching waveforms Rising input Falling input Undefined / don’t care Read waveform 1 (address controlled)3,6,7,9,12 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 tRC1 CE1 CE2 tOE OE DOUT Current supply 2/6/01; V.0.9 tOHZ tCHZ1, tCHZ2 tOLZ tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% Alliance Semiconductor ICC ISB P. 4 of 8 AS7C1024A AS7C31024A ® Write cycle (over the operating range)11, 12 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Write cycle time tWC 10 – 12 – 15 – 20 – ns Chip enable (CE1) to write end tCW1 8 – 10 – 12 – 12 – ns 12 Chip enable (CE2) to write end tCW2 8 – 10 – 12 – 12 – ns 12 Address setup to write end tAW 8 – 9 – 10 – 12 – ns Address setup time tAS 0 – 0 – 0 – 0 – ns Write pulse width tWP 7 – 8 – 9 – 12 – ns Address hold from end of write tAH 0 – 0 – 0 – 0 – ns Data valid to write end tDW 5 – 6 – 8 – 10 – ns Data hold time tDH 0 – 0 – 0 – 0 – ns 4, 5 Write enable to output in high Z tWZ – 6 – 6 – 6 – 8 ns 4, 5 Output active from write end tOW 1 – 1 – 1 – 2 – ns 4, 5 12 Write waveform 1 (WE controlled)10,11,12 tWC tAW tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CE1 and CE2 controlled)10,11,12 tWC tAW tAH Address tAS tCW1, tCW2 CE1 CE2 tWP WE tWZ DIN tDW tDH Data valid DOUT 2/6/01; V.0.9 Alliance Semiconductor P. 5 of 8 AS7C1024A AS7C31024A ® Data retention characteristics (over the operating range) Parameter Symbol Test conditions VCC for data retention VDR Chip deselect to data retention time tCDR VCC = 2.0V CE1 ≥ VCC–0.2V or CE2 ≤ 0.2V VIN ≥ VCC–0.2V or VIN ≤ 0.2V Operation recovery time tR Input leakage current | ILI | Device Min Max Unit 2.0 – V 0 – ns tRC – ns – 1 µA Data retention waveform Data retention mode VCC VDR ≥ 2.0V VCC VCC tCDR VDR VIH CE1 tR VIH AC test conditions – – – – Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V +3.3V 480W +3.0V GND 90% 10% 90% 2 ns Figure A: Input pulse 10% DOUT 255W C(14) GND Figure B: 5V Output load 320W DOUT 255W C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE1 and OE are Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except all high Z and low Z parameters, C=5pF. 2/6/01; V.0.9 Alliance Semiconductor P. 6 of 8 AS7C1024A AS7C31024A ® Package dimensions D e E1 E2 B Pin 1 c A A1 A2 b Seating Plane E A A1 A2 B b c D E E1 E2 e 32-pin SOJ 300 mil Min Max 0.145 0.025 0.086 0.105 0.026 0.032 0.014 0.020 0.006 0.013 0.820 0.830 0.250 0.275 0.292 0.305 0.330 0.340 0.050 BSC 32-pin SOJ 400 mil Min Max 0.145 0.025 0.086 0.115 0.026 0.032 0.015 0.020 0.007 0.013 0.820 0.830 0.360 0.380 0.395 0.405 0.435 0.445 0.050 BSC a;lsdfj;alksdfj;alkfdsa;lsdfj;alksdfj;alkfdsa;lsdfj;alks dfj;alkfdsa;lsdfj;alksdfj;alkfdsa;lsdfj;alksdfj;alkfdsa ;lsdfj;alksdfj;alkfdsa;lsdfj;alksdfj;alkfdsa;lsdfj;alksd fj;alkfdsa;lsdfj;alksdfj;alkfds b e α c D E 2/6/01; V.0.9 Hd A2 L pin 1 pin 32 pin 16 pin 17 A A1 Alliance Semiconductor A A1 A2 b c D e E Hd L α 32-pin TSOP 8×20 mm Min Max – 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.10 0.21 18.20 18.60 0.50 nominal 7.80 8.20 19.80 20.20 0.50 0.70 0° 5° P. 7 of 8 ASAS7C1024A ASAS7C31024A ® Ordering codes Package \ Access time Plastic SOJ, 300 mL Plastic SOJ, 400 mL TSOP 8×20 Volt/Temp 10 ns 12 ns 15 ns 20 ns 5V commercial AS7C1024A-10TJC AS7C1024A-12TJC AS7C1024A-15TJC AS7C1024A-20TJC 5V industrial AS7C1024A-10TJI AS7C1024A-12TJI AS7C1024A-15TJI AS7C1024A-20TJI 3.3V commercial AS7C31024A-10TJC AS7C31024A-12TJC AS7C31024A-15TJC AS7C31024A-20TJC 3.3V industrial AS7C31024A-10TJI AS7C31024A-12TJI AS7C31024A-15TJI AS7C31024A-20TJI 5V commercial AS7C1024A-10JC AS7C1024A-12JC AS7C1024A-15JC AS7C1024A-20JC 5V industrial AS7C1024A-10JI AS7C1024A-12JI AS7C1024A-15JI AS7C1024A-20JI 3.3V commercial AS7C31024A-10JC AS7C31024A-12JC AS7C31024A-15JC AS7C31024A-20JC 3.3V industrial AS7C31024A-10JI AS7C31024A-12JI AS7C31024A-15JI AS7C31024A-20JI 5V commercial AS7C1024A-10TC AS7C1024A-12TC AS7C1024A-15TC AS7C1024A-20TC 5V industrial AS7C1024A-10TI AS7C1024A-12TI AS7C1024A-15TI AS7C1024A-20TI 3.3V commercial AS7C31024A-10TC AS7C31024A-12TC AS7C31024A-15TC AS7C31024A-20TC 3.3V industrial AS7C31024A-10TI AS7C31024A-12TI AS7C31024A-15TI AS7C31024A-20TI Part numbering system AS7C X 1024 –XX X X SRAM prefix Blank=5V CMOS 3=3.3V CMOS Device number Access time Package:T=TSOP 8×20 J=SOJ 400 mil TJ=SOJ 300 mil Temperature range C = Commercial, 0°C to 70°C I = Industrial, -40°C to 85°C 2/6/01; V.0.9 Alliance Semiconductor P. 8 of 8 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.