ATMEL ATR0635-DK1

Features
• 16-channel GPS Correlator
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– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –142 dBm (Cold Start, With External LNA)
– Tracking Sensitivity: –158 dBm (With External LNA)
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– EmbeddedICE™ (In-Circuit Emulation)
128 Kbytes Internal RAM
384 Kbytes Internal ROM with u-blox GPS Firmware SuperSense®
1.5-bit ADC On-chip
Single IF Architecture
2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
2 USARTs
Master/Slave SPI Interface
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
4 KBytes of Battery Backup Memory
7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
ANTARIS4
Single-chip
GPS Receiver
SuperSense
ATR0635
Benefits
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Fully Integrated Design With Low BOM
No External Flash Memory Required
Supports NMEA®, UBX Binary and RTCM Protocol for DGPS
Supports SBAS (WAAS, EGNOS, MSAS)
Up to 4 Hz Update Rate
Supports A-GPS (Aiding)
Excellent Noise Performance
4928H–GPS–06/08
1. Description
The ATR0635 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel®’s ANTARIS®4 technology and integrates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS TCXO and blocking capacitors
are required to realize a stand-alone GPS functionality.
The ATR0635 includes a complete GPS firmware, licensed from u-blox AG, which performs the
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory.
The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data,
configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)
and A-GPS (aiding). It is also possible to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0635
operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation.
For maximum performance, we recommend to use the ATR0635 together with a low noise
amplifier (e.g. ATR0610).
The ATR0635 supports assisted GPS.
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ATR0635
4928H–GPS–06/08
ATR0635
2. Architectural Overview
2.1
Block Diagram
Figure 2-1.
ATR0635 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VCC1
VCC2
VBP
VBAT18
VBAT
LDOBAT_IN
Power Supply Manager/
PMSS/Logic
LDO_OUT
LDO_IN
LDO_EN
AGCO
EGC
SDI
TEST
1
MO
A
SIGHI
D
RF
NRF
A
SIGLO
D
VCO
PLL
XTO
CLK23
NXTO
XTO
X
SRAM
RTC
NSHDN
NSLEEP
P20/TIMEPULSE
PIO2
P21/TXD2
P22/RXD2
P18/TXD1
USART1
PIO2
P14/NAADET1
Advanced
Interrupt
Controller
Special
Function
USART2
APB
SPI
PIO2
Controller
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
Timer
Counter
SMD
Generator
XT_IN
XT_OUT
GPS
Correlators
Advanced
Power
Management
Controller
RF_ON
P25/NAADET0
P15/ANTON
P0/NANTSHORT
GPS
Accelerator
NX
P31/RXD1
USB
Transceiver
Watchdog
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
USB_DP
USB_DM
ROM
384K
SRAM
128K
ARM7TDMI
Embedded
ICE
ASB
PDC2
B
R
I
D
G
E
USB
P16/NEEPROM
Interface to
Off-Chip
Memory
(EBI)
P9/EXTINT0
Reset
Controller
NTRST
TDI
TDO
TCK
TMS
JTAG
DBG_EN
NRESET
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4928H–GPS–06/08
2.2
General Description
The ATR0635 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0635 is based on the successful ANTARIS4 technology which includes the ANTARIS high
performance SuperSense software in ROM, developed by u-blox AG, Switzerland. ANTARIS
provides a proven navigation engine which is used in high-end car navigation systems, automatic vehicle location (AVL), security and surveying systems, traffic control, road pricing, and
speed camera detectors, and provides location-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Also, as the high performance software SuperSense is available in
ROM, no external flash memory is needed.
The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a center frequency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
2.3
PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
2.4
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression.The relation between the reference frequency (fTCXO) and the
VCO center frequency (fTCXO) is given by:
fVCO = fTCXO × 64 = 23.104 MHz × 64 = 1478.656 MHz.
2.5
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
2.6
VGA/AGC
The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally
load the input of the following analog-to-digital converter. The AGC control loop can be selected
for on-chip closed-loop operation or for baseband controlled gain mode.
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ATR0635
4928H–GPS–06/08
ATR0635
2.7
Analog-to-digital Converter
The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced
comparators and a sub-sampling unit, clocked by the reference frequency (fTCXO). The frequency spectrum of the digital output signal (f OUT ), present at the data outputs SIGLO and
SIGH1, is 4.348 MHz.
2.8
Baseband
The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM
processor core with very low power consumption. It has a high-performance 32 bit RISC architecture, uses a high-density 16-bit instruction set. The ARM standard In-Circuit Emulation debug
interface is supported via the JTAG/ICE port of the ATR0635.
The ATR0635 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides an interface
between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on- and off-chip memories without processor intervention. Most importantly, the PDC2
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Controller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or
generate an interrupt on a signal change. After reset, the user must carefully program the PIO2
Controller in order to define which peripheral signals are connected with off-chip logic.
The ATR0635 features a Programmable Watchdog Timer.
An Advanced Power Management Controller (APMC) allows for the peripherals to be deactivated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode
is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating
32.768 kHz master clock.
A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for
storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.
The ATR0635 includes the full high performance firmware (SuperSense), licensed from u-blox
AG, Switzerland. Features of the ROM firmware are described in a software documentation
available from u-blox AG, Switzerland.
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4928H–GPS–06/08
3. Pin Configuration
3.1
Pinout
Figure 3-1.
Pinning BGA96 (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
ATR0635
G
H
Table 3-1.
ATR0635 Pinout
Pin Name
BGA 96
Pin Type
AGCO
A4
Analog I/O
CLK23
A8
Digital OUT
DBG_EN
E8
Digital IN
EGC
D4
Digital IN
GDIG
C5
Supply
GND
A6
Supply
GND
A9
Supply
GND
B11
Supply
GND
F5
Supply
GND
H8
Supply
GND
H12
Supply
GNDA
A3
Supply
GNDA
B1
Supply
Notes:
Pull Resistor
(Reset Value)(1)
PIO Bank A
Firmware Label
I
O
PD
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
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ATR0635
4928H–GPS–06/08
ATR0635
Table 3-1.
Pin Name
ATR0635 Pinout (Continued)
BGA 96
Pin Type
GNDA
B4
Supply
GNDA
D2
Supply
GNDA
E1
Supply
GNDA
E2
Supply
GNDA
E3
Supply
GNDA
F1
Supply
GNDA
F2
Supply
GNDA
F3
Supply
GNDA
G1
Supply
GNDA
H1
Supply
LDOBAT_IN
D11
Supply
LDO_EN
C11
Digital IN
LDO_IN
E11
Supply
LDO_OUT
E12
Supply
MO
C3
Analog OUT
NRESET
A7
Digital I/O
NRF
C1
Analog IN
NSHDN
E9
Digital OUT
NSLEEP
E10
Digital OUT
NTRST
H11
Digital IN
Pull Resistor
(Reset Value)(1)
PIO Bank A
Firmware Label
I
O
Open Drain PU
PD
NX
B2
Analog OUT
NXTO
B3
Analog IN
P0
C8
Digital I/O
PD
NANTSHORT
P1
D8
Digital I/O
Configurable (PD)
GPSMODE0
P2
C6
Digital I/O
Configurable (PD)
BOOT_MODE
‘0’
P8
D7
Digital I/O
Configurable (PD)
STATUSLED
‘0’
P9
A11
Digital I/O
PU to VBAT18
EXTINT0
P12
D6
Digital I/O
Configurable (PU)
GPSMODE2
P13
B10
Digital I/O
PU to VBAT18
GPSMODE3
P14
G6
Digital I/O
Configurable (PD)
NAADET1
P15
F11
Digital I/O
PD
ANTON
P16
G8
Digital I/O
Configurable (PU)
NEEPROM
P17
H6
Digital I/O
Configurable (PD)
GPSMODE5
P18
C7
Digital I/O
Configurable (PU)
TXD1
P19
F6
Digital I/O
Configurable (PU)
GPSMODE6
Notes:
EXTINT0
NPCS2
EXTINT1
‘0’
SCK1
SCK1
TXD1
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
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4928H–GPS–06/08
Table 3-1.
ATR0635 Pinout (Continued)
Pin Type
PIO Bank A
Pull Resistor
(Reset Value)(1)
Firmware Label
I
O
SCK2
SCK2
Pin Name
BGA 96
P20
G7
Digital I/O
Configurable (PD)
TIMEPULSE
P21
E6
Digital I/O
Configurable (PU)
TXD2
P22
D10
Digital I/O
PU to VBAT18
RXD2
RXD2
P23
F8
Digital I/O
Configurable (PU)
GPSMODE7
SCK
TXD2
SCK
P24
H7
Digital I/O
Configurable (PU)
GPSMODE8
MOSI
MOSI
P25
G5
Digital I/O
Configurable (PD)
NAADET0
MISO
MISO
P26
B6
Digital I/O
Configurable (PU)
GPSMODE10
NSS
NPCS0
P27
F7
Digital I/O
Configurable (PU)
GPSMODE11
NPCS1
P28
E7
Digital I/O
OH
P29
D5
Digital I/O
Configurable (PU)
GPSMODE12
NPCS3
P30
G12
Digital I/O
PD
AGCOUT0
AGCOUT0
P31
C10
Digital I/O
PU to VBAT18
RXD1
PURF
G4
Digital IN
PURF
H4
Digital IN
PUXTO
F4
Digital IN
RF
D1
Analog IN
RF_ON
F10
Digital OUT
SDI
C4
Digital IN
SIGHI0
B8
Digital OUT
SIGLO0
B7
Digital OUT
TCK
G9
Digital IN
PU
TDI
H10
Digital IN
PU
TDO
F9
Digital OUT
TEST
D3
Analog IN
TMS
G10
Digital IN
USB_DM
D9
Digital I/O
USB_DP
C9
Digital I/O
VBAT
D12
Supply
(2)
C12
Supply
VBP
G2
Supply
VBP
G3
Supply
VBP
H2
Supply
VBAT18
VBP
H3
Supply
VCC1
C2
Supply
VCC2
E4
Supply
Notes:
RXD1
PD
PU
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
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ATR0635
4928H–GPS–06/08
ATR0635
Table 3-1.
Pin Name
ATR0635 Pinout (Continued)
BGA 96
(3)
VDD_USB
Pin Type
A10
Supply
VDD18
H9
Supply
VDD18
G11
Supply
VDD18
F12
Supply
VDD18
B9
Supply
VDD18
E5
Supply
B5
Supply
VDDIO
H5
Supply
VDIG
A5
Supply
X
A2
Analog OUT
XT_IN
A12
Analog IN
XT_OUT
B12
Analog OUT
XTO
A1
Analog Input
VDDIO
Notes:
(4)
Pull Resistor
(Reset Value)(1)
PIO Bank A
Firmware Label
I
O
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.
3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page
20. For operation of the USB interface, supply of 3.0V to 3.6V is required.
4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 20.
3.2
Signal Description
Table 3-2.
Pin Number
Signal Description
Pin Name
Type
Active Level Pin Description/Comment
D1
RF
ANALOG IN
-
Input from SAW filter
C1
NRF
ANALOG IN
-
Inverted input from SAW filter
A1
XTO
ANALOG IN
-
TCXO input (23.104 MHz)
B3
NXTO
ANALOG IN
-
Inverted TCXO input (23.104 MHz)
RF Section
GPS XTAL Section
A2
X
ANALOG OUT
-
XTO interface (capacitor)
B2
NX
ANALOG OUT
-
Inverted XTO interface (capacitor)
A12
XT_IN
ANALOG IN
-
Oscillator input (32.768 kHz)
B12
XT_OUT
ANALOG OUT
-
Oscillator output (32.768 kHz)
RTC Section
Automatic Gain Control, bandwidth setting
A4
AGCO
ANALOG IO
-
Automatic gain control analog voltage, connect shunt capacitor to GND
D4
EGC
DIGITAL IN
-
Enable external gain control
(high = software gain control, low = automatic gain control)
G12
AGCOUT0
DIGITAL OUT
-
Software gain control
C4
SDI
DIGITAL IN
-
Software gain control
9
4928H–GPS–06/08
Table 3-2.
Signal Description (Continued)
Pin Number
Pin Name
Type
Active Level Pin Description/Comment
BOOT_MODE
DIGITAL IN
-
NRESET
DIGITAL IN
Low
Boot Section
C6
Leave open, internal pull down
Reset
A7
Reset input; open drain with internal pull-up resistor
APMC/Power Management
E9
NSHDN
DIGITAL OUT
Low
C11
LDO_EN
DIGITAL IN
-
E10
NSLEEP
DIGITAL OUT
Low
Shutdown output, connect to LDO_EN (C11)
Enable LDO18
Power-up output for GPS XTAL, connect to PUXTO (F4)
F4
PUXTO
DIGITAL IN
-
Power-up input for GPS XTAL
G4, H4
PURF
DIGITAL IN
-
Power-up input for GPS radio
F10
RF_ON
DIGITAL OUT
-
Power-up output for GPS radio, connect to PURF (G4, H4)
Advanced Interrupt Controller (AIC)
EXTINT0-1
DIGITAL IN
High/Low/
Edge
RXD1/RXD2
DIGITAL IN
-
USART receive data
C7, E6
TXD1/TXD2
DIGITAL OUT
-
USART transmit data
H6, G7
SCK1/SCK2
DIGITAL I/O
-
External synchronous serial clock
A11, B10
External interrupt request
USART
C10, D10
USB
C9
USB_DP
DIGITAL I/O
-
USB data (D+)
D9
USB_DM
DIGITAL I/O
-
USB data (D-)
SPI Interface
F8
SCK
DIGITAL I/O
-
SPI clock
H7
MOSI
DIGITAL I/O
-
Master out slave in
G5
MISO
DIGITAL I/O
-
B6
NSS/NPCS0
DIGITAL I/O
Low
Slave select
F7, D6, D5
NPCS1/NPCS2
/NPCS3
DIGITAL OUT
Low
Slave select
P0 to P31
DIGITAL I/O
-
Programmable I/O ports
DIGITAL IN
-
GPS mode pins
NEEPROM
DIGITAL IN
Low
D7
STATUSLED
DIGITAL OUT
-
Status LED
G7
TIMEPULSE
DIGITAL OUT
-
GPS synchronized time pulse
Master in slave out
PIO
A11, B[6,10],
C[6-8,10],
D[5-8,10],
E[6,7],
F[6-8],
G[5-8],
H[6,7]
Configuration
B[6,10],
D[5,6,8],
GPSMODE0-12
F[6-8], H[6,7]
G8
Enable EEPROM support
GPS
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4928H–GPS–06/08
ATR0635
Table 3-2.
Signal Description (Continued)
Pin Number
Pin Name
Type
Active Level Pin Description/Comment
Active Antenna Supervision
C8
NANTSHORT
DIGITAL IN
Low
Active antenna short detection Input
G5, G6
NAADET0/
NAADET1
DIGITAL IN
Low
Active antenna detection Input
F11
ANTON
DIGITAL OUT
-
Active antenna power-on Output
JTAG Interface
E8
DBG_EN
DIGITAL IN
-
Debug enable
F9
TDO
DIGITAL OUT
-
Test data out
G9
TCK
DIGITAL IN
-
Test clock
G10
TMS
DIGITAL IN
-
Test mode select
H10
TDI
DIGITAL IN
-
Test data in
H11
NTRST
DIGITAL IN
Low
Test reset input
MO
ANALOG OUT
-
IF output buffer
Debug/Test
C3
D3
TEST
ANALOG IN
-
Enable IF output buffer
B7
SIGLO
DIGITAL OUT
-
Digital IF (data output “Low”)
B8
SIGHI
DIGITAL OUT
-
Digital IF (data output “High”)
A8
CLK23
DIGITAL OUT
-
Digital IF (sample clock)
Power Analog Part
C2
VCC1
SUPPLY
-
Analog supply 3V
E4
VCC2
SUPPLY
-
Analog supply 3V
G2, G3, H2,
H3
VBP
SUPPLY
-
Analog supply 3V
A3, B1, B4,
D2, E[1-3],
F[1-3], G1,
H1
GNDA
SUPPLY
-
Analog Ground
Power Digital Part
A5
VDIG
SUPPLY
-
Digital supply (radio) 1.8V
B9, E5, F12,
G11,H9
VDD18
SUPPLY
-
Core voltage 1.8V
A10
VDD_USB
SUPPLY
-
USB transceiver supply voltage (3.0V to 3.6V (USB enabled) or 0 to
2.0V (USB disabled))
B5, H5
VDDIO
SUPPLY
-
Variable I/O voltage 1.65V to 3.6V
C5
GDIG
SUPPLY
-
Digital ground (radio)
A6, A9, B11,
F5, H8, H12
GND
SUPPLY
-
Digital ground
E11
LDO_IN
SUPPLY
-
2.3V to 3.6V
E12
LDO_OUT
SUPPLY
-
1.8V LDO18 output, max. 80 mA
D11
LDOBAT_IN
SUPPLY
-
2.3V to 3.6V
D12
VBAT
SUPPLY
-
1.5V to 3.6V
C12
VBAT18
SUPPLY
-
1.8V LDOBAT Output
LDO18
LDOBAT
11
4928H–GPS–06/08
3.3
Setting GPSMODE0 to GPSMODE12
The start-up configuration of this ROM-based system without external non-volatile memory is
defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be
configured through message commands passed through the serial interface after start-up. This
configuration of the ATR0635 can be stored in an external non-volatile memory like EEPROM.
Default designates settings used by ROM firmware if GPSMODE configuration is disabled
(GPSMODE0 = 0).
Table 3-3.
GPSMODE Functions
Pin
Function
GPSMODE0 (P1)
Enable configuration with GPSMODE pins
GPSMODE1 (P9)
This pin (EXTINT0) is used for FixNOW™ functionality and not used for GPSMODE
configuration.
GPSMODE2 (P12)
GPSMODE3 (P13)
GPSMODE4 (P14)
GPSMODE5 (P17)
GPSMODE6 (P19)
GPS sensitivity settings
This pin (NAADET1) is used as active antenna supervisor input and not used for
GPSMODE configuration. This is the default selection if GPSMODE configuration is
disabled.
Serial I/O configuration
GPSMODE7 (P23)
USB power mode
GPSMODE8 (P24)
General I/O configuration
GPSMODE9 (P25)
This pin (NAADET0) is used as an active Antenna Supervisor input and not used for
GPSMODE configuration
GPSMODE10 (P26)
GPSMODE11 (P27)
General I/O configuration
GPSMODE12 (P29) Serial I/O configuration
In the case that GPSMODE pins with internal pull-up or pull-down resistors are connected to
GND/VDD18, additional current is drawn over these resistors. Especially GPSMODE3 can
impact the back-up current.
3.3.1
Enable GPSMODE Pin Configuration
Table 3-4.
Enable Configuration With GPSMODE Pins
GPSMODE0
(Reset = PD) Description
0(1)
1
Note:
Ignore all GPSMODE pins. The default settings as indicated below are used.
Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12]
1. Leave open
If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins are
not connected externally, the reset default values of the internal pull-down and pull-up resistors
will be used.
12
ATR0635
4928H–GPS–06/08
ATR0635
3.3.2
Sensitivity Settings
Table 3-5.
GPSMODE3
(Fixed PU)
0(1)
(1)
GPSMODE2
(Reset = PU) Description
0
Auto mode (Default ROM value)
(2)
Fast mode
0
Normal mode
1
0
(2)
1
1(2)
Notes:
GPS Sensitivity Settings
1(2)
High sensitivity
1. Increased back-up current
2. Leave open
For all GPS receivers the sensitivity depends on the integration time of the GPS signals. Therefore there is a trade-off between sensitivity and the time to detect the GPS signal (Time to first
fix). The three modes, “Fast Acquisition”, “Normal” and “High Sensitivity”, have a fixed integration time. The “Normal” mode, recommended for the most applications, is a trade off between
the sensitivity and TTFF. The “Fast Acquisition” mode is optimized for fast acquisition, at the
cost of a lower sensitivity. The “High Sensitivity” mode is optimized for higher sensitivity, at the
cost of longer TTFF. The “Auto” mode adjusts the integration time (sensitivity) automatically
according to the measured signal levels. That means the receiver with this setting has a fast
TTFF at strong signals, a high sensitivity to acquire weak signals but some times at medium signal level a higher TTFF as the “Normal” mode. These sensitivity settings affect only the startup
performance not the tracking performance.
3.4
Serial I/O Configuration
The ATR0635 features a two-stage I/O-message and protocol-selection procedure for the two
available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given
USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second
stage, messages can be enabled or disabled for each enabled protocol on each port. In all configurations described below, all protocols are enabled on all ports, but output messages are
enabled in a way that ports appear to communicate at only one protocol. However, each port will
accept any input message in any of the three implemented protocols
Table 3-6.
Serial I/O Configuration
GPSMODE12
(Reset = PU)
GPSMODE6
(Reset = PU)
0
0
USART1/USB
USART2
GPSMODE5 (Output Protocol/
(Output Protocol/
(Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages(1) Information Messages
0(2)
UBX/57.6
NMEA/19.2
High
User, Notice, Warning, Error
0
0
1
UBX/38.4
NMEA/9.6
Medium
User, Notice, Warning, Error
0
1(2)
0(2)
UBX/19.2
NMEA/4.8
Low
User, Notice, Warning, Error
0
(2)
1
–/Auto
–/Auto
Off
None
0
(2)
NMEA/19.2
UBX/57.6
High
User, Notice, Warning, Error
1
1
(2)
1
(2)
0
0
1
NMEA/4.8
UBX/19.2
Low
User, Notice, Warning, Error
1(2)
1(2)
0(2)
NMEA/9.6
UBX/38.4
Medium
User, Notice, Warning, Error
1(2)
1(2)
1
UBX/115.2
NMEA/19.2
Debug
All
Notes:
1. See Table 3-7 to Table 3-10 on page 14, the messages are described in the ANTARIS4 protocol specification
2. Leave open
13
4928H–GPS–06/08
Both USART ports accept input messages in all three supported protocols (NMEA, RTCM and
UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed.
Response to a query input message will always use the same protocol as the query input message. The USB port does only accept NMEA and UBX as input protocol by default. RTCM can
be enabled via protocol messages on demand.
In Auto mode, no output message is sent out by default, but all input messages are accepted at
any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols. Response
to query input commands will be given by the same protocol and baud rate as it was used for the
query command. Using the respective configuration commands, periodic output messages can
be enabled.
The following message settings are used in the tables below:
Table 3-7.
NMEA Port
UBX Port
Table 3-8.
NMEA Port
UBX Port
Table 3-9.
NMEA Port
UBX Port
Table 3-10.
NMEA Port
UBX Port
14
Supported Messages at Setting Low
Standard
GGA, RMC
NAV
SOL, SVINFO
MON
EXCEPT
Supported Messages at Setting Medium
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA
NAV
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
Supported Messages at Setting High
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
Proprietary
PUBX00, PUBX03, PUBX04
NAV
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
MON
SCHD, IO, IPC, EXCEPT
Supported Messages at Setting Debug (Additional Undocumented Message May
be Part of Output Data)
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
Proprietary
PUBX00, PUBX03, PUBX04
NAV
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
MON
SCHD, IO, IPC, EXCEPT
RXM
RAW (RAW message support requires an additional license)
ATR0635
4928H–GPS–06/08
ATR0635
The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0
(ROM defaults):
Table 3-11.
Serial I/O Default Setting if GPSMODE Configuration is Deselected
(GPSMODE0 = 0)
USB
NMEA
USART1
NMEA
Baud rate (kBaud)
57.6
57.6
Input protocol
UBX, NMEA
UBX, NMEA, RTCM
UBX, NMEA, RTCM
Output protocol
NMEA
NMEA
UBX
Messages
GGA, RMC, GSA, GSV
GGA, RMC, GSA, GSV
NAV: SOL, SVINFO
MON: EXCEPT
User, Notice, Warning,
Error
User, Notice, Warning,
Error
Information
User Notice, Warning,
messages (UBX INF
Error
or NMEA TXT)
3.4.1
USART2
UBX
USB Power Mode
For correct response to the USB host queries, the device has to know its power mode. This is
configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported
to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with
no more than one USB power unit load.
Table 3-12.
USB Power Modes
GPSMODE7 (Reset = PU) Description
0
USB device is bus-powered (maximum current limit 100 mA)
(1)
USB device is self-powered (default ROM value)
1
Note:
3.4.2
1. Leave open
Active Antenna Supervisor
The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or
P14/NAADET1 are always initialized as general purpose I/Os and used as follows:
• P15/ANTON is an output which can be used to switch on and off antenna power supply.
• Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the
antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is assumed
that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its active low state.
• Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In
case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is
switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will
signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14
or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14 on
page 16).
15
4928H–GPS–06/08
Table 3-13.
Pin Usage of Active Antenna Supervisor
Pin
Usage
Meaning
P0/NANTSHORT
NANTSHORT
Active antenna short circuit detection
High = No antenna DC short circuit present
Low = Antenna DC short circuit present
P25/NAADET0/
MISO or
P14/NAADET1
NAADET
Active antenna detection input
High = No active antenna present
Low = Active antenna is present
P15/ANTON
ANTON
Active antenna power on output
High = Power supply to active antenna is switched on
Low = Power supply to active antenna is switched off
Table 3-14.
Antenna Detection I/O Settings
GPSMODE11 GPSMODE10 GPSMODE8
(Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET
0
0
0
P25/NAADET0/MISO
0
0
(1)
P25/NAADET0/MISO
0
1(1)
0
P14/NAADET1
0
1(1)
1(1)
1(1)
0
0
P14/NAADET1
Reserved for further use.
Do not use this setting.
1(1)
0
1(1)
P14/NAADET1
Reserved for further use.
Do not use this setting.
1(1)
1(1)
0
P25/NAADET0/MISO
(1)
1(1)
1(1)
P25/NAADET0/MISO
1
Note:
Comment
1
Reserved for further use.
Do not use this setting.
P14/NAADET1
(Default ROM value)
1. Leave open
The Antenna Supervisor Software will be configured as follows:
1. Enable Control Signal
2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected via
NANTSHORT)
3. Enable Open Circuit Detection via NAADET
The antenna supervisor function may not be disabled by GPSMODE pin selection.
If the antenna supervisor function is not used, please leave open ANTON, NANTSHORT and
NAADET.
16
ATR0635
4928H–GPS–06/08
ATR0635
3.4.3
External Connections for a Working GPS System
Figure 3-2.
Example of an External Connection (ATR0635)
ATR0635
LNA
(optional)
SAW
NC
NC
NC
SIGHI
SIGLO
CLK23
RF
NRF
ATR0610
RF_ON
PURF
NSLEEP
PUXTO
NC
NC
NC
NC
NC
NC
NC
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
NRESET
TMS
TCK
TDI
NTRST
TDO
DBG_EN
P0 - 2
P9
P12 - 17
P19
P23 - 27
P29 - 30
P30/AGCOUT0
SDI
NC
NC
GND analog
MO
TEST
EGC
XT_IN
32.768 kHz
(see RTC)
XT_OUT
XTO
TCXO
23.104 MHz
(see GPS Crystal)
NXTO
X
NX
P8
P20
NC
NC
STATUS LED
TIMEPULSE
USB_DM
USB_DP
Optional
USB
P31
P18
Optional
USART 1
P22
P21
Optional
USART 2
AGCO
GND digital
GND analog
GND
GNDD
GNDA
NSHDN
LDO_EN
LDO_OUT
VDD18
VDIG
+3V
(see Power Supply)
LDO_IN
LDOBAT_IN
VBAT18
VBAT
+3V
(see Power Supply)
VDDIO
+3V
(see Power Supply)
VDD_USB
+3V
(see Power Supply)
VCC1
VCC2
VBP
+3V
(see Power Supply)
GND
NC: Not connected
17
4928H–GPS–06/08
Table 3-15.
Recommended Pin Connections
Pin Name
Recommended External Circuit
P0/NANTSHORT
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
P1/GPSMODE0
Internal pull-down resistor; leave open in order to disable the GPSMODE pin configuration feature. Connect
to VDD18 to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in “Setting
GPSMODE0 to GPSMODE12” on page 12.
P2/BOOT_MODE
Internal pull-down resistor; leave open.
P8/STATUSLED
Output in default ROM firmware: leave open if not used
P9/EXTINT0
Internal pull-up resistor; leave open if unused.
P12/GPSMODE2/NPCS2
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P13/GPSMODE3/
EXTINT1
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P14/NAADET1
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
P15/ANTON
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
P16/NEEPROM
Internal pull-up resistor; leave open if no serial EEPROM is connected. Otherwise connect to GND.
P17/GPSMODE5/SCK1
Internal pull-down resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P18/TXD1
Output in default ROM firmware: leave open if serial interface is not used.
P19/GPSMODE6/SIGLO1
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P20/TIMEPULSE/SCK2
Output in default ROM firmware: leave open if time pulse feature is not used.
P21/TXD2
Output in default ROM firmware: leave open if serial interface not used.
P22/RXD2
Internal pull-up resistor; leave open if serial interface is not used.
P23/GPSMODE7/SCK
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P24/GPSMODE8/MOSI
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P25/NAADET0/MISO
Internal pull-down resistor; leave open if Antenna Supervision functionality is unused.
P26/GPSMODE10/NSS/
NPCS0
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P27/GPSMODE11/NPCS1
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P29/GPSMODE12/NPCS3
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE
definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.
P30/AGCOUT0
Internal pull-down resistor; leave open.
P31/RXD1
Internal pull-up resistor; leave open if serial interface is not used.
18
ATR0635
4928H–GPS–06/08
ATR0635
3.5
Connecting an Optional Serial EEPROM
The ATR0635 offers the possibility of connecting an external serial EEPROM. The internal ROM
firmware supports storing the configuration of the ATR0635 in serial EEPROM. The pin
P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0635. The
ATR0635’s 32-bit RISC processor accesses the external memory via SPI (serial peripheral interface). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel’s AT25320AY1-1.8.
Figure 3-3 shows an example of the serial EEPROM connection.
Figure 3-3.
Example of a Serial EEPROM Connection
AT25320AY1-1.8
ATR0635
P23/SCK
P24/MOSI
P25/MISO/NAADET0
P29/NPCS3
SCK
SI
SO
CS_N
HOLD_N
WP_N
GND
NC
P16/NEEPROM
P1/GPSMODE0
GND
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
VDDIO
+3V
(see Power Supply)
LDO_IN
LDOBAT_IN
NC: Not connected
Note:
The GPSMODE pin configuration feature can be disabled, because the configuration can be
stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.
19
4928H–GPS–06/08
4. Power Supply
The ATR0635 is supplied with six distinct supply voltages:
• The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V.
• VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG
should be connected to VDD18.
• VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and
the test pins and all GPIO pins not mentioned in next item.
• VDDIO, the variable supply voltage within 1.8V to 3.6V for the following GPIO pins: P1, P2,
P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. In input
mode, these pins are 5V input tolerant.
• VDD_USB, the power supply of the USB pins: USB_DM and USB_DP.
• VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN,
LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz
oscillator. In input mode, the four GPIO-pins are 5V input tolerant.
20
ATR0635
4928H–GPS–06/08
ATR0635
Figure 4-1.
Connecting Example: Separate Power Supplies for RF and Digital Part Using the Internal LDOs
ATR0635 internal
VCC1
2.7V to 3.3V
VCC2
RF
VBP
VDIG
2.3V to 3.6V
LDO_IN
NSHDN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
VDD18
Core
VDDIO
1.8V to 3.3V
variable I/O domain
1 µF
(X7R)
ldobat_in
LDOBAT
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
vbat
vbat18
VDD
1 µF
(X7R)
RTC
backup memory
0V or 3V to 3.6V
VDDUSB
USB SM and
transceiver
The ATR0635 contains a built in low dropout voltage regulator LDO18. This regulator can be
used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case,
LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V.
The LDO_EN input can be used to shut down VDD18 if the system is in standby mode.
If the host system does supply a 1.8V core voltage directly, this voltage has to be connected to
the VDD18 supply pins of the Core. LDO_EN must be connected to GND. LDO_IN can be connected to GND. LDO_OUT must not be connected.
A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the RTC
and backup SRAM from any input voltage VBAT between 1.5V and 3.6V. The backup battery
delivers the supply current if LDOBAT_IN is not powered.
21
4928H–GPS–06/08
The RTC section will be initialized properly if VDD18 is supplied first to the ATR0635. If VBAT is
applied first, the current consumption of the RTC and backup SRAM is undetermined.
Figure 4-2.
Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs
ATR0635 internal
VCC1
VCC2
RF
VBP
VDIG
2.7V to 3.3V
LDO_IN
NSHDN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
VDD18
Core
VDDIO
1.8V to 3.3V
variable IO domain
1 µF
(X7R)
ldobat_in
LDOBAT
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
vbat
vbat18
VDD
1 µF
(X7R)
RTC
backup memory
0V or 3V to 3.6V
VDDUSB
USB SM and
transceiver
The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and
USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled
if VDD_USB within 3.0V and 3.6V.
22
ATR0635
4928H–GPS–06/08
ATR0635
Figure 4-3.
Connecting Example: Separate Power Supplies for RF and Digital Part Using 1.8V from Host System
ATR0635 internal
VCC1
2.7V to 3.3V
VCC2
RF
VBP
VDIG
LDO_IN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
1.65V to 1.95V
VDD18
Core
VDDIO
1.8V to 3.3V
variable I/O domain
1 µF
(X7R)
ldobat_in
2.3V to 3.6V
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
LDOBAT
vbat
vbat18
VDD
1 µF
(X7R)
RTC
backup memory
0V or 3V to 3.6V
VDDUSB
USB SM and
transceiver
23
4928H–GPS–06/08
Figure 4-4.
Connecting Example: Power Supply from USB Using the Internal LDOs
ATR0635 internal
VCC1
VCC2
RF
VBP
VDIG
LDO_IN
NSHDN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
VDD18
Core
VDDIO
1.8V to 3.3V
variable I/O domain
1 µF
(X7R)
ldobat_in
LDOBAT
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
vbat
vbat18
VDD
1 µF
(X7R)
RTC
backup memory
USB-VSB 5V
24
External LDO
3.0V to 3.3V
VDDUSB
USB SM and
transceiver
ATR0635
4928H–GPS–06/08
ATR0635
5. Crystals
The ATR0635 requires a GPS TCXO. The reference frequency is 23.104 MHz. By connecting
an optional RTC crystal, different power modes are available. The reference frequency is 32.768
kHz.
5.1
GPS
Figure 5-1.
Equivalent Application Examples Using a GPS TCXO (See Table 5-1 on page 26)
22 pF
A1
XTO
12 pF
B3
TCXO
4.7 pF
NXTO
A2
Do not
connect
X
B2
NX
A1
12 pF
XTO
22 pF
B3
TCXO
4.7 pF
A2
Do not
connect
NXTO
X
B2
NX
Figure 5-2.
Application Example Using an External Reference Frequency and Balanced
Inputs (See Table 5-2 on page 26)
1:1
A1
XTO
Vin
B3
A2
Do not
connect
B2
NXTO
X
NX
25
4928H–GPS–06/08
Table 5-1.
Specification of GPS TCXOs Appropriate for the Application Example Shown in
Figure 5-1 on page 25
Parameter
Comment
Min
Typ
Max
Units
Frequency Characteristics
Nominal frequency referenced to
25°C
Nominal Frequency
23.104
MHz
Over operating temperature range
0.5
±ppm
Frequency deviation
Including calibration, temperature,
soldering and ageing effects
8
±ppm
Temperature range
Operating temperature range
–40.0
+85.0
°C
1.5
V
Electrical
Output waveform
DC coupled clipped sine wave
Output voltage
(peak-to-peak)
Operating range
0.8
Output load capacitance
Tolerable load capacitance
10
Table 5-2.
pF
Specification of an External Reference Signal for the Application Example Shown
in Figure 5-2 on page 25
Parameter
Comment
Min
Typ
Max
Units
Signal Characteristics
Nominal Frequency
5.2
23.104
Waveform
Sine wave or clipped sine wave
Amplitude
Voltage peak-to-peak
0.6
0.9
MHz
1.2
V
RTC Oscillator
Figure 5-3.
Crystal Connection
ATR0635 internal
XT_IN
32 kHz
Crystal
Oscillator
32.768 kHz
50 ppm
32.768 kHz clock
RTC
XT_OUT
C
C
C = 2 × Cload, Cload can be derived from the crystal datasheet. Maximum value for C is 25 pF.
26
ATR0635
4928H–GPS–06/08
ATR0635
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min
Max
Unit
Operating temperature
Top
–40
+85
°C
Storage temperature
Tstg
–55
+125
°C
VCC
–0.3
+3.7
V
Analog supply voltage
Pins
VCC1, VCC2, VBP
Digital supply voltage RF
VDIG
VDIG
–0.3
+3.7
V
DC supply voltage core
VDD18
VDD18
–0.3
+1.95
V
DC supply voltage VDDIO
domain
VDDIO
VDDIO
–0.3
+3.6
V
DC supply voltage USB
VDD_USB
VDD_USB
–0.3
+3.6
V
DC supply voltage LDO18
LDO_IN
LDO_IN
–0.3
+3.6
V
DC supply voltage LDOBAT
LDOBAT_IN
LDOBAT_IN
–0.3
+3.6
V
DC supply voltage VBAT
VBAT
VBAT
–0.3
+3.6
V
Digital input voltage
P0, P15, P30, XT_IN,
TMS, TCK, TDI, NTRST,
DBG_EN, LDO_EN,
NRESET
–0.3
+1.95
V
Digital input voltage
USB_DM, USB_DP
–0.3
+3.6
V
+5.0
V
P1, P2, P8, P9, P12 to
Digital input voltage
–0.3
P14, P16 to P27, P29, P31
Note:
Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified.
7. Handling
The ATR0635 is an ESD-sensitive device. The current ESD values are to be defined. Observe
proper precautions for handling.
8. Thermal Resistance
Parameters
Junction ambient according to JEDEC51-5
Symbol
Value
Unit
RthJA
49.5
K/W
27
4928H–GPS–06/08
9. Operating Range
Parameters
Analog supply voltage RF
Pins
Symbol
Min
VCC1, VCC2, VBP
VCC
2.70
Typ
Max
Unit
3.30
V
Digital supply voltage RF
VDIG
VDIG
1.65
1.8
1.95
V
Digital supply voltage core
VDD18
VDD18
1.65
1.8
1.95
V
Digital supply voltage VDDIO
domain(1)
VDDIO
VDDIO
1.65
1.8/3.3
3.6
V
Digital supply voltage USB(2)
VDD_USB
VDD_USB
3.0
3.3
3.6
V
DC supply voltage LDO18
DC supply voltage LDOBAT
DC Supply voltage VBAT
LDO_IN
LDO_IN
2.3
3.6
V
LDOBAT_IN
LDOBAT_IN
2.3
3.6
V
VBAT
VBAT
1.5
3.6
V
Supply voltage difference
(VΔ = VCC – VDIG)
≥ 0.80
VΔ
Temperature range
Temp
–40
V
+85
°C
fRF
1575.42
MHz
Reference frequency GPS XTAL
fTCXO
23.104
MHz
Reference frequency RTC
fXTC
32.768
KHz
Input frequency
Notes:
1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
2. Values defined for operating USB Interface. Otherwise VDD_USB may be connected to ground.
10. Electrical Characteristics
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No. Parameters
1
Test Conditions
Pin
Symbol
fTXCO = 23.104 MHz
C3
fIF
D1, C1
Min
Typ
Max
Unit
Type*
96.764
MHz
A
Z11
10 – j80
Ω
C
RF Front-end
1.1 Output frequency
1.2 Input impedance (balanced) fRF = 1575.42 MHz
1.3 Mixer conversion gain
C3
GMIX
10
dB
C
1.4 Mixer noise figure (SSB)
C3
NFMIX
6
dB
C
Gmax_tot
90
dB
C
NFtot
6.8
dB
C
1.5 Maximum total gain
VAGCO = 2.2V
1.6 Total noise figure (SSB)
2
VGA/AGC
2.1 Minimum gain
VAGCO = 1.0V
GVGA,min
0
dB
C
2.2 Maximum gain
VAGCO = 2.2V
GVGA,max
70
dB
C
VAGCO = 2.2V
NVGA,min
6.6
dB/V
D
VAGCO = 1.0V
NVGA,max
150
dB/V
D
2.3 Control-voltage sensitivity
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
28
ATR0635
4928H–GPS–06/08
ATR0635
10. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No. Parameters
Test Conditions
Pin
Symbol
2.4 AGC cut-off frequency
Cext = open
A4
f3dB_AGC
2.5 AGC cut-off frequency
Cext = 100 pF
A4
f3dB_AGC
Unit
Type*
250
kHz
D
33
kHz
D
3.1 Voltage level power-on
F4, G4,
H4
VPU,on
V
C
3.2 Voltage level power-off
F4, G4,
H4
VPU,off
0.5
V
C
1.95
V
A
30
mA
A
80
µA
A
1
5
µA
A
1.8
1.95
V
A
After startup (sleep/backup
mode), at room
temperature
15
µA
A
After startup (backup mode
5.3 Current consumption VBAT and LDOBAT_IN = 0V), at
room temperature
10
µA
A
1.5
mA
C
3
4
LDO_OUT
1.3
1.65
1.8
LDO_OUT
4.3 Current consumption
After startup, no load, at
room temperature
4.4 Current consumption
Standby mode
(LDO_EN = 0), at room
temperature
LDOBAT(2)
5.1 Output voltage(3)
Current consumption
LDOBAT_IN(4)
5.4 Current consumption
6
Max
LDO18(1)
4.2 Output current
5.2
Typ
PMSS
4.1 Output voltage
5
Min
VBAT18
1.65
After startup (normal
mode), at room
temperature
Core
6.1 DC supply voltage VDD18
VO,18
0
VDD18
V
D
6.2 DC supply voltage VDDIO
VO,IO
0
VDDIO
V
D
6.3
Low-level input voltage
VDD18 domain
VDD18 = 1.65V to 1.95V
VIL,18
–0.3
0.3 ×
VDD18
V
C
6.4
High-level input voltage
VDD18 domain
VDD18 = 1.65V to 1.95V
VIH,18
0.7 ×
VDD18
VDD18
+ 0.3
V
C
6.5
Schmitt trigger threshold
rising
VDD18 = 1.65V to 1.95V
CLK23
Vth+,CLK23
0.7 ×
VDD18
V
C
6.6
Schmitt trigger threshold
falling
VDD18 = 1.65V to 1.95V
CLK23
Vth-,CLK23
V
C
0.3 ×
VDD18
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
29
4928H–GPS–06/08
10. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No. Parameters
Test Conditions
6.7 Schmitt trigger hysteresis
VDD18 = 1.65V to 1.95V
Pin
Symbol
Min
CLK23
Vhyst,CLK23
Typ
Max
Unit
Type*
0.2
0.55
V
C
6.8
Schmitt trigger threshold
rising
VDD18 = 1.65V to 1.95V
NRESET Vth+,NRESET
0.8
1.3
V
C
6.9
Schmitt trigger threshold
falling
VDD18 = 1.65V to 1.95V
NRESET Vth-,NRESET
0.46
0.77
V
C
6.10
Low-level input voltage
VDDIO domain
VDDIO = 1.65V to 3.6V
VIL,IO
–0.3
+0.41
V
C
6.11
High-level input voltage
VDDIO domain
VDDIO = 1.65V to 3.6V
VIH,IO
1.46
5.0
V
C
6.12
Low-level input voltage
VBAT18 domain
VBAT18 = 1.65V to 1.95V
A11, B10,
C10, D10
VIL,BAT
–0.3
+0.41
V
C
6.13
High-level input voltage
VBAT18 domain
VBAT18 = 1.65V to 1.95V
A11, B10,
C10, D10
VIH,BAT
1.46
5.0
V
C
C9, D9
VIL,USB
–0.3
+0.8
V
C
C9, D9
VIH,USB
2.0
4.6
V
C
0.4
V
A
V
A
V
A
V
A
V
A
V
A
V
A
V
A
+1
µA
C
10
pF
D
6.14 Low-level input voltage USB VDD_USB = 3.0V to 3.6V
6.15
High-level input voltage
USB
VDD_USB = 3.0V to 3.6V
39Ω source resistance +
27Ω external series resistor
6.16
Low-level output voltage
VDD18 domain
IOL = 1.5 mA,
VDD18 = 1.65V
VOL,18
6.17
High-level output voltage
VDD18 domain
IOH = –1.5 mA,
VDD18 = 1.65V
VOH,18
6.18
Low-level output voltage
VDDIO domain
IOL = 1.5 mA,
VDDIO = 3.0V
VOL,IO
6.19
High-level output voltage
VDDIO domain
IOH = –1.5 mA,
VDDIO = 3.0V
VOH,IO
6.20
Low-level output voltage
VBAT18 domain
IOL = 1 mA
P9, P13,
P22, P31
VOL,BAT
6.21
High-level output voltage
VBAT18 domain
IOH = –1 mA
P9, P13,
P22, P31
VOH,BAT
6.22
Low-level output voltage
USB
IOL = 2.2 mA,
VDD_USB = 3.0V to 3.6V,
27Ω external series resistor
DP, DM
VOL,USB
6.23
High-level output voltage
USB
IOH = 0.2 mA,
VDD_USB = 3.0V to 3.6V,
27Ω external series resistor
DP, DM
VOH,USB
2.8
6.24
Input-leakage current
(standard inputs and I/Os)
VDD18 = 1.95V
VIL = 0V
ILEAK
–1
6.25 Input capacitance
VDD18
– 0.45
0.4
VDDIO
– 0.5
0.4
1.2
0.3
ICAP
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
30
ATR0635
4928H–GPS–06/08
ATR0635
10. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.
No. Parameters
Test Conditions
Pin
Symbol
Min
A7
RPU
Typ
Max
Unit
Type*
0.7
1.8
kΩ
C
6.26
Input pull-up resistor
NRESET
6.27
Input pull-up resistors TCK,
TDI, TMS
G9, H10,
G10
RPU
7
18
kΩ
C
6.28
Input pull-up resistors P9,
P13, P22, P31
A11, B10,
C10, D10
RPU
100
235
kΩ
C
6.29
Input pull-down resistors
DBG_EN, NTRST, RF_ON
E8, H11
RPD
7
18
kΩ
C
6.30
Input pull-down resistors
P0, P15, P30
F10, C8,
F11, G12
RPD
100
235
kΩ
C
Configurable input pull-up
resistors P1, P2, P8, P12,
6.31
P14, P16 to P21, P23 to
P27, P29
VDDIO = 3.6V,
VPAD = 0V
RCPU
50
160
kΩ
C
Configurable input
pull-down resistors P1, P2,
6.32
P8, P12, P14, P16 to P21,
P23 to P27, P29
VDDIO = 3.6V,
VPAD = 3.6V
RCPD
40
160
kΩ
C
Configurable input pull-up
resistor USB_DP (idle state)
C9
RCPU
0.9
1.575
kΩ
C
Configurable input pull-up
6.34 resistor USP_DP (operation
state)
C9
RCPU
1.425
3.09
kΩ
C
C9, D9
RPD
10
500
kΩ
C
6.33
6.35
Input pull-down resistors
USB_DP, USB_DM
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18.
2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup
SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN
falls below 1.5V.
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.
4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
31
4928H–GPS–06/08
11. Power Consumption
Table 11-1.
Power Consumption
Mode
Conditions
Sleep
At 1.8V, no CLK23
0.065
C
Shutdown
RTC, backup SRAM and LDOBAT
0.007
C
Normal
Typ.
Unit
Type*
Satellite acquisition
40
Normal tracking on 6 channels with 1 fix/s; each
additional active tracking channel adds 0.5 mA
29
C
All channels disabled
26
C
mA
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design
parameter
32
ATR0635
4928H–GPS–06/08
ATR0635
12. Ordering Information
Extended Type Number
Package
MPQ
Remarks
ATR0635-7KQY
BGA96
3000
7 mm × 10 mm, 0.8 mm pitch, Pb-free,
RoHS-compliant
ATR0635-EK1
-
1
Evaluation kit/Road test kit
1
Design kit including design guide and PCB
Gerber files
ATR0635-DK1
-
13. Package Information
Package: BGA96
Dimensions in mm
n 0.08 m
n 0.15 m
2.
C
BA
0.4±0.05
A1 Corner
Top View
Bottom View
A1 Corner
A
B
C
D
E
F
G
H
0.8
7±0.05
0.8
Pin A1 Laser Marking
A
8.8
10±0.05
B
technical drawings
according to DIN
specifications
0.75±0.05
A
B
C
D
E
F
G
H
12 11 10 9 8 7 6 5 4 3 2 1
5.6
1 2 3 4 5 6 7 8 9 10 11 12
0.1 C
0.08 C
0.3±0.05
1.4 max
Issue: 2; 31.05.06
Seating plane
3.
C
0.26±0.04
Drawing-No.: 6.580-5005.01-4
Note:
1. All dimensions and tolerance conform to ASME Y 14.5M-1994
2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C
3. Primary datum C and seating plane are defined by the spherical crowns of the solder balls
4. The surface finish of the package shall be EDM CHARMILLE #24 - #27
5. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2˚
5. Raw ball diameter: 0.4 mm ref.
33
4928H–GPS–06/08
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
34
Revision No.
History
4928H-GPS-06/08
• Section 8 “Thermal Resistance” on page 27 added
• Section 10 “Electrical Characteristics” numbers 2.6 and 2.7 on page 29
deleted
• Section 10 “Electrical Characteristics” numbers 4.2, 6.7 and 6.26 to 6.35
on pages 29 to 31 changed
4928G-GPS-09/07
• Table 3-1 “ATR0635 Pinout” on page 6 changed
4928F-GPS-06/07
• Section 9 “Electrical Characteristics” numbers 6.31 and 6.32 on page 31
changed
4928E-GPS-03/07
• Table 3-2 “Signal Description” on pages 9 to 11 changed
• Table 10-1 “Power Consumption” on page 32 changed
4928D-GPS-01/07
• Put datasheet in a new template
•Table 3-11 “Serial I/O Default Setting if GPSMODE Configuration is
Deselected (GPSMODE0 = 0)” on page 15 changed
• Section 9 “Electrical Characteristics” on pages 28 to 31 changed
• Section 10 “Power Consumption” on page 32 changed
ATR0635
4928H–GPS–06/08
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4928H–GPS–06/08