AZM AZT71HG

AZT71
Programmable Capacitive Tuning IC
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DESCRIPTION
FEATURES
The AZT71 is a digitally programmed capacitor specifically designed to
tune a crystal or SAW based oscillator to a desired center frequency. The
desired capacitance value for production trimming is set by a serial data
stream when placed into a programming mode. The AZT71 is designed to
be a labor and cost saving device within the oscillator production process.
•
Capacitive tuning range of
6.6pF to 37.553pF
(See AZT70 for different values)
•
•
Using EEPROM technology, the capacitance can be re-tuned as needed
during the production process by repeating the programming steps
thereby increasing production yield.
•
The AZT71 is available in an SON8 package (1.5mm x 1.0mm) for very
small form factor oscillators. Also available in MLP6 and TSOT6.
•
•
0.063pF minimum step size
Reprogrammable through
nonvolatile EEPROM storage
May be placed in parallel for
greater capacitance values
Very low supply current
2.5V to 3.6V supply voltage
BLOCK DIAGRAM
APPLICATIONS
•
•
Fast production tuning of crystal
or SAW oscillators
Filters requiring capacitive tuning
PACKAGE AVAILABILITY
•
•
•
SON8
MLP6
TSOT6
•
All are Green/RoHS/Pb-Free
Order Number
Package
Marking
AZT71QG1
SON8
Y <Date Code>2
AZT71HG1
TSOT6
Y1G<Date Code>2
AZT71MG1
MLP6
Y1G<Date Code>2
1
Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in
2
See www.azmicrotek.com for date code format
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May 2012, Rev 1.2
Arizona Microtek, Inc.
AZT71
Programmable Capacitive Tuning IC
PIN DESCRIPTION AND CONFIGURATION
Table 1 - Pin Description SON8 Package (1.5mm x 1.0mm)
Name
Type
Function
1
X1
Output
Capacitance
2
NC
n/a
not connected
3
VSS
Power
Negative Supply (GND)
4
VDD
Power
Positive Supply
5
DA
Input
Programming Data Input
6
CLK
Input
Programming Clock Input
7
NC
n/a
not connected
8
PV
Input
Programming Voltage
X1
1
NC
2
VSS
3
VDD
4
Y <date code>
Pin
8
PV
7
NC
6
CLK
5
DA
Figure 1 - Pin Configuration SON8
Table 2 - Pin Description TSOT6 Package
Name
Type
Function
1
X1
Output
Capacitance
2
VSS
Power
Negative Supply (GND)
3
4
5
6
PV
CLK
DA
VDD
Input
Input
Input
Power
Programming Voltage
Programming Clock Input
Programming Data Input
Positive Supply
X1 1
Y1 <date code>
Pin
VSS 2
PV 3
6 VDD
5 DA
4 CLK
Figure 2 - Pin Configuration TSOT6
Table 3 - Pin Description 6MLP Package (2.0mm x 2.0mm)
Name
Type
Function
1
X1
Output
Capacitance
2
VSS
Power
Negative Supply (GND)
3
4
5
6
VDD
DA
CLK
PV
Power
Input
Input
Input
Positive Supply
Programming Data Input
Programming Clock Input
Programming Voltage
X1
1
VSS
2
VDD
3
YG1
<date code>
Pin
6
PV
5
CLK
4
DA
Figure 3 - Pin Configuration 6MLP
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May 2012, Rev 1.2
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AZT71
Programmable Capacitive Tuning IC
ENGINEERING NOTES
CAPACITOR STRUCTURE
The AZT71 capacitance value is composed of four parallel capacitors banks, CF is a fixed capacitor value of 6.6pF and
Chi, Cmid & Clo are variable capacitors of differing ranges and resolutions as seen in Table 4. Capacitors composing Chi,
Cmid and Clo are set with a binary control word through an 11-bit shift register described in PROGRAMMING THE AZT71.
The values of each Chi, Cmid and Clo stepping are detailed in the complete Nominal Capacitance Binary Mapping
spreadsheet.
CTotal = CF + Chi + Cmid + Clo
Table 4 - AZT71 Capacitor Structure
Internal
Capacitor
Min Value
(pF)
Max Value
(pF)
Step Size
(pF)
CF
Chi
Cmid
Clo
6.6
0
0
0
6.6
19.2
9.8
1.953
n/a
6.4
1.4
0.063
Total
6.6
37.553
PROGRAMMING THE AZT71
CONTROL WORD
The capacitance in the AZT71 is controlled by an 11-bit shift register with the data input bit definitions shown in Table 5.
The control word data is inputted serially on the rising edge of the CLK signal with bit0 first and bit10 last.
Table 5 - AZT71 Control Word Definition
bit10
bit9
bit8
Chi
MSB
bit7
11-bit Control Word
bit6
bit5
bit4
Cmid
LSB
MSB
---
bit3
bit2
bit1
---
LSB
Clo
LSB
MSB
---
---
bit0
Not Used
The control word mapping is a binary word for each of Chi, Cmid and Clo where higher number bits are more significant.
Figure 4 shows the capacitance value mapping for the AZT71. The detailed Nominal Capacitance Binary Mapping can be
located on the AZM website.
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Arizona Microtek, Inc.
AZT71
Programmable Capacitive Tuning IC
Figure 4 – AZT71 Capacitance Value Mapping
AZT71 FUNCTIONAL MODES
The AZT71 is designed to be used in 2 functional modes, Programming and Operational.
In the Programming mode, the AZT71 is used by the manufacturer to set the capacitance value to control the desired
center frequency of the oscillator. The programming mode uses either the shift registers or EEPROM (detailed later) and
gives the manufacturer access to pins DA, CLK, and PV which allow the AZT71 to be programmed with an
accompanying programming board (Figure 5). Arizona Microtek can provide this board (AZPB70) along with software
that works through all the programming steps/functions described in the next sections.
In the Operational mode, the EEPROM internal to the AZT71 has already been programmed with the desired factory
settings. Pins DA, CLK, and PV are to be disconnected, thereby allowing the AZT71’s internal pull-downs to place the
pins at ground potential. In the operational mode, only 3 pins are necessary for hookup (Figure 6).
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AZT71
Programmable Capacitive Tuning IC
VDD
DA
DA
AZT71
Programming
CLK
Board
(PRT70)
X1
CLK
PV
PV
VSS
OUT
RESONATOR
OSCILLATOR
Figure 5 – AZT71 in Programming Mode
VDD
NC
DA
AZT71
X1
NC
CLK
NC
PV
VSS
OUT
RESONATOR
OSCILLATOR
Figure 6 – AZT71 in Operational Mode
PROGRAMMING MODES
The AZT71 has two capacitance setting modes from which bits are set and the matching capacitors are selected.
•
Reading directly from the shift register
o This is useful for testing the capacitance and subsequent oscillator frequency. This mode is active after
the last bit is shifted in and when the CLK pin is left logic high. For the shift register, capacitors are
selected when bits are active HIGH.
•
Reading from the value contained in the EEPROM
o Prevents customer adjustment and retains factory programming and is active when the CLK pin is at logic
low or not connected. For the EEPROM, capacitors are selected when bits are active LOW.
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AZT71
Programmable Capacitive Tuning IC
PROGRAMMING FROM THE SHIFT REGISTER
To initially determine the capacitance value for the desired center frequency of the oscillator one should set the
capacitance of the AZT71 directly from the active shift register bits. To accomplish this, the CLK pin is left high after the
last control word bit has been shifted in. Figure 7 shows the control word 11001100100 has been serially entered into the
register. Note that bit0 is the 1st bit to enter and bit10 is the last. In the AZT71, bit0 does not affect the capacitance value
but still must be included in the serial bit stream. For the shift register, capacitors are selected when bits are active HIGH.
bit 0
DA
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
Register data
active when
CLK is high
bit 0
loaded 1st
CLK
t
Figure 7 - Shift register programming
WRITING DATA TO THE EEPROM
Once the desired capacitance value has been determined, the digital control word can be written or re-written into the
EEPROM. By storing the control word in the EEPROM, the customer is prevented from making adjustments from the
factory set programming data. This is accomplished within the AZT71 with internal pull-downs on the DA, PV, and CLK
pins. The detailed sequence for writing data to the EEPROM within the AZT71 is described in Table 6. Note that with
EEPROM, capacitors are selected when bits are active LOW.
Table 6 – Data writing sequence for EEPROM
Step
1
Action
Determine the desired capacitor control word with the operational power supply voltage and
desired oscillator conditions
2
Set the VDD supply voltage to +5.0V
3
If EEPROM is not already erased, erase EEPROM (see
ERASING THE EEPROM)
4
Read the current state of the EEPROM bits (see READING BACK FROM THE EEPROM)
5
Compare the desired control word to the stored EEPROM control word. Count the number of
differences so as to prevent double/redundant writing
6
One bit at a time, load the first desired control word bit (bit selection for EEPROM is active LOW)
7
Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 10)
8
Progress through all necessary control word bits by repeating steps 5 & 6 until all bits are set to the
desired control word.
9
Verify the correct EEPROM contents by reading back the individual bits
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May 2012, Rev 1.2
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AZT71
Programmable Capacitive Tuning IC
For an example of writing bits into the EEPROM, suppose the desired capacitance is 7.23pF. The control word becomes
‘00000010100’ (Figure 8). Also suppose the EEPROM bits have been erased and therefore logic high (The AZT71 is
initially shipped in this condition). Since bit0 is the first bit to be loaded, the bit sequence becomes 0-0-1-0-1-0-0-0-0-0-0.
However, as described before, selecting bits for the EEPROM are active LOW, which will invert the logical values in the
sequence to 1-1-0-1-0-1-1-1-1-1-1 (Figure 9). Note the differences between the EEPROM bits and the converted control
word. Since there are 2 differences, two write cycles are required as only 1 bit should be written at a time. Figure 10
shows the timing for bit2 while Figure 11 shows the timing for bit4.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
Figure 8 – Desired control word
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
DA
difference
bit 0
bit 1
bit 2
difference
bit 3
bit 4
EEPROM
Figure 9 – Converted control word and differences from known EEPROM states
bit 0
DA
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 0
loaded 1st
bit 7
bit 8
bit 9
bit 10
bit 10
loaded last
CLK
10ms
min
≥5.6V,
≤6.1V
4µs
min
PV
t
Figure 10 – First programming cycle to program bit2 into the EEPROM
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bit 0
DA
AZT71
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
Programmable Capacitive Tuning IC
bit 7
bit 8
bit 9
bit 10
bit 10
loaded last
bit 0
loaded 1st
CLK
10ms
min
≥5.6V,
≤6.1V
4µs
min
PV
t
Figure 11 – Second programming cycle to program bit4 into the EEPROM
READING BACK FROM THE EEPROM
During programming, the PV pin is used to program the necessary control bits into the EEPROM. However, it is also used
to read the bits currently programmed into the EEPROM. When the PV pin is not used during programming, the AZT71
provides a weak pull-up and pull-down on the pin. This allows the EEPROM data to be shifted out to the PV pin and read
after the CLK sequence is complete and when the DA & CLK pins are high (Figure 12). Each EEPROM bit is selected by
setting the DA signal low (EEPROM selection is active low) during the CLK sequence. With an external 68kΩ resistor
pull-up to VDD on the PV pin, a low EEPROM bit produces ≤ 0.4V level while a high EEPROM bit produces a ≥ 0.6*VDD
level.
bit 0
DA
bit 1
bit0
loaded 1st
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit5
selected
bit 10
bit10
loaded last
CLK
≥ 0.6*VDD
PV
With an external 68kΩ resistor pull-up to VDD
indeterminate
≤ 0.4V
Resulting voltage if
bit5 was high in
EEPROM
Resulting voltage if
bit5 was low in
EEPROM
t
Figure 12 – Timing diagram to read bits from EEPROM
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AZT71
Programmable Capacitive Tuning IC
ERASING THE EEPROM
The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After
the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains
high.
Table 7 – Erase sequence for EEPROM
Step
Action
1
Set the VDD supply voltage to +5.0V
2
Load the programming word bits all high.
3
Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 13)
4
Verify the correct EEPROM contents by reading back the individual bits
bit 0
DA
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit0
loaded 1st
bit 10
bit10
loaded last
CLK
EEPROM has
been erased
(no capacitors
selected)
10ms
min
≥5.6V,
≤6.1V
4µs
min
PV
t
Figure 13 – Programming Sequence for erasing the EEPROM
PROGRAMMING VOLTAGE LIMIT CIRCUIT
Some existing programming circuits use a current source connected to a 6.5 – 8.0 V supply. That circuit produces an
excessive voltage on the PV pin, which can damage the AZT71. A simple modification eliminates the issue and maintains
full programming compatibility with existing programming methods. A 5.6 V, ½ watt Zener, 1N5232B or equivalent,
placed between the PV pin and ground will limit the voltage while still allowing the programming circuit to generate the
current required for programming fuse link type parts.
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AZT71
Programmable Capacitive Tuning IC
PERFORMANCE DATA
Table 8 – Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which device life may be impaired.
1
Symbol
Characteristic
Rating
Unit
VDD
Power Supply
0 to +6.5
V
VI1
Input Voltage
-0.5 to VDD + 0.5
V
TA
Operating Temperature Range
-40 to +85
°C
TSTG
Storage Temperature Range
-65 to +150
°C
ESDHBM
Human Body Model
TBD
V
ESDMM
Machine Model
TBD
V
ESDCDM
Charged Device Model
TBD
V
PV Pin can exceed VDD by 1.2V during the programming interval
Table 9 – DC Characteristics
DC Characteristics (VDD = 2.375V to 3.6V unless otherwise specified, TA = -40 to 85 °C)
Symbol
Characteristic
CPV
Nominal capacitance variation across
process
CVV
Capacitance variation across output
voltage
CTV
Capacitance variation across
temperature
Conditions
Min
Typ
-15
Voltage variation at X1 pin, 100MHz
100MHz - Zero Code
100MHz - Mid Code
Max
Unit
+15
%
±150
ppm/V
325
1
40
100MHz - Full Scale
ppm/°C
130
VIH
Input HIGH Voltage
DA, CLK
0.8 * VDD
V
VIL
Input LOW Voltage
DA, CLK
0.2 * VDD
V
RPD,D
Pull-down Resistor
DA
75k
Ω
RPD,CLK
Pull-down Resistor
CLK
75k
Ω
RPD,PV
Pull-down Resistor
PV
170k
Ω
VOH
Output High Voltage
0.6 * VDD
V
VOL
Output Low Voltage
PV Pin when reading EEPROM bits
68kΩ external pull-up resistor to VDD
0.4
V
VPP
Programming Voltage (VDD=5.0V)
PV pin when programming EEPROM
IDD
Power Supply Current
Normal Operation
IDDPROG
Power Supply Current
Programming Mode
tMEM
EEPROM Data Retention
20
yrs
Tprog
Programming Temperature
25
°C
Cyprog
Programming Cycle
1
5.6
10
6.0
6.1
V
7.0
50
µA
20
µA
k
Bit4, Bit7 High
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AZT71
Programmable Capacitive Tuning IC
Table 10 – AC Characteristics
AC Characteristics (VDD = 2.375V to 3.6V unless otherwise specified, TA = -40 to 85 °C)
Symbol
CF
CLK
Characteristic
Fixed Capacitance
Step Size
Max Value
Step Size
Max Value
Step Size
Max Value
Max CLK rate
50% duty cycle
5
Unit
pF
pF
pF
pF
pF
pF
pF
MHz
Tprog
Programming Time (VDD=5.0V, PV=6.0V)
per bit programmed
10
ms
Chi
Cmid
Clo
Q
Conditions
Q Value
Typ
6.6
6.4
19.2
1.4
9.8
0.063
1.953
20MHz - Full Scale
150
300
20MHz - Mid Scale
100
200
80MHz - Full Scale
40
40
25
25
80
80
50
50
80MHz - Mid Scale
155MHz - Full Scale
155MHz - Mid Scale
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Max
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May 2012, Rev 1.2
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AZT71
Programmable Capacitive Tuning IC
PACKAGE DIAGRAM
SON8 (1.5x1.0x0.4mm)
Green/RoHS compliant/Pb-Free
MSL=1
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AZT71
Programmable Capacitive Tuning IC
PACKAGE DIAGRAM
TSOT6
Green/RoHS compliant/Pb-Free
MSL=1
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AZT71
Programmable Capacitive Tuning IC
PACKAGE DIAGRAM
MLP6 (2.0mm x 2.0mm)
Green/RoHS compliant/Pb-Free
MSL=1
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of
any product or circuit and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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