SEMICONDUCTOR TECHNICAL DATA The MC10H145 is a 16 x 4 bit register file. The active-low chip select allows easy expansion. The operating mode of the register file is controlled by the WE input. When WE is “low” the device is in the write mode, the outputs are “low” and the data present at Dn input is stored at the selected address, when WE is “high,” the device is in the read mode — the data state at the selected location is present at the Qn outputs. L SUFFIX CERAMIC PACKAGE CASE 620–10 • Address Access Time, 4.5 ns Typical • Power Dissipation, 700 mW Typical • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K-Compatible P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 MAXIMUM RATINGS Characteristic Symbol Rating Unit VEE VI –8.0 to 0 Vdc 0 to VEE Vdc 50 100 mA Power Supply (VCC = 0) Input Voltage (VCC = 0) Output Current — Continuous — Surge Iout Operating Temperature Range TA Tstg Storage Temperature Range — Plastic — Ceramic TRUTH TABLE MODE °C –55 to +150 –55 to +165 ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note) 0° 25° 75° Characteristic Symbol Min Max Min Max Min Max Power Supply Current IE — 160 — 163 — 165 mA IinH IinL — 375 — 220 — 220 µA 0.5 — 0.5 — 0.3 — µA –0.735 Vdc Input Current High Input Current Low High Output Voltage Low Output Voltage High Input Voltage Low Input Voltage Unit VOH VOL –1.02 –0.84 –0.98 –0.81 –0.92 –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc VIH VIL –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc OUTPUT WE Dn Qn Write “0” L L L L Write “1” L L Read L H X Q Disabled H H X X L °C 0 to +75 INPUT CS L Q-State of Addressed Cell DIP PIN ASSIGNMENT NOTE: Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Q1 1 16 VCC Q0 2 15 Q2 CS 3 14 Q3 D1 4 13 WE D0 5 12 D3 A3 6 11 D2 A2 7 10 A0 VEE 8 9 A1 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). 3/93 Motorola, Inc. 1996 2–233 REV 5 MC10H145 AC PARAMETERS MC10H145 TA = 0 to +75°C, VEE = –5.2 Vdc ±5% Characteristics Symbol Read Mode Chip Select Access Time Chip Select Recovery Time Address Access Time Write Mode Write Pulse Width Data Setup Time Prior to Write Data Hold Time After Write Address Setup Time Prior to Write Address Hold Time After Write Chip Select Setup Time Prior to Write Chip Select Hold Time After Write Write Disable Time Write Recovery Time Chip Enable Strobe Mode Data Setup Prior to Chip Select Write Enable Setup Prior to Chip Select Address Setup Prior to Chip Select Data Hold Time After Chip Select Write Enable Hold Time After Chip Select Address Hold Time After Chip Select Chip Select Minimum Pulse Width Rise and Fall Time Address to Output CS to Output Capacitance Input Capacitance Output Capacitance Min Max tACS tRCS tAA 0 0 0 4.0 4.0 6.0 tW tWSD tWHD tWSA tWHA tWSCS tWHCS tWS tWR 6.0 0 1.5 3.5 1.5 0 1.5 1.0 1.0 — — — — — — — 4.0 4.0 tCSD tCSW tCSA tCHD tCHW tCHA tCS tr, tf 0 0 0 1.0 0 2.0 4.0 — — — — — — — 0.6 0.6 2.5 2.5 — — 6.0 8.0 Cin Cout Unit Conditions ns Measured from 50% of input to 50% of output. See Note 2. ns tWSA = 3.5 ns Measured at 50% of input to 50% of output. tW = 6.0 ns. ns Guaranteed but not tested on standard product. See Figure 1. ns Measured between 20% and 80% points. pF Measured with a pulse technique. p NOTES: 1. Test circuit characteristics: RT = 50 Ω, MC10H145. CL 5.0 pF (including jig and Stray Capacitance). Delay should be derated 30 ps/pF for capacitive loads up to 50 pF. 2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory. 3. For proper use of MECL in a system environment, consult MECL System Design Handbook. FIGURE 1 — CHIP ENABLE STROBE MODE A TCHA TCSD DIN TCHD CS MOTOROLA TCHW TCSW WE TCSA TCS 2–234 MECL Data DL122 — Rev 6 MC10H145 BLOCK DIAGRAM Q1 Q0 9 A3 15 CS 2 1 DATA OUT BUFFER DATA OUT BUFFER DATA OUT BUFFER 14 SENSE SENSE SENSE SENSE 7 16 X 4 MEMORY CELL ARRAY 6 WRITE AND DATA IN BUFFER 4 5 D0 MECL Data DL122 — Rev 6 3 CHIP SELECT BUFFER 10 A1 A2 Q3 DATA OUT BUFFER Address Buffer/ 1/16 Decoder A0 Q2 D1 2–235 13 11 D2 WE 12 D3 MOTOROLA MC10H145 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 V 0.010 (0.250) G1 X S T L–M N S S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S Z C H –T– SEATING PLANE F VIEW S G1 0.010 (0.250) S T L–M S 0.007 (0.180) M T L–M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA N K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L–M 2–236 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– MECL Data DL122 — Rev 6 MC10H145 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MECL Data DL122 — Rev 6 2–237 *MC10H145/D* MC10H145/D MOTOROLA