P4C422 HIGH SPEED 256 X 4 STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35 ns (Commercial) – 15/20/25/35 ns (Military) CMOS for Low Power – 495 mW Max. – 10/12/15/20/25 (Commercial) – 495 mW Max. – 15/20/25/35 (Military) Fully TTL Compatible Inputs and Outputs Single 5V±10% Power Supply Separate I/O Resistant to single event upset and latchup resulting from advanced process and design improvements. Standard Pinout (JEDEC Approved) – 22-Pin 400 mil DIP – 24-Pin 300 mil SOIC – 24-Pin Square LCC – 24-Pin CERPACK DESCRIPTION The P4C422 is a 1,024-bit high-speed (10ns) Static RAM with a 256 x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS1) and active HIGH chip select two (CS2) as well as 3-state outputs. Functional Block Diagram In addition to high performance and high density, the device features latch-up protection, single event and upset protection. The P4C422 is offered in several packages: 22-pin 400 mil DIP (plastic and ceramic), 24-pin 300 mil SOIC, 24-pin square LCC and 24-pin CERPACK. Devices are offered in both commercial and military temperature ranges. Pin ConfigurationS SOIC (S4) CERPACK (F3) SIMILAR DIP (P3-1, C3-1, D3-1) Document # SRAM101 REV B Revised July 2009 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM Maximum Ratings(1) Sym RECOMMENDED OPERATING CONDITIONS Parameter Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C Sym Parameter TSTG Storage Temperature -65 to +150 °C CIN Input Capacitance IOUT DC Output Current 50 mA COUT Output Capacitance Commercial Military CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Conditions Typ Unit VIN=0V 5 pF VOUT=0V 7 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) P4C422 Sym Parameter Test Conditions VOH Output High Voltage IOH = -5.2 mA, VCC=Min 2.4 VOL Output Low Voltage IOL = +8 mA, VCC=Min VIH Input High Voltage VIL Input Low Voltage VCL Input Clamp Diode Voltage IIN= -10 mA -1.5 IIX Input Load Current GND ≤ VIN ≤ VCC -10 10 µA IOZ Output Current (High Z) VOL ≤ VOUT ≤ VOH, Output Disabled -10 10 µA IOS Output Short Circuit Current(3) VCC=Max, VOUT=GND 90 mA Min Max 2.4 Unit V 0.4 2.1 V V 0.8 V V POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym ICC Parameter Dynamic Operating Current Temperature Range -12 -15 -20 -25 -35 Unit Commercial 90 90 90 90 65 65 mA Military N/A N/A 90 90 90 90 mA Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4.This parameter is sampled and not 100% tested. Document # SRAM101 REV B -10 5.Transition time is ≤ 3ns for 10,12, and 15 ns products and ≤ 5ns for 20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input and output levels of 1.5V. The output loading is equivalent to the specified IOL/IOH with a load capacitance of 15 pF (10,12) or 30 pF (15, 20, 25, 35) as in Fig.1a and 1b respectively. 6.Transition time is ≤ 3ns for 10, 12, and 15ns products and ≤ 5ns for 20, 25, and 35ns products, see Fig 1d. Transition is measured at steady state HIGH level -500mV or steady state LOW level +500mV on the output from a level on the input with load shown in Fig. 1c. 7.tW is measured at tWSA=min.; tWSA is measured at tW=min. Page 2 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/reading operation of the memory. When the chip select one (CS1) and the write enable (WE) are LOW and the chip select two (CS2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the "write recovery glitch." Reading is performed with chip select one (CS1) LOW, chip select two (CS2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select one (CS1) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE CS2 CS1 WE OE Output Notes: Standby L X X X High Z Standby X H X X High Z DOUT Disabled H L X H High Z Read H L H L DOUT Write H L L X High Z H = HIGH L = LOW X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state for the P4C422. Mode AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10% except as noted, All Temperature Ranges)(2) Sym Parameter tRC Read Cycle Time (5) tACS Chip Select Time (5) tZRCS Chip Select to High-Z (6) tAOS Output Enable Time tZROS tAA -10* Min -12 Max 12 Min -15 Max 12 Min -20 Max 15 Min -25 Max 20 Min -35 Max 25 Min Max 35 Unit ns 7.5 8 8 12 15 25 ns 8 10 12 15 20 30 ns 7.5 8 8 12 15 25 ns Output Enable to High-Z (6) 8 10 12 15 20 30 ns Address Access Time (5) 10 12 15 20 25 35 ns VCC = 5V ± 5% TIMING WAVEFORM OF READ CYCLE Document # SRAM101 REV B Page 3 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -10* Sym Parameter Min tWC Write Cycle Time(5) tZWS Write Enable to High-Z tWR Write Recovery Time tW Write Pulse Width -12 Max 10 (6) (5,7) Min -15 Max 12 Min -20 Max 15 Min -25 Max 20 Min -35 Max 25 Min Max 35 Unit ns 8 10 12 15 20 30 ns 8 10 12 15 20 25 ns 8 9 11 13 15 20 ns tWSD Data Setup Time Prior to Write(5) 0 0 0 2 5 5 ns tWHD Data Hold Time 2 2 2 5 5 5 ns tWSA Address Setup Time(5) 0 0 0 2 5 5 ns tWHA Address Hold Time 2 2 4 5 5 5 ns tWSCS Chip Select Setup Time(5) 0 0 0 2 5 5 ns tWHCS Chip Select Hold Time 2 2 2 5 5 5 ns (5) (5) (5) TIMING WAVEFORM OF WRITE Cycle Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state Document #SRAm101 REV B 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM AC TEST LOADS & WAVEFORMS Figure 1A Figure 1B Figure 1C Figure 1D Document # SRAM101 REV B Page 5 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM ORDERING INFORMATION Document #SRAm101 REV B Page 6 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM SIDEBRAZED DUAL IN-LINE PACKAGE C3-1 Pkg # # Pins 22 (400 Mil) Symbol Min Max A - 0.200 b 0.014 0.026 b2 0.035 0.060 C 0.008 0.015 D - 1.100 E 0.360 0.410 eA 0.400 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - CERDIP DUAL IN-LINE PACKAGE Pkg # D3-1 # Pins 22 (400 Mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.111 E 0.350 0.410 eA 0.400 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - α 0° 15° Document # SRAM101 REV B Page 7 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM CERPACK CERAMIC FLAT PACKAGE F3 Pkg # # Pins 24 Symbol Min Max A 0.060 0.090 b 0.015 0.022 c 0.004 0.009 D - 0.630 E 0.330 0.380 e 0.050 BSC k 0.008 0.015 L 0.250 0.370 Q 0.026 0.045 S - 0.085 S1 0.005 - Pkg # L4 # Pins 24 SQUARE LEADLESS CHIP CARRIER Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D/E 0.395 0.410 D1/E1 0.250 BSC D2/E2 0.125 BSC D3/E3 - 0.410 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 6 NE 6 Document # SRAM101 REV B Page 8 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM PLASTIC DUAL IN-LINE PACKAGE P3-1 Pkg # # Pins 22 (400 Mil) Symbol Min Max A - 0.210 A1 0.015 - b 0.014 0.022 b2 0.045 0.065 C 0.009 0.015 D 1.065 1.120 E1 0.330 0.390 E 0.390 0.425 e 0.100 BSC eB - 0.500 L 0.115 0.160 α 0° 15° SMALL OUTLINE IC PLASTIC PACKAGE Pkg # S4 # Pins 24 (300 Mil) Symbol Min Max A 0.093 0.104 A1 0.004 0.012 b2 0.013 0.020 C 0.009 0.012 D 0.598 0.614 e 0.050 BSC E 0.291 0.299 H 0.394 0.419 h 0.010 0.029 L 0.016 0.050 α 0° 8° Document # SRAM101 REV B Page 9 P4C422 - HIGH SPEED 256 x 4 STATIC CMOS RAM REVISIONS DOCUMENT NUMBER SRAM 101 DOCUMENT TITLE P4C422 - HIGH SPEED 256 X 4 STATIC CMOS RAM REV ISSUE DATE ORIGINATOR OR 1997 DAB New Data Sheet A Oct-2005 JDB Changed logo to Pyramid B Aug-2009 JDB Corrected DC Electrical Characteristics table Document #SRAm101 REV B DESCRIPTION OF CHANGE Page 10