SEMICONDUCTOR TECHNICAL DATA The MC10129 data inputs are compatible with, and accept TTL logic levels as well as levels compatible with IBM–type buses. The clock, strobe, and reset inputs accept MECL 10,000 logic levels. The data inputs accept the bus levels, and storage elements are provided to yield temporary latch storage of the information after receiving it from the bus. The outputs can be strobed to allow accurate synchronization of signals and/or connection to MECL 10,000 level buses. When the clock is low, and the reset input is disabled, the outputs will follow the D inputs. The latches will store the data on the rising edge of the clock. The outputs are enabled when the strobe input is high. Unused D inputs must be tied to VCC or Gnd. The clock, strobe, and reset inputs each have 50 k ohm pulldown resistors to VEE. They may be left floating, if not used. The MC10129 will operate in either of two modes. The first mode is obtained by tying the hysteresis control input to VEE. In this mode, the input threshold points of the D inputs are fixed. The second mode is obtained by tying the hysteresis control input to ground. In this mode, input hysteresis is achieved as shown in the test table. This hysteresis is desirable where extra noise margin is required on the D inputs. The outer input pins are unaffected by the mode of operation used. The MC10129 is especially useful in interface applications for central processors, mini–computers, and peripheral equipment. L SUFFIX CERAMIC PACKAGE CASE 620–10 PIN ASSIGNMENT GND 1 16 GND Q3 2 15 Q1 Q2 3 14 Q0 D3 HYSTERESIS CONTROL 4 13 D1 5 12 STROBE D2 6 11 CLOCK D0 7 10 RESET VEE 8 9 VCC PD = 750 mW typ/pkg (No Load) tpd = 10 ns typ VCC Max = 7.0 Vdc LOGIC DIAGRAM D0 7 D C D1 13 HYSTERESIS CONTROL CLOCK RESET STROBE R 3 Q2 R TRUTH TABLE D C 5 11 10 12 15 Q1 D C D3 4 R D C D2 6 14 Q0 2 Q3 R VCC = PIN 9 GND = PIN 1 AND 16 VEE = PIN 8 D C STROBE RESET Qn + 1 X X L X H X H L H L L X H H H X H X L X L L L Qn H 9/96 Motorola, Inc. 1996 3–1 REV 6 MC10129 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Pin Under Test Symbol Negative Power Supply Drain Current –30°C Min +25°C Max Min Typ +85°C Max Min Max Unit IE 8 8 167 189 152 172 167 189 mAdc Positive Power Supply Drain Current ICC 9 8.0 8.0 8.0 mAdc Input Current IinH 4 6 7 10 11 12 13 150 150 150 720 390 390 150 95 95 95 450 245 245 95 95 95 95 450 245 245 95 µAdc ICBO (1.) 4 6 7 13 1.5 1.5 1.5 –1.0 –1.0 –1.0 1.0 1.0 1.0 µAdc IinL 10 11 12 0.5 0.5 0.5 –1.0 0.5 0.5 0.5 µAdc 0.3 0.3 0.3 Output Voltage Logic 1 VOH 2 3 2 3 –1.060 –1.060 –1.060 –1.060 –0.890 –0.890 –0.890 –0.890 –0.960 –0.960 –0.960 –0.960 –0.810 –0.810 –0.810 –0.810 –0.890 –0.890 –0.890 –0.890 –0.700 –0.700 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 2 3 2 3 –1.890 –1.890 –1.890 –1.890 –1.675 –1.675 –1.675 –1.675 –1.850 –1.850 –1.850 –1.850 –1.650 –1.650 –1.650 –1.650 –1.825 –1.825 –1.825 –1.825 –1.615 –1.615 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 (2.) 2 2 2 2 (3.) 2 (4.) Threshold Voltage Logic 0 VOLA 2 2 2 2 2 2 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –0.910 –0.910 –0.910 –0.910 –0.910 –0.910 –1.655 –1.655 –1.655 –1.655 –1.655 –1.655 (2.) (2.) (3.) (4.) –1.630 –1.630 –1.630 –1.630 –1.630 –1.630 Vdc –1.595 –1.595 –1.595 –1.595 –1.595 –1.595 Switching Times Propagation Delay Vdc ns Data Input t7+14+ t7–14– t11–14+ t11–14– t12+14+ t12–14– t10+14– 14 14 3.7 3.7 15 15 3.7 3.7 10 10 15 15 3.7 3.7 30 40 14 14 2.7 2.7 11 11 2.7 2.7 5.0 5.0 9.0 9.0 2.7 2.7 11 11 14 14 1.6 1.6 8.0 8.0 1.6 1.6 4.0 4.0 7.0 7.0 1.6 1.6 8.0 8.0 14 2.0 8.0 2.0 5.0 6.5 2.0 8.0 t7+14+ t7–14– tsetup 14 14 6.6 3.7 30 17 6.7 3.7 18 10 25 15 6.6 3.7 30 40 14 30 2.7 15 30 14 0 –2.0 15 –2.0 Rise Time thold t+ 14 1.5 5.0 1.5 2.0 4.3 1.5 5.0 Fall Time t– 14 1.5 5.0 1.5 2.0 4.3 1.5 5.0 Clock Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time 1. Pin 5 to VEE, VIL to Data input one at a time. 2. Output latched to logic high state prior to test. VIHA′, VILA′ are standard logic 1 and logic 0 MTTL threshold voltages. VIHA′′, VILA′′, VIHA′′′ and VILA′′′ are logic 1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3–2. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level given. 5. Operation and limits shown also apply for VCC = +6.0V. VIHA′′ VIHA′′′ Hysteresis Mode Threshold Voltage Logic 1 Vout Logic 0 VILA′′ VILA′′′ Vin Figure 1. Hysteresis Mode Threshold Voltage MOTOROLA 3–2 MECL Data DL122 — Rev 6 MC10129 ELECTRICAL CHARACTERISTICS TEST VOLTAGE VALUES (Volts) MECL 10,000 INPUT LEVELS @ Test Temperature VIHmax VILmin VIHAmin VILAmax VIH VIL VIHA′ VILA′ –30°C –0.890 –1.890 –1.155 –1.500 3.000 0.400 2.000 0.800 +25°C –0.810 –1.850 –1.105 –1.475 3.000 0.400 2.000 0.800 +85°C –0.700 –1.825 –1.035 –1.440 3.000 0.400 2.000 0.800 VIHA′ VILA′ VIHmax VILmin 11 11 12 12 Characteristic Symbol IE 8 8 Positive Power Supply Drain Current ICC 9 Input Current IinH 4 6 7 10 11 12 13 Logic 1 Output Voltage Logic 0 Threshold Voltage Logic 1 Threshold Voltage Logic 0 Clock Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time VIL 10 11 12 VOH 2 3 2 3 12 12 12 12 10,11 10,11 10,11 10,11 VOL 2 3 2 3 12 12 12 12 10,11 10,11 10,11 10,11 2 (2.) 2 2 2 2 (3.) 2 (4.) (2.) (3.) (4.) 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 10 11 12 1,16 1,16 1,16 4 6 4 6 11,12 10 10,11 1,16 1,16 1,5,16 1,5,16 4 6 4 6 12 11 11,12 1,16 1,16 1,5,16 1,5,16 4 4 4 1,16 1,16 1,16 1,16 1,5,16 1,5,16 4 10,11 10,11 10,11 10 10,11 (2.) 1,16 4 6 7 13 10,12 12 12 12 Gnd 1,5,16 1,16 13 IinL 2 2 2 2 2 2 VIH 10,11 11 12 4 6 7 13 VOLA VILAmax 4 6 7 ICBO (1.) VOHA VIHAmin 4,6,7,13 Switching Times Propagation Delay Data Input TEST VOLTAGE APPLIED TO PINS LISTED BELOW Pin Under Test Negative Power Supply Drain Current Output Voltage TTL INPUT LEVELS (6.) 12 10,12 12 12 12 10,11 10,11 10,11 11 +1.11V +0.31V Pulse In Pulse Out 4 4 4 4 Figure +2.0V t7+14+ t7–14– t11–14+ t11–14– t12+14+ t12–14– t10+14– t7+14+ t7–14– tsetup thold t+ 14 14 12 12 10,11 10,11 7 7 14 14 Figure 3 Figure 3 1,16 1,16 14 14 12 12 10 10 7,11 7,11 14 14 Figure 6 Figure 6 1,16 1,16 10,11 10,11 12 12 14 14 7 7 Figure 4 Figure 4 1,16 1,16 7 Figure 5 Figure 3 Figure 3 1,16 1,5,16 1,5,16 t– 14 14 +5.0V +2.40V 1,16 1,16 1,16 1,16 1,5,16 1,5,16 14 14 14 12 12 12 10,11 10,11 10,11 7 7 14 14 14 7 14 14 14 12 12 12 10 10 10,11 7,11 7,11 7 14 14 14 Figure 7 Figure 7 Figure 3 1,16 1,16 1,16 14 12 10,11 7 14 Figure 3 1,16 1. Pin 5 to VEE, VIL to Data input one at a time. 2. Output latched to logic high state prior to test. VIHA′, VILA′ are standard logic 1 and logic 0 MTTL threshold voltages. VIHA′′, VILA′′, VIHA′′′ and VILA′′′ are logic 1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3–2. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level given. 5. Operation and limits shown also apply for VCC = +6.0V. 6. When testing, choose either TTL or IBM input levels. MECL Data DL122 — Rev 6 3–3 MOTOROLA MC10129 ELECTRICAL CHARACTERISTICS TEST VOLTAGE VALUES (Volts) IBM INPUT LEVELS (6.) @ Test Temperature VIH VIL –30°C 3.11 0.150 +25°C 3.11 0.150 +85°C 3.11 0.150 Pin Under Test Characteristic Symbol Negative Power Supply Drain Current IE 8 8 Positive Power Supply Drain Current ICC 9 Input Current IinH 4 6 7 10 11 12 13 Output Voltage Logic 1 Output Voltage Logic 0 Threshold Voltage Logic 1 Threshold Voltage Logic 0 4 6 7 13 IinL 10 11 12 VOH 2 3 2 3 VOL 2 3 2 3 VOLA Clock Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time 1.700 0.70 VIHA′′ VILA′′ VIHA′′′ VILA′′′ VCC (5.) VEE 2.90 2.00 2.20 1.30 +5.0 –5.2 2.60 1.70 1.90 1.00 +5.0 –5.2 2.30 1.40 1.60 0.70 +5.0 –5.2 VCC (5.) VEE Gnd 9 9 8 5,8 1,5,16 1,16 9 9 5,8 5,8 1,16 1,16 9 9 9 9 9 9 9 8 8 8 8 8 8 8 1,16 1,16 1,16 1,16 1,16 1,16 1,16 9 9 9 9 8 8 8 8 1,16 1,16 1,16 1,16 9 9 9 8 8 8 1,16 1,16 1,16 9 9 9 9 5,8 5,8 8 8 1,16 1,16 1,5,16 1,5,16 9 9 9 9 5,8 5,8 8 8 1,16 1,16 1,5,16 1,5,16 9 9 9 9 9 9 5,8 5,8 5,8 5,8 8 8 1,16 1,16 1,16 1,16 1,5,16 1,5,16 9 9 9 9 9 9 5,8 5,8 5,8 5,8 8 8 1,16 1,16 1,16 1,16 1,5,16 1,5,16 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIH VIL VIHA′ VILA′ VIHA′′ VILA′′ VIHA′′′ VILA′′′ 4 6 7 13 4 6 7 13 4 6 4 6 4 6 4 6 2 (2.) 2 2 2 2 (3.) 2 (4.) 4 4 4 2 2 2 2 2 2 4 4 4 (2.) (2.) 4 4 4 4 4 (3.) (4.) Switching Times Propagation Delay Data Input VILA′ 4,6, 7,13 ICBO (1.) VOHA VIHA′ HYSTERESIS MODE 4 Figure +7.0V –3.2V +2.0V t7+14+ t7–14– t11–14+ t11–14– t12+14+ t12–14– t10+14– t7+14+ t7–14– tsetup thold t+ 14 14 +5.0V +2.40V Figure 3 Figure 3 9 9 5,8 5,8 1,16 1,16 14 14 Figure 6 Figure 6 9 9 5,8 5,8 1,16 1,16 t– 14 14 7 7 Figure 4 Figure 4 9 9 5,8 5,8 1,16 1,16 14 14 14 7 Figure 5 Figure 3 Figure 3 9 9 9 5,8 8 8 1,16 1,5,16 1,5,16 14 14 14 Figure 7 Figure 7 Figure 3 9 9 9 5,8 5,8 5,8 1,16 1,16 1,16 14 Figure 3 9 5,8 1,16 1. Pin 5 to VEE, VIL to Data input one at a time. 2. Output latched to logic high state prior to test. VIHA′, VILA′ are standard logic 1 and logic 0 MTTL threshold voltages. VIHA′′, VILA′′, VIHA′′′ and VILA′′′ are logic 1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3–2. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level given. 5. Operation and limits shown also apply for VCC = +6.0V. 6. When testing, choose either TTL or IBM input levels. MOTOROLA 3–4 MECL Data DL122 — Rev 6 MC10129 Figure 2. SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C Vin 25 µF 0.1 µ F Coax Vout VCC +7.0 Vdc +5.0 Vdc 0.1 µF Coax 7 14 D D0 Q0 Input C R Pulse Generator Input Pulse t+ = t– = 5.5 ± 0.5 ns (10 to 90%) 13 15 D D1 Unused Inputs (D) must be tied to VCC or Pin 16 C Q1 R 6 50-ohm termination to ground located in each scope channel input. All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. 3 D D2 Q2 C R 4 D3 5 Clock 11 Reset 10 Strobe 12 2 D C Hysteresis Control Unused outputs connected to a 50-ohm resistor to ground. Q3 R 8 1 16 0.1 µF 25 µF –3.2 Vdc VEE + 2.0 Vdc NOTE: All power supplies and logic levels are shifted 2 volts positive. MECL Data DL122 — Rev 6 3–5 MOTOROLA MC10129 Figure 3 – DATA to OUTPUT (Clock and Reset are low, Strobe is high) Figure 4 – STROBE to OUTPUT (Data is high, Clock and Reset are low) +5.0 V +1.11 V 50% Data Strobe +2.4 V t+ +0.31 V t+ t– t7+14+ t– +1.11 V 80% 50% 20% Q 50% Q +0.31 V +1.11 V 80% 50% t12+14+ t7–14– 20% +0.31 V t12–14– Figure 6 – CLOCK to OUTPUT (Reset is low, Strobe is high) Data +5.0 V Figure 5 – RESET to OUTPUT (Data and Strobe are high) +2.4 V Clock +1.11 V +1.11 V 50% 50% 50% t– t+ Q Clock +1.11 V 80% 50% 20% +0.31 V Reset +0.31 V +0.31 V +1.11 V t11–14– 50% t11–14+ +0.31 V t– t+ Figure 7 – TSET UP AND THOLD WAVEFORMS +1.11 V 80% 50% +5.00 V 50% 20% Q 50% D +0.31 V +2.400 V thold tsetup +1.11 V 50% C +0.31 V t11–14+ Q t10+14– MOTOROLA 3–6 MECL Data DL122 — Rev 6 MC10129 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A M T B S DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S Motorola reserves the right to make changes without further notice to any products herein. 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