Four Bit Universal Shift Register

MC10141
Four Bit Universal Shift
Register
The MC10141 is a four–bit universal shift register which performs
shift left, or shift right, serial/parallel in, and serial/parallel out
operations with no external gating. Inputs S1 and S2 control the four
possible operations of the register without external gating of the clock.
The flip–flops shift information on the positive edge of the clock. The
four operations are stop shift, shift left, shift right, and parallel entry of
data. The other six inputs are all data type inputs; four for parallel
entry data, and one for shifting in from the left (DL) and one for
shifting in from the right (DR).
• PD = 425 mW typ/pkg (No Load)
• fShift = 200 MHz typ
• tr, tf = 2.0 ns typ (20%–80%)
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
LOGIC DIAGRAM
D3
S1
1 of 4
Decode
r
S2
DR
D2
Parallel Enter
D1
1
1
PLCC–20
FN SUFFIX
CASE 775
Shift Left
DL
Hold
VCC1 = PIN 1
VCC2 = PIN 16
MC10141P
AWLYYWW
D0
Shift Right
C
MC10141L
AWLYYWW
DQ
DQ
DQ
DQ
C
C
C
C
Q3
Q2
Q1
A
WL
YY
WW
Q0
TRUTH TABLE
OUTPUTS
S1
S2
OPERATING MODE
Q0n+1
Q1n+1
Q2n+1
Q3n+1
L
L
Parallel Entry
D0
D1
D2
D3
L
H
Shift Right*
Q1n
Q2n
Q3n
DR
H
L
Shift Left*
DL
Q0n
Q1n
Q2n
H
H
Stop Shift
Q0n
Q1n
Q2n
Q3n
*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
VCC1
1
16
VCC2
Q2
2
15
Q1
Q3
3
14
Q0
C
4
13
DL
DR
5
12
D0
D3
6
11
D1
S2
7
10
S1
VEE
8
9
D2
VEE = PIN 8
SELECT
10141
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Package
Shipping
MC10141L
CDIP–16
25 Units / Rail
MC10141P
PDIP–16
25 Units / Rail
MC10141FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10141/D
MC10141
SHIFT FREQUENCY TEST CIRCUIT
VCC1 = VCC2
+2.0 VDC
VIN
COAX
INPUT
PULSE GENERATOR
50-ohm termination to ground
located in each scope channel input.
VOUT
0.1 µF
25 uF
1
DL
C
16
Q0
D0
D1
TEST PROCEDURES:
1.SET D1, D2, D3 = +0.31 VDC (LOGIC L)
D0 = +1.11 VDC (LOGIC H)
—V
IH TO SET Q0 HIGH.
2.APPY CLOCK PULSE
VIL
3.MAINTAIN CLOCK LOW.
SET S1 = +0.31 VDC (LOGIC L)
S2 = +1.11 VDC (LOGIC H)
Q1
D2
D3
Q2
S1
S2
DR
Coax
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
Q3
4. TEST SHIFT FREQUENCY
8
0.1 µF
VEE = -3.2VDC
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MC10141
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
112
IinH
5
6
7
4
350
350
390
425
–30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
82
102
112
mAdc
220
220
245
265
220
220
245
265
µAdc
µAdc
IinL
12
0.5
Output Voltage
Logic 1
VOH
3
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
VOL
3
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage Logic 1
VOHA
(Note 1.)
3
3
3
3
–1.080
–1.080
–1.080
–1.080
Threshold Voltage Logic 0
VOLA
(Note 1.)
3
3
3
3
Switching Times
Load)
0.5
Min
0.3
–0.980
–0.980
–0.980
–0.980
–0.910
–0.910
–0.910
–0.910
–1.655
–1.655
–1.655
–1.655
–1.630
–1.630
–1.630
–1.630
Vdc
–1.595
–1.595
–1.595
–1.595
(50Ω
Propagation Delay
Setup TIme (tsetup)
Hold Time (thold)
ns
t4+3+
t12+4+
t10+4+
t4+12+
3
14
14
14
1.7
2.5
5.5
1.5
3.9
1.8
2.5
5.0
1.5
2.9
3.8
2.0
2.5
5.5
1.5
4.2
Rise Time
(20 to 80%)
t3+
3
1.0
3.4
1.1
2.0
3.3
1.1
3.6
Fall Time
(20 to 80%)
t3–
3
1.0
3.4
1.1
2.0
3.3
1.1
3.6
150
200
Shift Frequency
Vdc
fshift
1. These tests to be performed in sequence as shown.
150
VIH
P1
VIL
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
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3
P2
150
VIHA
VIL
P3
MHz
VILA
VIL
MC10141
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85°C
–0.700
–1.825
–1.035
–1.440
–5.2
Characteristic
Symbol
Pin
Under
Test
Power Supply Drain Current
IE
8
IinH
5
6
7
4
5
6
7
4
IinL
12
4,5,6,7,9,
10,11,13
6
Input Current
Output Voltage
Logic 1
VOH
3
Output Voltage
Logic 0
VOL
3
Threshold Voltage
Logic 1
VOHA
(Note 1.)
3
3
3
3
Threshold Voltage
Logic 0
VOLA
(Note 1.)
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
3
3
3
3
VILmin
VIHAmin
Hold Time (thold)
VEE
12
6
6
6
Note 3.
Note 3.
7
6
7
Note 4.
Note 4.
6
Switching Times (50Ω Load)
Propagation Delay
Setup TIme (tsetup)
VILAmax
P1
P2
(VCC)
Gnd
P3
8
1, 16
8
8
8
8
1, 16
1, 16
1, 16
1, 16
8
1, 16
8
4
1, 16
8
4
1, 16
8
8
8
8
4
4
4
1, 16
1, 16
1, 16
1, 16
8
8
8
8
4
4
4
1, 16
1, 16
1, 16
1, 16
4
4
–3.2 V
+2.0 V
t4+3+
t12+4+
t10+4+
t4+12+
3
14
14
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Rise Time
(20 to 80%)
t3+
3
8
1, 16
Fall Time
(20 to 80%)
t3–
3
8
1, 16
8
1, 16
Shift Frequency
fshift
1. These tests to be performed in sequence as shown.
Note 2.
VIH
P1
VIL
P2
VIHA
VIL
P3
VILA
VIL
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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MC10141
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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5
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10141
PACKAGE DIMENSIONS
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
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6
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
MC10141
Notes
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MC10141
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC10141/D