SHARC Processor ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SUMMARY The ADSP-2148x processors are available with unique audiocentric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more For complete ordering information, see Ordering Guide on Page 66 High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip ROM Up to 450 MHz operating frequency Code compatible with all other members of the SHARC family Internal Memory SIMD Core Block 0 RAM/ROM Instruction Cache 5 Stage Sequencer DAG1/2 Core Timer PEx DMD 64-BIT PEy FLAGx/IRQx/ TMREXP JTAG THERMAL DIODE PMD 64-BIT S B0D 64-BIT Block 1 RAM/ROM Block 2 RAM B2D 64-BIT B1D 64-BIT Block 3 RAM B3D 64-BIT DMD 64-BIT Core Bus Cross Bar Internal Memory I/F PMD 64-BIT EPD BUS 64-BIT IOD0 32-BIT PERIPHERAL BUS 32-BIT IOD1 32-BIT IOD0 BUS FFT FIR IIR PERIPHERAL BUS DTCP/ MTM EP SPEP BUS CORE FLAGS/ PWM3-1 PCG C-D TIMER 1-0 TWI SPI/B UART S/PDIF PCG Tx/Rx A-D DPI Routing/Pins DPI Peripherals ASRC PDAP/ SPORT IDP 7-0 3-0 7-0 DAI Routing/Pins DAI Peripherals WDT CORE PWM FLAGS 3-0 AMI SDRAM CTL External Port Pin MUX Peripherals External Port Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 TABLE OF CONTENTS Summary ............................................................... 1 Maximum Power Dissipation ................................. 21 General Description ................................................. 3 Package Information ............................................ 21 Family Core Architecture ........................................ 4 Timing Specifications ........................................... 22 Family Peripheral Architecture ................................ 7 Output Drive Currents ......................................... 55 I/O Processor Features ......................................... 10 Test Conditions .................................................. 55 System Design .................................................... 11 Capacitive Loading .............................................. 55 Development Tools ............................................. 12 Thermal Characteristics ........................................ 56 Additional Information ........................................ 13 100-LQFP_EP Lead Assignment ................................ 58 Related Signal Chains .......................................... 13 176-Lead LQFP_EP Lead Assignment ......................... 60 Pin Function Descriptions ....................................... 14 Outline Dimensions ................................................ 64 Specifications ........................................................ 18 Surface-Mount Design .......................................... 65 Operating Conditions .......................................... 18 Automotive Products .............................................. 66 Electrical Characteristics ....................................... 19 Ordering Guide ..................................................... 66 Absolute Maximum Ratings .................................. 21 ESD Sensitivity ................................................... 21 REVISION HISTORY 3/13—Revision A to Revision B Corrected outstanding document errata. Added section Static Voltage Scaling (SVS) ................... 11 Revised Development Tools ...................................... 12 Revised MS0-1 Pin Description in Pin Function Descriptions ........................................ 14 Revised Electrical Characteristics ................................ 19 Revised Total Power Dissipation ................................. 20 Added paragraph to SDRAM Interface Timing (166 MHz SDCLK) ................................................................ 32 Added footnote 3 to Table 32 in AMI Read ................... 33 Changed Max values in Table 43 in Pulse-Width Modulation Generators (PWM) ................................................. 45 Added model to Automotive Product Table (Table 63) in Automotive Products ............................................... 66 Revised Ordering Guide ........................................... 66 Added 450 MHz products and information to the following: • Tables 1 and 2 in General Description ......................3 • Operating Conditions ........................................ 18 • Electrical Characteristics ..................................... 19 • Tables 14 and 15 in Total Power Dissipation ........... 20 • Table 20 in Clock Input ...................................... 24 Rev. B | Page 2 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 GENERAL DESCRIPTION The ADSP-2148x SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2148x processors are 32-bit/40-bit floating point processors optimized for high performance audio applications with large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Table 1. Processor Benchmarks Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with Reversal) FIR Filter (per Tap)1 IIR Filter (per Biquad)1 Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] [4 × 4] × [4 × 1] Divide (y/×) Inverse Square Root Table 1 shows performance benchmarks for the ADSP-2148x processors. Table 2 shows the features of the individual product offerings. 1 Speed (at 400 MHz) 23 μs Speed (at 450 MHz) 20.44 μs 1.25 ns 5 ns 1.1 ns 4.43 ns 11.25 ns 20 ns 7.5 ns 11.25 ns 10.0 ns 17.78 ns 6.67 ns 10.0 ns Assumes two files in multichannel SIMD mode Table 2. ADSP-2148x Family Features Feature Maximum Instruction Rate RAM ROM Audio Decoders in ROM1 Pulse-Width Modulation DTCP Hardware Accelerator External Port Interface (SDRAM, AMI)2 Serial Ports Direct DMA from SPORTs to External Port (External Memory) FIR, IIR, FFT Accelerator Watchdog Timer MediaLB Interface IDP/PDAP UART DAI (SRU)/DPI (SRU2) S/PDIF Transceiver SPI TWI SRC Performance3 Thermal Diode VISA Support Package2 ADSP-21483 400 MHz 3 Mbits Yes (16-bit) ADSP-21486 400 MHz ADSP-21487 450 MHz 5 Mbits ADSP-21488 400 MHz 3 Mbits 4 Mbits Yes 4 Units (3 Units on 100-Lead Packages) Contact Analog Devices AMI Only Yes (16-bit) 8 Yes 176-Lead LQFP EPAD 100-Lead LQFP EPAD Yes Yes (176-Lead Package Only) Automotive Models Only Yes 1 Yes Yes Yes 1 –128 dB Yes Yes 176-Lead LQFP EPAD ADSP-21489 450 MHz 5 Mbits No No 176-Lead LQFP EPAD 100-Lead LQFP EPAD ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The 100-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead Assignment on page 60. 3 Some models have –140 dB performance. For more information, see Ordering Guide on page 66. 1 Rev. B | Page 3 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The diagram on Page 1 shows the two clock domains that make up the ADSP-2148x processors. The core clock domain contains the following features: • Two processing elements (PEx, PEy), each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting 2x64-bit data transfers between memory and the core at every core processor cycle • One periodic interval timer with pinout • On-chip SRAM (5 Mbit) and mask-programmable ROM (4 Mbit) • JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints which allows flexible exception handling. The block diagram of the ADSP-2148x on Page 1 also shows the peripheral clock domain (also known as the I/O processor) which contains the following features: • IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers • Peripheral and external port buses for core connection • External port with an AMI and SDRAM controller • 4 units for PWM control • 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers • Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnects, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, a 2-wire interface (TWI), one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG), pulse width modulation (PWM), and a flexible signal routing unit (DPI SRU2). As shown in the SHARC core block diagram on Page 5, the processor uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hardware, the processors can perform 2.7 GFLOPS running at 450 MHz. FAMILY CORE ARCHITECTURE The ADSP-2148x is code compatible at the assembly level with the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2148x shares architectural features with the ADSP-2126x, ADSP2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. Rev. B | SIMD Computational Engine The ADSP-2148x contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEx is always active, and PEy may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or register file access. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle and are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. Timer The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Page 4 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 S JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 16x32 DAG2 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX 64-BIT DM DATA 64 MULTIPLIER MRF 80-BIT MRB 80-BIT SHIFTER ALU RF Rx/Fx PEx 16x40-BIT DATA SWAP RF Sx/SFx PEy 16x40-BIT ASTATx ASTATy STYKx STYKy ALU SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT Figure 2. SHARC Core Block Diagram Universal Registers These registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral registers (control/status). The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-2148x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data. With the its separate program and data memory buses and onchip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. The two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Instruction Cache Flexible Instruction Set The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processor can conditionally execute a multiply, an add, and a Single-Cycle Fetch of Instruction and Four Operands Rev. B | Page 5 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 subtract in both processing elements while branching and fetching up to four 32-bit values from memory, all in a single instruction. Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions from previous SHARC processors, the ADSP-2148x supports new instructions of 16 and 32 bits. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchronous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. On-Chip Memory The ADSP-21483 and the ADSP-21488 processors contain 3 Mbits of internal RAM (Table 3) and the ADSP-21486, ADSP-21487, and ADSP-21489 processors contain 5 Mbits of internal RAM (Table 4). Each memory block supports singlecycle, independent accesses by the core processor and I/O processor. Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)1 Long Word (64 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Reserved 0x0004 8000–0x0004 8FFF Block 0 SRAM 0x0004 9000–0x0004 CFFF Reserved 0x0004 D000–0x0004 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Reserved 0x0005 8000–0x0005 8FFF Block 1 SRAM 0x0005 9000–0x0005 CFFF Reserved 0x0005 D000–0x0005 FFFF Block 2 SRAM 0x0006 0000–0x0006 1FFF Reserved 0x0006 2000– 0x0006 FFFF Block 3 SRAM 0x0007 0000–0x0007 1FFF Reserved 0x0007 2000–0x0007 FFFF 1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF Reserved Reserved 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF Block 0 SRAM Block 0 SRAM 0x0008 C000–0x0009 1554 0x0009 2000–0x0009 9FFF Reserved Reserved 0x0009 1555–0x0009 FFFF 0x0009 A000–0x0009 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF Reserved Reserved 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF Block 1 SRAM Block 1 SRAM 0x000A C000–0x000B 1554 0x000B 2000–0x000B 9FFF Reserved Reserved 0x000B 1555–0x000B FFFF 0x000B A000–0x000B FFFF Block 2 SRAM Block 2 SRAM 0x000C 0000–0x000C 2AA9 0x000C 0000–0x000C 3FFF Reserved Reserved 0x000C 2AAA–0x000D FFFF 0x000C 4000–0x000D FFFF Block 3 SRAM Block 3 SRAM 0x000E 0000–0x000E 2AA9 0x000E 0000–0x000E 3FFF Reserved Reserved 0x000E 2AAA–0x000F FFFF 0x000E 4000–0x000F FFFF Short Word (16 Bits) Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0012 0000–0x0012 3FFF Block 0 SRAM 0x0012 4000–0x0013 3FFF Reserved 0x0013 4000–0x0013 FFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0016 4000–0x0017 3FFF Reserved 0x0017 4000–0x0017 FFFF Block 2 SRAM 0x0018 0000–0x0018 7FFF Reserved 0x0018 8000–0x001B FFFF Block 3 SRAM 0x001C 0000–0x001C 7FFF Reserved 0x001C 8000–0x001F FFFF Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales representative for additional details. The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are Rev. B | most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory maps in Table 3 and Table 4 display the internal memory address space of the processors. The 48-bit space section describes what this address range looks like to an Page 6 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)1 Long Word (64 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Reserved 0x0004 8000–0x0004 8FFF Block 0 SRAM 0x0004 9000–0x0004 EFFF Reserved 0x0004 F000–0x0004 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Reserved 0x0005 8000–0x0005 8FFF Block 1 SRAM 0x0005 9000–0x0005 EFFF Reserved 0x0005 F000–0x0005 FFFF Block 2 SRAM 0x0006 0000–0x0006 3FFF Reserved 0x0006 4000– 0x0006 FFFF Block 3 SRAM 0x0007 0000–0x0007 3FFF Reserved 0x0007 4000–0x0007 FFFF 1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF Reserved Reserved 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF Block 0 SRAM Block 0 SRAM 0x0008 C000–0x0009 3FFF 0x0009 2000–0x0009 DFFF Reserved Reserved 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF Reserved Reserved 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF Block 1 SRAM Block 1 SRAM 0x000A C000–0x000B 3FFF 0x000B 2000–0x000B DFFF Reserved Reserved 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF Block 2 SRAM Block 2 SRAM 0x000C 0000–0x000C 5554 0x000C 0000–0x000C 7FFF Reserved Reserved 0x000C 5555–0x000D FFFF 0x000C 8000–0x000D FFFF Block 3 SRAM Block 3 SRAM 0x000E 0000–0x000E 5554 0x000E 0000–0x000E 7FFF Reserved Reserved 0x000E 5555–0x0000F FFFF 0x000E 8000–0x000F FFFF Short Word (16 Bits) Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0012 0000–0x0012 3FFF Block 0 SRAM 0x0012 4000–0x0013 BFFF Reserved 0x0013 C000–0x0013 FFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0016 4000–0x0017 BFFF Reserved 0x0017 C000–0x0017 FFFF Block 2 SRAM 0x0018 0000–0x0018 FFFF Reserved 0x0019 0000–0x001B FFFF Block 3 SRAM 0x001C 0000–0x001C FFFF Reserved 0x001D 0000–0x001F FFFF Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Please contact your Analog Devices sales representative for additional details. FAMILY PERIPHERAL ARCHITECTURE instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. ROM Based Security The ADSP-2148x has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features are available after the correct key is scanned. The ADSP-2148x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. External Memory The external port interface supports access to the external memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The external ports are comprised of the following modules. On-Chip Memory Bandwidth The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bits, CCLK speed) and the IOD0/1 buses (2 × 32-bit, PCLK speed). Rev. B | Page 7 of 68 | • An Asynchronous Memory Interface which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in bank 0 and 8M words of external memory in bank 1, bank 2, and bank 3. • A SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. NOTE: this feature is not available on the ADSP-21486 product. March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 • Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port. A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. Note that 32-bit wide devices are not supported on the SDRAM and AMI interfaces. Non-SDRAM external memory address space is shown in Table 5. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. Table 5. External Memory for Non-SDRAM Addresses Bank Bank 0 Bank 1 Bank 2 Bank 3 Size in Words 6M 8M 8M 8M Address Range 0x0020 0000–0x007F FFFF 0x0400 0000–0x047F FFFF 0x0800 0000–0x087F FFFF 0x0C00 0000–0x0C7F FFFF Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. SIMD Access to External Memory External Port The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The external port, available on the 176-lead LQFP, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The SDRAM controller on the processor supports SIMD access on the 64-bit EPD (external port data bus) which allows access to the complementary registers on the PEy unit in the normal word space (NW). This removes the need to explicitly access the complimentary registers when the data is in external SDRAM memory. VISA and ISA Access to External Memory The SDRAM controller on the ADSP-2148x processors supports VISA code operation which reduces the memory load since the VISA instructions are compressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the traditional ISA operation is also supported. Note that code execution is only supported from bank 0 regardless of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode. Table 7. External Bank 0 Instruction Fetch Access Type Size in Words Address Range ISA (NW) 4M 0x0020 0000–0x005F FFFF VISA (SW) 10M 0x0060 0000–0x00FF FFFF SDRAM Controller The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices at speeds up to fSDCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 4M bytes and 256M bytes of memory. SDRAM external memory address space is shown in Table 6. NOTE: this feature is not available on the ADSP-21486 model. Table 6. External Memory for SDRAM Addresses Bank Bank 0 Bank 1 Bank 2 Bank 3 Size in Words 62M 64M 64M 64M Address Range 0x0020 0000–0x03FF FFFF 0x0400 0000–0x07FF FFFF 0x0800 0000–0x0BFF FFFF 0x0C00 0000–0x0FFF FFFF Rev. B | Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. Page 8 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single-update mode or double-update mode. In single-update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double-update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. PWM signals can be mapped to the external port address lines or to the DPI pins. MediaLB The automotive models of the ADSP-2148x processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin as well as 5-pin media local bus protocols. It supports speeds up to 1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of automotive models, see Automotive Products on Page 66. Digital Applications Interface (DAI) The digital applications interface (DAI) allows the connection of various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI includes eight serial ports, four precision clock generators (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports (SPORTs) The ADSP-2148x features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with Rev. B | another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes: • Standard serial mode • Multichannel (TDM) mode • I2S mode • Packed I2S mode • Left-justified mode S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, or the precision clock generators (PCGs), and are controlled by the SRU control registers. Asynchronous Sample Rate Converter (SRC) The asynchronous sample rate converter contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I2S, left-justified sample pair, or right-justified mode. The IDP also provides a parallel data acquisition port (PDAP), which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data. Precision Clock Generators The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Page 9 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The outputs of PCG A and B can be routed through the DAI pins and the outputs of PCG C and D can be driven on to the DAI as well as the DPI pins. Digital Peripheral Interface (DPI) The ADSP-2148x SHARC processors have a digital peripheral interface that provides connections to two serial peripheral interface ports (SPI), one universal asynchronous receivertransmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two general-purpose timers. Serial Peripheral (Compatible) Interface (SPI) The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. UART Port The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O)—The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access)—The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables the generalpurpose timer. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: • 7-bit addressing • Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration • Digital filtering and timed event processing • 100 kbps and 400 kbps data rates • Low interrupt rate I/O PROCESSOR FEATURES The I/O processors provide up to 65 channels of DMA, as well as an extensive set of peripherals. DMA Controller The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-2148x’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the PDAP, or the UART. The DMA channel summary is shown in Table 8. Programs can be downloaded to the ADSP-2148x using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers. Table 8. DMA Channels Peripheral SPORTs IDP/PDAP SPI UART External Port Accelerators Memory-to-Memory MLB1 Timers The ADSP-2148x has a total of three timers: a core timer that can generate periodic software interrupts and two generalpurpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: 1 • Pulse waveform generation mode Automotive models only. • Pulse width count/capture mode • External event watchdog mode Rev. B | Page 10 of 68 | March 2013 DMA Channels 16 8 2 2 2 2 2 31 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 9. Boot Mode Selection, 176-Lead Package Delay Line DMA The processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Scatter/Gather DMA The processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from non contiguous memory blocks. FFT Accelerator The FFT accelerator implements a radix-2 complex/real input, complex output FFT with no core intervention. The FFT accelerator runs at the peripheral clock frequency. FIR Accelerator The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. BOOT_CFG2–0 000 001 010 011 1xx Booting Mode SPI Slave Boot SPI Master Boot AMI User Boot (for 8-bit Flash Boot) No boot (processor executes from internal ROM after reset) Reserved Table 10. Boot Mode Selection, 100-Lead Package BOOT_CFG1–0 00 01 10 11 Booting Mode SPI Slave Boot SPI Master Boot Reserved No boot (processor executes from internal ROM after reset) The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data, and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency. The “Running Reset” feature allows a user to perform a reset of the processor core and peripherals, but without resetting the PLL and SDRAM controller, or performing a boot. The functionality of the RESETOUT/RUNRSTIN pin has now been extended to also act as the input for initiating a Running Reset. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. Watchdog Timer Power Supplies The watchdog timer is used to supervise the stability of the system software. When used in this way, software reloads the watchdog timer in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control. The processors have separate power supply connections for the internal (VDD_INT) and external (VDD_EXT) power supplies. The internal supply must meet the VDD_INT specifications. The external supply must meet the VDD_EXT specification. All external supply pins must be connected to the same power supply. The 32-bit watchdog timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by forcing the processor to a known state through generation of a system reset, if the timer expires before being reloaded by software. Software initializes the count value of the timer, and then enables the timer. The watchdog timer resets both the core and the internal peripherals. Note that this feature is available on the 176-lead package only. To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDD_INT and GND. IIR Accelerator SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the ADSP-2148x boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an SPI slave. Booting is determined by the boot configuration (BOOT_CFG2–0) pins in Table 9 for the 176-lead package and Table 10 for the 100-lead package. Rev. B | Static Voltage Scaling (SVS) Some models of the ADSP-2148x feature Static Voltage Scaling (SVS) on the VDD_INT power supply. (See the Ordering Guide on Page 66 for model details.) This voltage specification technique can provide significant performance benefits including 450 MHz core frequency operation without a significant increase in power. SVS optimizes the required VDD_INT voltage for each individual device to enable enhanced operating frequency up to 450 MHz. The optimized SVS voltage results in a reduction of maximum IDD_INT which enables 450 MHz operation at the same or lower maximum power than 400 MHz operation at a fixed voltage supply. Implementation of SVS requires a specific voltage regulator circuit design and initialization code. Refer to the Engineer-to-Engineer Note “Static Voltage Scaling for ADSP-2148x Processors” (EE-357) for further information. The EE-Note details the requirements and process to implement a SVS power supply system to enable operation up to 450 MHz. This applies only to specific products within the ADSP-2148x family which are capable of supporting 450 MHz operation. Page 11 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Details on power consumption and Static and Dynamic current consumption can be found at Total Power Dissipation on Page 20. Also see Operating Conditions on Page 18 for more information. The following are SVS features. • SVS is applicable only to 450 MHz models (not applicable to 400 MHz or lower frequency models). • Each individual SVS device includes a register (SVS_DAT) containing the unique SVS voltage set at the factory, known as SVSNOM. The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. EZ-KIT Lite Evaluation Board • The SVSNOM value is the intended set voltage for the VDD_INT voltage regulator. • No dedicated pins are required for SVS. The TWI serial bus is used to communicate SVSNOM to the voltage regulator. • Analog Devices recommends a specific voltage regulator design and initialization code sequence that optimizes the power-up sequence. The Engineer-to-Engineer Note “Static Voltage Scaling for ADSP-2148x Processors” (EE-357) contains the details of the regulator design and the initialization requirements. • Any differences from the Analog Devices recommended programmable regulator design must be reviewed by Analog Devices to ensure that it meets the voltage accuracy and range requirements. Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2148x processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide. DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products, emulators, and a wide variety of software add-ins. Integrated Development Environments (IDEs) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. The newest IDE, CrossCore Embedded Studio, is based on the EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, Rev. B | algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. Board Support Packages for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page. Page 12 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages: The Circuits from the LabTM site (www.analog.com/circuits) provides: • www.analog.com/ucos3 • www.analog.com/ucfs • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • www.analog.com/ucusbd • www.analog.com/lwip • Drill down links for components in each chain to selection guides and application information Algorithmic Modules To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. • Reference designs applying best practice design techniques Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer Note “Analog Devices JTAG Emulation Technical Reference” (EE-68) on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2148x architecture and functionality. For detailed information on the ADSP-2148x family core architecture and instruction set, refer to the SHARC Processor Programming Reference. RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the Glossary of EE Terms on the Analog Devices website. Rev. B | Page 13 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 PIN FUNCTION DESCRIPTIONS Table 11. Pin Descriptions Name ADDR23–0 Type I/O/T (ipu) State During/ After Reset High-Z/ driven low (boot) DATA15–0 I/O/T (ipu) High-Z AMI_ACK I (ipu) MS0–1 O/T (ipu) High-Z AMI_RD O/T (ipu) High-Z AMI_WR O/T (ipu) High-Z FLAG[0] INPUT FLAG1/IRQ1 I/O (ipu) FLAG[1] FLAG1/Interrupt Request1. INPUT FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2] FLAG2/Interrupt Request2/Memory Select2. INPUT FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3] FLAG3/Timer Expired/Memory Select3. INPUT The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. FLAG0/IRQ0 I/O (ipu) Description External Address. The processor outputs addresses for external memory and peripherals on these pins. The ADDR pins can be multiplexed to support the external memory interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4 pins for parallel input data. External Data. The data pins can be multiplexed to support the external memory interface data (I/O), and FLAGS7–0 (I/O). Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait states to an external memory access. AMI_ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS1-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS1-0 lines are inactive; they are active however when a conditional memory access instruction is executed, when the condition evaluates as true. The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from external memory. AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to external memory. FLAG0/Interrupt Request0. Rev. B | Page 14 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 11. Pin Descriptions (Continued) Name SDRAS Type O/T (ipu) State During/ After Reset High-Z/ driven high High-Z/ driven high High-Z/ driven high Description SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDCAS O/T (ipu) SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDWE O/T (ipu) SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDCKE O/T (ipu) High-Z/ SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK driven high signal. For details, see the data sheet supplied with the SDRAM device. SDA10 O/T (ipu) High-Z/ SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM driven high accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses. SDDQM O/T (ipu) High-Z/ DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal driven high for read accesses. Input data is masked when DQM is sampled high during a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM is sampled high during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initialization completes. Afterwards it is driven low irrespective of whether any SDRAM accesses occur or not. SDCLK O/T (ipd) High-Z/ SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See driving Figure 41 on Page 55. For models in the 100-lead package, the SDRAM interface should be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. DAI _P20–1 I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. DPI _P14–1 The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. WDT_CLKIN I Watchdog Timer Clock Input. This pin should be pulled low when not used. WDT_CLKO O Watchdog Resonator Pad Output. WDTRSTO O (ipu) Watchdog Timer Reset Out. THD_P I Thermal Diode Anode. When not used, this pin can be left floating. THD_M O Thermal Diode Cathode. When not used, this pin can be left floating. The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. Rev. B | Page 15 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 11. Pin Descriptions (Continued) Name MLBCLK1 Type I State During/ After Reset Description Media Local Bus Clock. This clock is generated by the MLB controller that is synchronized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be grounded. 1 I/O/T in 3 High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and MLBDAT pin mode. I is received by all other MLB devices including the MLB controller. The MLBDAT line in 5 pin carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB mode. controller is not used, this pin should be grounded. MLBSIG1 I/O/T in 3 High-Z Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address pin mode. I generated by the MLB Controller, as well as the Command and RxStatus bytes from in 5 pin MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, mode this pin should be grounded. 1 MLBDO O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode. This serves as the output data pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground. 1 MLBSO O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground. TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the device. TRST I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. EMU O (O/D, ipu) High-Z Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools product line of JTAG emulators target board connector only. The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. Rev. B | Page 16 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 11. Pin Descriptions (Continued) Name CLK_CFG1–0 Description Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are: 00 = 8:1 01 = 32:1 10 = 16:1 11 = reserved CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. RESETOUT/ I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also RUNRSTIN has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. BOOT_CFG2–0 I Boot Configuration Select. These pins select the boot mode for the processor (see Table 9). The BOOT_CFG pins must be valid before RESET (hardware and software) is asserted. The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. 1 Type I State During/ After Reset The MLB pins are only available on the automotive models. Table 12. Pin List, Power and Ground Name VDD_INT VDD_EXT GND1 VDD_THD 1 Type P P G P Description Internal Power Supply I/O Power Supply Ground Thermal Diode Power Supply. When not used, this pin can be left floating. The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided in the package. Rev. B | Page 17 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SPECIFICATIONS OPERATING CONDITIONS 300 MHz / 350 MHz / 400 MHz Parameter1 Description VDD_INT 2 Internal (Core) Supply Voltage 450 MHz Min Nom Max Min Nom Max Unit 1.05 1.1 1.15 SVSNOM – 25 mV 1.0 – 1.15 SVSNOM + 25 mV V VDD_EXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V VDD_THD Thermal Diode Supply Voltage 3.13 3.47 3.13 3.47 V VIH3 High Level Input Voltage @ VDD_EXT = Max 2.0 3.6 2.0 3.6 V VIL3 Low Level Input Voltage @ VDD_EXT = Min –0.3 0.8 –0.3 0.8 V VIH_CLKIN4 High Level Input Voltage @ VDD_EXT = Max 2.2 VDD_EXT 2.2 VDD_EXT V VIL_CLKIN Low Level Input Voltage @ VDD_EXT = Min –0.3 +0.8 –0.3 +0.8 V TJ Junction Temperature 100-Lead LQFP_EP @ TAMBIENT 0°C to +70°C 0 110 0 115 °C TJ Junction Temperature 100-Lead LQFP_EP @ TAMBIENT –40°C to +85°C –40 125 NA NA °C TJ Junction Temperature 176-Lead LQFP_EP @ TAMBIENT 0°C to +70°C 0 110 0 115 °C TJ Junction Temperature 176-Lead LQFP_EP @ TAMBIENT –40°C to +85°C –40 125 NA NA °C 1 Specifications subject to change without notice. SVSNOM refers to the nominal SVS voltage which is set between 1.0 V and 1.15 V at the factory for each individual device. Only the unique SVSNOM value in each chip may be used for 401 MHz to 450 MHz operation of that chip. This spec lists the possible range of the SVSNOM values for all devices. The initial VDD_INT voltage at power on is 1.1 V nominal and it transitions to SVS programmed voltage as outlined in Engineer-to-Engineer Note “Static Voltage Scaling for ADSP-2148x Processors” (EE-357). 3 Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, AMI_ACK, MLBCLK, MLBDAT, MLBSIG. 4 Applies to input pins CLKIN, WDT_CLKIN. 2 Rev. B | Page 18 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 ELECTRICAL CHARACTERISTICS 300 MHz / 350 MHz / 400 MHz / 450 MHz Parameter1 Description 2 Test Conditions Min 2.4 VOH High Level Output Voltage @ VDD_EXT = Min, IOH = –1.0 mA3 VOL2 Low Level Output Voltage @ VDD_EXT = Min, IOL = 1.0 mA3 IIH4, 5 IIL4 Typ Max Unit V 0.4 V High Level Input Current @ VDD_EXT = Max, VIN = VDD_EXT Max 10 μA Low Level Input Current @ VDD_EXT = Max, VIN = 0 V Low Level Input Current @ VDD_EXT = Max, VIN = 0 V Pull-up 10 μA 200 μA IOZH6, 7 Three-State Leakage Current @ VDD_EXT = Max, VIN = VDD_EXT Max 10 μA IOZL6 Three-State Leakage Current @ VDD_EXT = Max, VIN = 0 V 10 μA IOZLPU7 Three-State Leakage Current Pull-up @ VDD_EXT = Max, VIN = 0 V 200 μA IOZHPD8 Three-State Leakage Current Pull-down @ VDD_EXT = Max, VIN = VDD_EXT Max 200 μA IDD_INT9 Supply Current (Internal) fCCLK > 0 MHz IDD_INT Supply Current (Internal) VDDINT = 1.1 V, ASF = 1, TJ = 25°C CIN10, 11 Input Capacitance 5 IILPU Table 14 + Table 15 mA × ASF 410 / 450 / 500 / 550 TCASE = 25°C mA 5 1 pF Specifications subject to change without notice. Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO, MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1. 3 See Output Drive Currents on Page 55 for typical drive current capabilities. 4 Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN. 5 Applies to input pins with internal pull-ups: TRST, TMS, TDI. 6 Applies to three-statable pin: TDO. 7 Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU. 8 Applies to three-statable pin with pull-down: SDCLK. 9 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-214xx SHARC Processors” (EE-348) for further information. 10 Applies to all signal pins. 11 Guaranteed, but not tested. 2 Rev. B | Page 19 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Total Power Dissipation The information in this section should be augmented with the Engineer-to-Engineer Note “Estimating Power for ADSP-214xx SHARC Processors” (EE-348). Table 13. Activity Scaling Factors (ASF)1 Activity Idle Low Medium Low Medium High Peak Typical (50:50)2 Peak Typical (60:40)2 Peak Typical (70:30)2 High Typical High Peak Total power dissipation has two components: 1. Internal power consumption is additionally comprised of two components: • Static current due to leakage. Table 14 shows the static current consumption (IDD_INT_STATIC) as a function of junction temperature (TJ) and core voltage (VDD_INT). • Dynamic current (IDD_INT_DYNAMIC), due to transistor switching characteristics and activity level of the processor. The activity level is reflected by the Activity Scaling Factor (ASF), which represents the activity level of the application code running on the processor core and having various levels of peripheral and external port activity (Table 13). Dynamic current consumption is calculated by selecting the ASF that corresponds most closely with the user application and then multiplying that with the dynamic current consumption (Table 15). Scaling Factor (ASF) 0.29 0.53 0.61 0.77 0.85 0.93 1.00 1.16 1.25 1.31 1 See the Engineer-to-Engineer Note “Estimating Power for ADSP-214xx SHARC Processors” (EE-348) for more information on the explanation of the power vectors specific to the ASF table. 2 Ratio of continuous instruction loop (core) to SDRAM control code reads and writes. 2. External power consumption is due to the switching activity of the external pins. Table 14. Static Current—IDD_INT_STATIC (mA)1 TJ (°C) –45 –35 –25 –15 –5 +5 +15 +25 +35 +45 +55 +65 +75 +85 +95 +105 +115 +125 1 0.975 V 68 74 82 94 109 129 152 182 217 259 309 369 437 519 615 727 853 997 1.0 V 77 83 92 104 121 142 168 199 237 282 334 398 471 559 662 779 914 1067 1.025 V 86 92 101 115 133 156 183 216 256 305 361 429 506 599 707 833 975 1138 1.05 V 96 103 113 127 147 171 201 237 279 331 391 464 547 645 761 897 1047 1219 VDD_INT (V) 1.075 V 107 114 125 140 161 188 219 257 303 359 423 500 588 693 816 958 1119 1305 1.10 V 118 126 138 155 177 206 240 280 329 389 458 539 633 746 877 1026 1198 1397 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 18. Rev. B | Page 20 of 68 | March 2013 1.125 V 131 140 153 171 194 225 261 305 358 421 495 582 682 802 942 1103 1285 1498 1.15 V 144 154 168 187 212 245 285 331 388 455 533 626 731 860 1007 1179 1372 1601 1.175 V 159 170 185 205 233 268 309 360 420 492 576 675 789 926 1083 1266 1473 1716 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 15. Dynamic Current in CCLK Domain—IDD_INT_DYNAMIC (mA, with ASF = 1.0)1, 2 fCCLK (MHz) 100 150 200 250 300 350 400 450 1 2 VDD_INT (V) 0.975 V 76 117 153 190 227 263 300 339 1.0 V 77 119 156 195 233 272 309 349 1.025 V 81 123 161 201 240 278 317 356 1.05 V 84 126 165 207 246 286 326 365 1.075 V 87 130 170 212 253 294 335 374 1.10 V 88 133 174 217 260 302 344 385 1.125 V 90 136 179 223 266 309 352 394 1.15 V 92 139 183 229 273 318 361 405 1.175 V 95 144 188 235 280 325 370 415 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 19. Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 18. ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Stresses greater than those listed in Table 16 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The information presented in Figure 3 provides details about the package branding for the ADSP-2148x processors. For a complete listing of product availability, see Ordering Guide on Page 66. a Table 16. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDD_INT) External (I/O) Supply Voltage (VDD_EXT) Thermal Diode Supply Voltage (VDD_THD) Input Voltage Output Voltage Swing Storage Temperature Range Junction Temperature While Biased ADSP-2148x tppZ-cc Rating –0.3 V to +1.32 V –0.3 V to +3.6 V –0.3 V to +3.6 V vvvvvv.x n.n #yyww country_of_origin S –0.5 V to +3.6 V –0.5 V to VDD_EXT +0.5 V –65°C to +150°C 125°C Figure 3. Typical Package Brand Table 17. Package Brand Information1 Brand Key t pp Z cc vvvvvv.x n.n # yyww ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 1 Non automotive only. For branding information specific to automotive products, contact Analog Devices Inc. MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-214xx SHARC Processors” (EE-348) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 56. Rev. B | Page 21 of 68 | Field Description Temperature Range Package Type RoHS Compliant Option See Ordering Guide Assembly Lot Code Silicon Revision RoHS Compliant Designation Date Code March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 TIMING SPECIFICATIONS Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 43 on Page 55 for voltage reference levels. Core Clock Requirements The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, the processor core, and the serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 4). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. PMCTL (SDCKR) PMCTL (PLLBP) CLKIN DIVIDER fINPUT LOOP FILTER VCO fVCO PLL DIVIDER fCCLK CCLK SDRAM DIVIDER BYPASS MUX CLKIN BYPASS MUX PLL XTAL BUF CLK_CFGx/ PMCTL (2 × PLLM) PMCTL (INDIV) PMCTL (PLLD) DIVIDE BY 2 PMCTL (PLLBP) SDCLK PCLK fVCO ÷ (2 × PLLM) PCLK CCLK RESET DELAY OF 4096 CLKIN CYCLES PIN MUX CLKOUT (TEST ONLY)* RESETOUT BUF RESETOUT CORESRST *CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT. THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN. Figure 4. Core Clock and System Clock Relationship to CLKIN where: Voltage Controlled Oscillator (VCO) In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 20. • The product of CLKIN and PLLM must never exceed 1/2 of fVCO (max) in Table 20 if the input divider is not enabled (INDIV = 0). • The product of CLKIN and PLLM must never exceed fVCO (max) in Table 20 if the input divider is enabled (INDIV = 1). fVCO = VCO output PLLM = Multiplier value programmed in the PMCTL register. During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware. PLLD = 2, 4, 8, or 16 based on the divider value programmed on the PMCTL register. During reset this value is 2. fINPUT = is the input frequency to the PLL. fINPUT = CLKIN when the input divider is disabled or fINPUT = CLKIN ÷ 2 when the input divider is enabled The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT fCCLK = (2 × PLLM × fINPUT) ÷ PLLD Rev. B | Page 22 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 18. All of the timing specifications for the ADSP-2148x peripherals are defined in relation to tPCLK. See the peripheral specific section for each peripheral’s timing information. Power-Up Sequencing The timing requirements for processor startup are given in Table 19. While no specific power-up sequencing is required between VDD_EXT and VDD_INT, there are some considerations that system designs should take into account. • No power supply should be powered up for an extended period of time (> 200 ms) before another supply starts to ramp up. Table 18. Clock Periods Timing Requirements tCK tCCLK tPCLK tSDCLK Description CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × tCCLK SDRAM Clock Period = (tCCLK) × SDCKR Figure 4 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-214xx SHARC Processor Hardware Reference. • If the VDD_INT power supply comes up after VDD_EXT, any pin, such as RESETOUT and RESET, may actually drive momentarily until the VDD_INT rail has powered up. Systems sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior. Note that during power-up, when the VDD_INT power supply comes up after VDD_EXT, a leakage current of the order of threestate leakage current pull-up, pull-down may be observed on any pin, even if that is an input only (for example the RESET pin) until the VDD_INT rail has powered up. Table 19. Power Up Sequencing Timing Requirements (Processor Startup) Parameter Min Max Unit Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD 1 tCLKRST tPLLRST RESET Low Before VDD_EXT or VDD_INT On 0 VDD_INT On Before VDD_EXT –200 +200 ms CLKIN Valid After VDD_INT and VDD_EXT Valid 0 200 ms CLKIN Valid Before RESET Deasserted ms 2 μs 3 μs 10 PLL Control Setup Before RESET Deasserted 20 Core Reset Deasserted After RESET Deasserted 4096 × tCK + 2 × tCCLK Switching Characteristic tCORERST4, 5 1 Valid VDD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles. 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4096 cycle count depends on tSRST specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. Rev. B | Page 23 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 RESET tRSTVDD VDDINT tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1–0 tPLLRST tCORERST RESETOUT Figure 5. Power-Up Sequencing Clock Input Table 20. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low CLKIN Width High tCKH tCKRF3 CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK4 CCLK Period fVCO5 VCO Frequency tCKJ6, 7 CLKIN Jitter Tolerance 300 MHz Min Max 350 MHz Min Max 400 MHz Min Max 450 MHz Min Max 26.661 13 13 22.81 11 11 201 10 10 17.751 8.875 8.875 1002 45 45 3 10 800 +250 3.33 200 –250 2.85 200 –250 1002 45 45 3 10 800 +250 2.5 200 –250 1 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL. Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL. 3 Guaranteed by simulation but not tested on silicon. 4 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 5 See Figure 4 on Page 22 for VCO diagram. 6 Actual input jitter should be combined with ac specifications for accurate timing analysis. 7 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. 2 tCKJ tCK CLKIN tCKH tCKL Figure 6. Clock Input Rev. B | Page 24 of 68 | March 2013 1002 45 45 3 10 800 +250 2.22 200 –250 1002 45 45 3 10 900 +250 Unit ns ns ns ns ns MHz ps ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Clock Signals The ADSP-2148x can use an external clock or a crystal. See the CLKIN pin description in Table 11 on Page 14. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 7 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-2148x CLKIN R1 0ȍ XTAL R2 47ȍ C1 22pF Y1 C2 22pF CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1. R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS. 25 MHz TYPICAL VALUES Figure 7. Recommended Circuit for Fundamental Mode Crystal Operation Rev. B | Page 25 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Reset Table 21. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min Max 4 × tCK 8 Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μ while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 8. Reset Running Reset The following timing specification applies to RESETOUT/RUNRSTIN pin when it is configured as RUNRSTIN. Table 22. Running Reset Parameter Timing Requirements tWRUNRST Running RESET Pulse Width Low tSRUNRST Running RESET Setup Before CLKIN High Min Max 4 × tCK 8 ns ns CLKIN tWRUNRST tSRUNRST RUNRSTIN Figure 9. Running Reset Rev. B | Page 26 of 68 | Unit March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts, as well as the DAI_P20–1 and DPI_P14–1 pins when they are configured as interrupts. Table 23. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min Max 2 × tPCLK +2 Unit ns INTERRUPT INPUTS tIPW Figure 10. Interrupts Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 24. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min Max 4 × tPCLK – 1 tWCTIM FLAG3 (TMREXP) Figure 11. Core Timer Rev. B | Page 27 of 68 | March 2013 Unit ns ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Timer PWM_OUT Cycle Timing The following timing specification applies to timer0 and timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 25. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min Max Unit 2 × tPCLK – 1.2 2 × (231 – 1) × tPCLK ns tPWMO PWM OUTPUTS Figure 12. Timer PWM_OUT Timing Timer WDTH_CAP Timing The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse-width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1 pins. Table 26. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width Min Max Unit 2 × tPCLK 2 × (231 – 1) × tPCLK ns tPWI TIMER CAPTURE INPUTS Figure 13. Timer Width Capture Timing Rev. B | Page 28 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Watchdog Timer Timing Table 27. Watchdog Timer Timing Parameter Timing Requirement tWDTCLKPER Switching Characteristics tRST WDT Clock Rising Edge to Watchdog Timer RESET Falling Edge tRSTPW Reset Pulse Width Min Max Unit 100 1000 ns 3 6.4 ns 64 × tWDTCLKPER ns tWDTCLKPER WDT_CLKIN tRST tRSTPW WDTRSTO Figure 14. Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 28. DAI/DPI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid Min Max Unit 1.5 12 ns DAI_Pn DPI_Pn tDPIO DAI_Pm DPI_Pm Figure 15. DAI Pin to Pin Direct Routing Rev. B | Page 29 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20). Table 29. Precision Clock Generator (Direct Pin Routing) Parameter Min Max Unit Timing Requirements tPCGIW Input Clock Period tPCLK × 4 ns tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input 4.5 ns Clock tHTRIG PCG Trigger Hold After Falling Edge of PCG Input 3 ns Clock Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge 2.5 10 ns Delay After PCG Input Clock tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × tPCGIP) 10 + (2.5 × tPCGIP) ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns tPCGOW1 Output Clock Period 2 × tPCGIP – 1 ns D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 Normal mode of operation. tSTRIG tHTRIG DAI_Pn DPI_Pn PCG_TRIGx_I DAI_Pm DPI_Pm PCG_EXTx_I (CLKIN) tPCGIP tDPCGIO DAI_Py DPI_Py PCG_CLKx_O tDTRIGCLK tDPCGIO DAI_Pz DPI_Pz PCG_FSx_O tDTRIGFS Figure 16. Precision Clock Generator (Direct Pin Routing) Rev. B | Page 30 of 68 | March 2013 tPCGOW ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Flags The timing specifications provided below apply to the DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0, and FLAG3–0 pins when configured as FLAGS. See Table 11 on Page 14 for more information on flag use. Table 30. Flags Parameter Timing Requirement tFIPW1 FLAGs IN Pulse Width Switching Characteristic FLAGs OUT Pulse Width tFOPW1 1 Min tFIPW FLAG OUTPUTS tFOPW Figure 17. Flags Rev. B | Page 31 of 68 | March 2013 Unit 2 × tPCLK + 3 ns 2 × tPCLK – 3 ns This is applicable when the Flags are connected to DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0 and FLAG3–0 pins. FLAG INPUTS Max ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SDRAM Interface Timing (166 MHz SDCLK) The maximum frequency for SDRAM is 166 MHz. For information on SDRAM frequency and programming, see the ADSP-214xx SHARC Processor Hardware Reference, Engineerto-Engineer Note “Interfacing SDRAM Memories to SHARC Processors” (EE-286), and the SDRAM vendor data sheet. Table 31. SDRAM Interface Timing Parameter Timing Requirements tSSDAT DATA Setup Before SDCLK tHSDAT DATA Hold After SDCLK Switching Characteristics tSDCLK1 SDCLK Period SDCLK Width High tSDCLKH tSDCLKL SDCLK Width Low tDCAD2 Command, ADDR, Data Delay After SDCLK tHCAD2 Command, ADDR, Data Hold After SDCLK tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK Min Max Unit 0.7 1.23 ns ns 6 2.2 2.2 ns ns ns ns ns ns ns 4 1 5.3 0.3 1 Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 166 MHz the SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM Memories to SHARC Processors” (EE-286) for more information on hardware design guidelines for the SDRAM interface. 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE. tSDCLKH tSDCLK SDCLK tSSDAT tHSDAT tSDCLKL DATA (IN) tDCAD tENSDAT tHCAD DATA (OUT) tDCAD tHCAD COMMAND/ADDR (OUT) Figure 18. SDRAM Interface Timing Rev. B | Page 32 of 68 | March 2013 tDSDAT ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 AMI Read Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 32. AMI Read Parameter Min Timing Requirements tDAD1, 2, 3 Address Selects Delay to Data Valid 1, 3 tDRLD AMI_RD Low to Data Valid Data Setup to AMI_RD High 2.5 tSDS tHDRH4, 5 Data Hold from AMI_RD High 0 2, 6 tDAAK AMI_ACK Delay from Address, Selects tDSAK4 AMI_ACK Delay from AMI_RD Low Switching Characteristics tDRHA Address Selects Hold After AMI_RD High RHC + 0.20 Address Selects to AMI_RD Low tSDCLK – 3.8 tDARL2 tRW AMI_RD Pulse Width W – 1.4 tRWR AMI_RD High to AMI_RD Low HI + tSDCLK – 1 W = (number of wait states specified in AMICTLx register) × tSDCLK. RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK Where PREDIS = 0 HI = RHC: Read to Read from same bank HI = RHC + IC: Read to Read from different bank HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank Where PREDIS = 1 HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank HI = RHC + (3 × tSDCLK): Read to Read from same bank HI = RHC + Max (IC, (3 × tSDCLK): Read to Read from different bank IC = (number of idle cycles specified in AMICTLx register) × tSDCLK H = (number of hold cycles specified in AMICTLx register) × tSDCLK 1 Max Unit W + tSDCLK –5.4 W – 3.2 ns ns ns ns ns ns tSDCLK –9.5 + W W–7 ns ns ns ns Data delay/setup: System must meet tDAD, tDRLD, or tSDS. The falling edge of MSx, is referenced. 3 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used. 4 Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. 5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 55 for the calculation of hold times given capacitive and dc loads. 6 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). 2 Rev. B | Page 33 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 AMI_ADDR AMI_MSx tDARL tRW tDRHA AMI_RD tDRLD tSDS tDAD tHDRH AMI_DATA tRWR tDSAK tDAAK AMI_ACK AMI_WR Figure 19. AMI Read Rev. B | Page 34 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 AMI Write Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 33. AMI Write Parameter Min Timing Requirements tDAAK1, 2 AMI_ACK Delay from Address, Selects 1, 3 tDSAK AMI_ACK Delay from AMI_WR Low Switching Characteristics tDAWH2 Address Selects to AMI_WR Deasserted tSDCLK – 3.1+ W 2 tDAWL Address Selects to AMI_WR Low tSDCLK – 3 tWW AMI_WR Pulse Width W – 1.3 tDDWH Data Setup Before AMI_WR High tSDCLK – 3.7+ W tDWHA Address Hold After AMI_WR Deasserted H + 0.15 Data Hold After AMI_WR Deasserted H tDWHD tDATRWH4 Data Disable After AMI_WR Deasserted tSDCLK – 4.3 + H 5 tWWR AMI_WR High to AMI_WR Low tSDCLK – 1.5+ H tDDWR Data Disable Before AMI_RD Low 2 × tSDCLK – 6 tWDE AMI_WR Low to Data Enabled tSDCLK – 3.7 W = (number of wait states specified in AMICTLx register) × tSDCLK H = (number of hold cycles specified in AMICTLx register) × tSDCLK Max Unit tSDCLK – 9.7 + W W–6 ns ns tSDCLK + 4.9 + H 1 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). The falling edge of MSx is referenced. 3 Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode. 4 See Test Conditions on Page 55 for calculation of hold times given capacitive and dc loads. 5 For Write to Write: tSDCLK + H, for both same bank and different bank. For Write to Read: 3 × tSDCLK + H, for the same bank and different banks. 2 AMI_ADDR AMI_MSx tDWHA tDAWH tDAWL tWW AMI_WR tWWR tWDE tDATRWH tDDWH AMI_DATA tDSAK tDWHD tDAAK AMI_ACK AMI_RD Figure 20. AMI Write Rev. B | Page 35 of 68 | March 2013 tDDWR ns ns ns ns ns ns ns ns ns ns ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Serial Ports In slave transmitter mode and master receiver mode, the maximum serial port frequency is fPCLK/8. In master transmitter mode and slave receiver mode, the maximum serial port clock frequency is fPCLK/4. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width. Serial port signals (SCLK, frame sync, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 34. Serial Ports—External Clock Parameter Timing Requirements Frame Sync Setup Before SCLK tSFSE1 (Externally Generated Frame Sync in either Transmit or Receive Mode) tHFSE1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) tSDRE1 Receive Data Setup Before Receive SCLK 1 tHDRE Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in either Transmit or Receive Mode) tHOFSE2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in either Transmit or Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK tHDTE2 Transmit Data Hold After Transmit SCLK 1 2 Min Max Unit 2.5 ns 2.5 ns 1.9 2.5 (tPCLK × 4) ÷ 2 – 1.5 tPCLK × 4 ns ns ns ns 10.25 ns 2 ns ns ns 9 2 Referenced to sample edge. Referenced to drive edge. Table 35. Serial Ports—Internal Clock Parameter Timing Requirements Frame Sync Setup Before SCLK tSFSI1 (Externally Generated Frame Sync in either Transmit or Receive Mode) Frame Sync Hold After SCLK tHFSI1 (Externally Generated Frame Sync in either Transmit or Receive Mode) Receive Data Setup Before SCLK tSDRI1 Receive Data Hold After SCLK tHDRI1 Switching Characteristics Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) tDFSI2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) tHOFSI2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) tDFSIR2 tHOFSIR2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) 2 Transmit Data Delay After SCLK tDDTI Transmit Data Hold After SCLK tHDTI2 tSCKLIW Transmit or Receive SCLK Width 1 2 Referenced to the sample edge. Referenced to drive edge. Rev. B | Page 36 of 68 | March 2013 Min Max Unit 7 ns 2.5 ns ns ns 7 2.5 4 –1 9.75 –1 3.25 –2 2 × tPCLK – 1.5 2 × tPCLK + 1.5 ns ns ns ns ns ns ns ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) tDFSI tDFSE tSFSI tHOFSI tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) tSCLKW SAMPLE EDGE DAI_P20–1 (SCLK) tDFSI tDFSE tHOFSI tSFSI tHFSI DAI_P20–1 (FS) tSFSE tHOFSE DAI_P20–1 (FS) tHDTI tDDTI tHDTE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) Figure 21. Serial Ports Rev. B | Page 37 of 68 | March 2013 tDDTE tHFSE ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 36. Serial Ports—External Late Frame Sync Parameter Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 1 Min Max 8.5 ns ns 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified, as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tHFSE/I tSFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tHFSE/I tSFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT t Figure 22. External Late Frame Sync1 1 This figure reflects changes made to support left-justified mode. Rev. B | Page 38 of 68 | March 2013 Unit ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 37. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK tDDTTE1 tDDTIN1 Data Enable from Internal Transmit SCLK 1 Min Max Unit 11.5 ns ns ns 2 –1.5 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) tDDTEN tDDTTE DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 (SCLK, INT) tDDTIN DAI_P20–1 (DATA CHANNEL A/B) Figure 23. Serial Ports—Enable and Three-State Rev. B | Page 39 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The SPORTx_TDV_O output signal (routing unit) becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPORTx_TDV_O is asserted for communication with external devices. Table 38. Serial Ports—TDV (Transmit Data Valid) Parameter Switching Characteristics1 tDRDVEN TDV Assertion Delay from Drive Edge of External Clock tDFDVEN TDV Deassertion Delay from Drive Edge of External Clock tDRDVIN TDV Assertion Delay from Drive Edge of Internal Clock tDFDVIN TDV Deassertion Delay from Drive Edge of Internal Clock 1 Min Max 3 8 –1 2 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) TDVx DAI_P20-1 tDFDVEN tDRDVEN DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, INT) TDVx DAI_P20-1 tDFDVIN tDRDVIN Figure 24. Serial Ports—TDM Internal and External Clock Rev. B | Page 40 of 68 | March 2013 Unit ns ns ns ns ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Input Data Port (IDP) The timing requirements for the IDP are given in Table 39. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 39. Input Data Port (IDP) Parameter Timing Requirements tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge 1 tSIHFS Frame Sync Hold After Serial Clock Rising Edge Data Setup Before Serial Clock Rising Edge tSISD1 tSIHD1 Data Hold After Serial Clock Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 Min 3.8 2.5 2.5 2.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 Max Unit ns ns ns ns ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. tIDPCLK SAMPLE EDGE DAI_P20–1 (SCLK) tIDPCLKW tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 25. IDP Master Timing Rev. B | Page 41 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 PDAP chapter of the ADSP-214xx SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the ADDR23–4 pins or over the DAI pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 40. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the Table 40. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements PDAP_HOLD Setup Before PDAP_CLK Sample Edge tSPHOLD1 tHPHOLD1 PDAP_HOLD Hold After PDAP_CLK Sample Edge tPDSD1 PDAP_DAT Setup Before PDAP_CLK Sample Edge 1 tPDHD PDAP_DAT Hold After PDAP_CLK Sample Edge tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width 1 Min Max Unit 2.5 2.5 3.85 2.5 (tPCLK × 4) ÷ 2 – 3 tPCLK × 4 ns ns ns ns ns ns 2 × tPCLK + 3 2 × tPCLK – 1.5 ns ns Source pins of PDAP_DATA are ADDR23–4 or DAI pins. Source pins for PDAP_CLK and PDAP_HOLD are 1) DAI pins; 2) CLKIN through PCG; 3) DAI pins through PCG; or 4) ADDR3–2 pins. SAMPLE EDGE tPDCLK tPDCLKW DAI_P20–1 (PDAP_CLK) tHPHOLD tSPHOLD DAI_P20–1 (PDAP_HOLD) tPDHD tPDSD DAI_P20–1/ ADDR23–4 (PDAP_DATA) tPDHLDD DAI_P20–1 (PDAP_STROBE) Figure 26. PDAP Timing Rev. B | Page 42 of 68 | March 2013 tPDSTRB ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Sample Rate Converter—Serial Input Port The ASRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 41 are valid at the DAI_P20–1 pins. Table 41. ASRC, Serial Input Port Parameter Timing Requirements Frame Sync Setup Before Serial Clock Rising Edge tSRCSFS1 tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge tSRCSD1 Data Setup Before Serial Clock Rising Edge 1 tSRCHD Data Hold After Serial Clock Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period 1 Min 4 5.5 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 Max Unit ns ns ns ns ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI_P20–1 (SCLK) tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCSD tSRCHD DAI_P20–1 (SDATA) Figure 27. ASRC Serial Input Port Timing Rev. B | Page 43 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 specification with regard to serial clock. Note that serial clock rising edge is the sampling edge, and the falling edge is the drive edge. Sample Rate Converter—Serial Output Port For the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to SCLK on the output port. The serial data output has a hold time and delay Table 42. ASRC, Serial Output Port Parameter Timing Requirements Frame Sync Setup Before Serial Clock Rising Edge tSRCSFS1 tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period Switching Characteristics tSRCTDD1 Transmit Data Delay After Serial Clock Falling Edge 1 Transmit Data Hold After Serial Clock Falling Edge tSRCTDH 1 Min Max 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 ns ns ns ns 9.9 1 Unit ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI_P20–1 (SCLK) tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCTDD tSRCTDH DAI_P20–1 (SDATA) Figure 28. ASRC Serial Output Port Timing Rev. B | Page 44 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Pulse-Width Modulation Generators (PWM) The following timing specifications apply when the ADDR23–8/DPI_14–1 pins are configured as PWM. Table 43. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min Max Unit tPCLK – 2 2 × tPCLK – 1.5 (216 – 2) × tPCLK (216 – 1) × tPCLK ns ns tPWMW PWM OUTPUTS tPWMP Figure 29. PWM Timing S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 30 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is rightjustified to the next frame sync transition. Table 44. S/PDIF Transmitter Right-Justified Mode Parameter Timing Requirement tRJD Frame Sync to MSB Delay in Right-Justified Mode 16-Bit Word Mode 18-Bit Word Mode 20-Bit Word Mode 24-Bit Word Mode Unit 16 14 12 8 SCLK SCLK SCLK SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK DAI_P20–1 SDATA Nominal tRJD LSB MSB MSB–1 MSB–2 Figure 30. Right-Justified Mode Rev. B | Page 45 of 68 | March 2013 LSB+2 LSB+1 LSB ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Figure 31 shows the default I2S-justified mode. The frame sync is low for the left channel and HI for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. Table 45. S/PDIF Transmitter I2S Mode Parameter Timing Requirement tI2SD Frame Sync to MSB Delay in I2S Mode DAI_P20–1 SDATA Unit 1 SCLK Nominal Unit 0 SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK Nominal tI2SD MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 31. I2S-Justified Mode Figure 32 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition with no delay. Table 46. S/PDIF Transmitter Left-Justified Mode Parameter Timing Requirement tLJD Frame Sync to MSB Delay in Left-Justified Mode DAI_P20–1 FS LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 32. Left-Justified Mode Rev. B | Page 46 of 68 | March 2013 LSB ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 47. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 47. S/PDIF Transmitter Input Data Timing Parameter Timing Requirements tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge tSIHFS1 Frame Sync Hold After Serial Clock Rising Edge tSISD1 Data Setup Before Serial Clock Rising Edge tSIHD1 Data Hold After Serial Clock Rising Edge Transmit Clock Width tSITXCLKW tSITXCLK Transmit Clock Period tSISCLKW Clock Width tSISCLK Clock Period 1 Min Max 3 3 3 3 9 20 36 80 Unit ns ns ns ns ns ns ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSITXCLKW tSITXCLK DAI_P20–1 (TxCLK) tSISCLK tSISCLKW DAI_P20–1 (SCLK) tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 33. S/PDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the internal biphase clock. Table 48. Oversampling Clock (TxCLK) Switching Characteristics Parameter Frequency for TxCLK = 384 × Frame Sync Frequency for TxCLK = 256 × Frame Sync Frame Rate (FS) Max Oversampling Ratio × Frame Sync <= 1/tSITXCLK 49.2 192.0 Rev. B | Page 47 of 68 | March 2013 Unit MHz MHz kHz ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Switching Characteristics tDFSI tHOFSI tDDTI tHDTI tSCLKIW1 1 Min Frame Sync Delay After Serial Clock Frame Sync Hold After Serial Clock Transmit Data Delay After Serial Clock Transmit Data Hold After Serial Clock Transmit Serial Clock Width Unit 5 ns ns ns ns ns –2 5 –2 8 × tPCLK – 2 SCLK frequency is 64 × FS where FS = the frequency of frame sync. SAMPLE EDGE DRIVE EDGE tSCLKIW DAI_P20–1 (SCLK) tDFSI tHOFSI DAI_P20–1 (FS) tDDTI tHDTI DAI_P20–1 (DATA CHANNEL A/B) Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. B | Max Page 48 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SPI Interface—Master The ADSP-2148x contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in Table 50 and Table 51 applies to both. Table 50. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements Data Input Valid to SPICLK Edge (Data Input Setup Time) tSSPIDM tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period SPICLK Edge to Data Out Valid (Data Out Delay Time) tDDSPIDM tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tSDSCIM DPI Pin (SPI Device Select) Low to First SPICLK Edge tHDSM Last SPICLK Edge to DPI Pin (SPI Device Select) High tSPITDM Sequential Transfer Delay Min Max 8.2 2 ns ns 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 ns ns ns ns ns ns ns ns 2.5 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 1.2 DPI (OUTPUT) tSDSCIM tSPICHM tSPICLM tSPICLKM SPICLK (CP = 0, CP = 1) (OUTPUT) tHDSM tHDSPIDM tDDSPIDM MOSI (OUTPUT) tSSPIDM tSSPIDM tHSPIDM CPHASE = 1 tHSPIDM MISO (INPUT) tHDSPIDM tDDSPIDM MOSI (OUTPUT) CPHASE = 0 tSSPIDM tHSPIDM MISO (INPUT) Figure 35. SPI Master Timing Rev. B | Page 49 of 68 | March 2013 Unit tSPITDM ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SPI Interface—Slave Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Min Serial Clock Cycle Serial Clock High Period Serial Clock Low Period SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 tSSPIDS Data Input Valid to SPICLK edge (Data Input Set-up Time) tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tSDPPW SPIDS Deassertion Pulse Width (CPHASE=0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active SPIDS Assertion to Data Out Active (SPI2) tDSOE1 tDSDHI SPIDS Deassertion to Data High Impedance 1 tDSDHI SPIDS Deassertion to Data High Impedance (SPI2) tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 1 Max Unit 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK ns ns ns ns 2 × tPCLK 2 2 2 × tPCLK ns ns ns ns 0 0 0 0 7.5 7.5 10.5 10.5 9.5 2 × tPCLK 5 × tPCLK ns ns ns ns ns ns ns The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral Interface Port” chapter. SPIDS (INPUT) SPICLK (CP = 0, CP = 1) (INPUT) tSPICHS tSPICLS tSPICLKS tHDS tSDSCO tDSOE tSDPPW tDSDHI tDDSPIDS tDDSPIDS tHDSPIDS MISO (OUTPUT) tSSPIDS tHSPIDS CPHASE = 1 MOSI (INPUT) tHDSPIDS MISO (OUTPUT) tDSOV CPHASE = 0 tSSPIDS MOSI (INPUT) Figure 36. SPI Slave Timing Rev. B | Page 50 of 68 | March 2013 tHSPIDS tDSDHI ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Media Local Bus All the numbers given are applicable for all speed modes (1024 FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for 5-pin), unless otherwise specified. Please refer to the MediaLB specification document revision 3.0 for more details. Table 52. MLB Interface, 3-Pin Specifications Parameter 3-Pin Characteristics tMLBCLK MLB Clock Period 1024 FS 512 FS 256 FS tMCKL MLBCLK Low Time 1024 FS 512 FS 256 FS tMCKH MLBCLK High Time 1024 FS 512 FS 256 FS tMCKR MLBCLK Rise Time (VIL to VIH) 1024 FS 512 FS/256 FS MLBCLK Fall Time (VIH to VIL) tMCKF 1024 FS 512 FS/256 FS 1 MLBCLK Pulse Width Variation tMPWV 1024 FS 512 FS/256 DAT/SIG Input Setup Time tDSMCF tDHMCF DAT/SIG Input Hold Time tMCFDZ DAT/SIG Output Time to Three-state DAT/SIG Output Data Delay From MLBCLK Rising Edge tMCDRV tMDZH2 Bus Hold Time 1024 FS 512 FS/256 DAT/SIG Pin Load CMLB 1024 FS 512 FS/256 1 2 Min Typ Max 20.3 40 81 Unit ns ns ns 6.1 14 30 ns ns ns 9.3 14 30 ns ns ns 1 2 0 1 3 ns ns 1 3 ns ns 0.7 2.0 nspp nspp 15 8 ns ns ns ns 2 4 ns ns 40 60 pf pf Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Rev. B | Page 51 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLBCLK tMCKR tMCKL tMCKF tMLBCLK tMCFDZ tMCDRV tMDZH MLBSIG/ MLBDAT (Tx, Output) VALID Figure 37. MLB Timing (3-Pin Interface) Table 53. MLB Interface, 5-Pin Specifications Parameter 5-Pin Characteristics tMLBCLK MLB Clock Period 512 FS 256 FS tMCKL MLBCLK Low Time 512 FS 256 FS tMCKH MLBCLK High Time 512 FS 256 FS tMCKR MLBCLK Rise Time (VIL to VIH) tMCKF MLBCLK Fall Time (VIH to VIL) 1 MLBCLK Pulse Width Variation tMPWV tDSMCF2 DAT/SIG Input Setup Time tDHMCF DAT/SIG Input Hold Time tMCDRV DS/DO Output Data Delay From MLBCLK Rising Edge tMCRDL3 DO/SO Low From MLBCLK High 512 FS 256 FS DS/DO Pin Load CMLB Min Typ Max 40 81 Unit ns ns 15 30 ns ns 15 30 ns ns 6 6 2 8 ns ns nspp ns ns ns 10 20 ns ns 40 pf 3 5 1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). 2 Gate Delays due to OR'ing logic on the pins must be accounted for. 3 When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset, external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven. Rev. B | Page 52 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLBCLK tMCKR tMCKL tMCKF tMLBCLK tMCRDL tMCDRV VALID MLBSO/ MLBDO (Tx, Output) Figure 38. MLB Timing (5-Pin Interface) MLBCLK tMPWV tMPWV Figure 39. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. 2-Wire Interface (TWI)—Receive and Transmit Timing For information on the TWI receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. Rev. B | Page 53 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 JTAG Test Access Port and Emulation Table 54. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low 2 tDSYS System Outputs Delay After TCK Low 1 2 Min Max 20 5 6 7 18 4tCK ns ns ns ns ns ns 10 tTCK ÷ 2 + 7 System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0. System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU. tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 40. IEEE 1149.1 JTAG Test Access Port Rev. B | Page 54 of 68 | March 2013 Unit ns ns ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 OUTPUT DRIVE CURRENTS TESTER PIN ELECTRONICS Figure 41 shows typical I-V characteristics for the output drivers of the ADSP-2148x, and Table 55 shows the pins associated with each driver. The curves represent the current drive capability of the output drivers as a function of output voltage. 50: VLOAD T1 70: ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: Table 55. Driver Types 0.5pF 4pF Driver Type Associated Pins A FLAG[0–3], AMI_ADDR[0–23], DATA[0–15], AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS, SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO, RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK B SDCLK 2pF 400: NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 42. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 200 SOURCE/SINK (VDDEXT) CURRENT (mA) DUT OUTPUT 45: 150 VOH 3.13 V, 125 °C TYPE B CAPACITIVE LOADING 100 Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 42). Figure 46 and Figure 47 show graphically how output delays and holds vary with load capacitance. The graphs of Figure 44 through Figure 47 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. TYPE A 50 0 TYPE A -50 -100 TYPE B -150 VOL 3.13 V, 125 °C 7 -200 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 6 Figure 41. Typical Drive at Junction Temperature TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 21 on Page 26 through Table 54 on Page 54. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 42. Timing is measured on signals when they cross the 1.5 V level as described in Figure 43. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. RISE AND FALL TIMES (ns) SWEEP (VDDEXT) VOLTAGE (V) TYPE A DRIVE FALL y = 0.0414x + 0.2661 TYPE A DRIVE RISE y = 0.0341x + 0.3093 5 4 TYPE B DRIVE RISE y = 0.0153x + 0.2131 3 2 TYPE B DRIVE FALL y = 0.0152x + 0.1882 1 0 0 25 50 75 100 125 150 LOAD CAPACITANCE (pF) Figure 44. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Max) INPUT 1.5V OR OUTPUT 1.5V Figure 43. Voltage Reference Levels for AC Measurements Rev. B | Page 55 of 68 | March 2013 175 200 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 9 14 8 TYPE A DRIVE FALL y = 0.0747x + 0.5154 10 RISE AND FALL TIMES DELAY (ns) RISE AND FALL TIMES (ns) 12 TYPE A DRIVE RISE y = 0.0571x + 0.5558 8 TYPE B DRIVE FALL y = 0.0278x + 0.3138 6 4 TYPE B DRIVE RISE y = 0.0258x + 0.3684 2 TYPE A DRIVE RISE y = 0.0256x + 3.5859 TYPE A DRIVE FALL y = 0.0359x + 2.924 7 TYPE B DRIVE RISE y = 0.0116x + 3.5697 6 5 4 3 TYPE B DRIVE FALL y = 0.0136x + 3.1135 2 1 0 0 25 50 75 100 125 150 175 200 0 0 25 50 LOAD CAPACITANCE (pF) Figure 45. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Min) 125 150 175 200 THERMAL CHARACTERISTICS TYPE A DRIVE FALL y = 0.0196x + 1.2945 4 RISE AND FALL DELAY (ns) 100 Figure 47. Typical Output Rise/Fall Delay (VDD_EXT = Min) 4.5 TYPE A DRIVE RISE y = 0.0152x + 1.7607 3.5 TYPE B DRIVE RISE y = 0.0068x + 1.7614 3 TYPE B DRIVE FALL y = 0.0074x + 1.421 2 The ADSP-2148x processor is rated for performance over the temperature range specified in Operating Conditions on Page 18. Table 57 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. Test board design complies with JEDEC standards JESD51-7 (LQFP_EP). The junction-to-case measurement complies with MIL- STD-883. All measurements use a 2S2P JEDEC test board. 2.5 1.5 To determine the junction temperature of the device while on the application PCB, use: 1 0.5 0 75 LOAD CAPACITANCE (pF) T J = T CASE + JT P D 0 25 50 75 100 125 150 175 200 LOAD CAPACITANCE (pF) where: TJ = junction temperature °C Figure 46. Typical Output Rise/Fall Delay (VDD_EXT = Max) TCASE = case temperature (°C) measured at the top center of the package JT = junction-to-top (of package) characterization parameter is the Typical value from Table 57. PD = power dissipation Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A + JA P D where: TA = ambient temperature °C Values of JC are provided for package comparison and PCB design considerations when an external heatsink is required. Rev. B | Page 56 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Note that the thermal characteristics values provided in Table 56 and Table 57 are modeled values. Thermal Diode The ADSP-2148x processors incorporate thermal diode/s to monitor the die temperature. The thermal diode of is a grounded collector, PNP Bipolar Junction Transistor (BJT). The THD_P pin is connected to the emitter and the THD_M pin is connected to the base of the transistor. These pins can be used by an external temperature sensor (such as ADM 1021A or LM86 or others) to read the die temperature of the chip. Table 56. Thermal Characteristics for 100-Lead LQFP_EP Parameter JA JMA JMA JC JT JMT JMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 17.8 15.4 14.6 2.4 0.24 0.37 0.51 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W The technique used by the external temperature sensor is to measure the change in VBE when the thermal diode is operated at two different currents. This is shown in the following equation: kT V BE = n ------ In(N) q Table 57. Thermal Characteristics for 176-Lead LQFP_EP Parameter JA JMA JMA JC JT JMT JMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 16.9 14.6 13.8 2.3 0.21 0.32 0.41 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W where: n = multiplication factor close to 1, depending on process variations k = Boltzmann’s constant T = temperature (°C) q = charge of the electron N = ratio of the two currents The two currents are usually in the range of 10 micro Amperes to 300 micro Amperes for the common temperature sensor chips available. Table 58 contains the thermal diode specifications using the transistor model. Table 58. Thermal Diode Parameters – Transistor Model1 Symbol IFW2 IE nQ3, 4 RT3, 5 Parameter Forward Bias Current Emitter Current Transistor Ideality Series Resistance Min 10 10 1.012 0.12 Typ 1.015 0.2 1 Max 300 300 1.017 0.28 Unit μA μA Ω See Engineer-to-Engineer Note “Using the On-Chip Thermal Diode on Analog Devices Processors” (EE-346). 2 Analog Devices does not recommend operation of the thermal diode under reverse bias. 3 Specified by design characterization. 4 The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: IC = IS × (e qVBE/nqkT –1) where IS = saturation current, q = electronic charge, VBE = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5 The series resistance (RT) can be used for more accurate readings as needed. Rev. B | Page 57 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 100-LQFP_EP LEAD ASSIGNMENT Table 59. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number) Lead Name VDD_INT CLK_CFG1 BOOT_CFG0 VDD_EXT VDD_INT BOOT_CFG1 GND NC NC CLK_CFG0 VDD_INT CLKIN XTAL VDD_EXT VDD_INT VDD_INT RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Lead Name VDD_EXT DPI_P08 DPI_P07 VDD_INT DPI_P09 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DAI_P03 DPI_P14 VDD_INT VDD_INT VDD_INT DAI_P13 DAI_P07 DAI_P19 DAI_P01 DAI_P02 VDD_INT VDD_EXT VDD_INT DAI_P06 DAI_P05 DAI_P09 Lead No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Lead Name Lead No. VDD_INT 76 FLAG0 77 VDD_INT 78 VDD_INT 79 FLAG1 80 FLAG2 81 FLAG3 82 MLBCLK 83 MLBDAT 84 MLBDO 85 VDD_EXT 86 MLBSIG 87 VDD_INT 88 MLBSO 89 TRST 90 EMU 91 TDO 92 VDD_EXT 93 VDD_INT 94 TDI 95 TCK 96 VDD_INT 97 RESET 98 TMS 99 VDD_INT 100 GND 101* MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected to ground (GND). * Pin no. 101 is the GND supply (see Figure 48 and Figure 49) for the processor; this pad must be robustly connected to GND. Rev. B | Lead Name DAI_P10 VDD_INT VDD_EXT DAI_P20 VDD_INT DAI_P08 DAI_P04 DAI_P14 DAI_P18 DAI_P17 DAI_P16 DAI_P15 DAI_P12 VDD_INT DAI_P11 VDD_INT VDD_INT GND THD_M THD_P VDD_THD VDD_INT VDD_INT VDD_INT VDD_INT Page 58 of 68 | March 2013 Lead No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Figure 48 shows the top view of the 100-lead LQFP_EP lead configuration. Figure 49 shows the bottom view of the 100-lead LQFP_EP lead configuration. LEAD 100 LEAD 76 LEAD 1 LEAD 75 LEAD 1 INDICATOR ADSP-2148x 100-LEAD LQFP_EP TOP VIEW LEAD 25 LEAD 51 LEAD 26 LEAD 50 Figure 48. 100-Lead LQFP_EP Lead Configuration (Top View) LEAD 76 LEAD 100 LEAD 75 LEAD 1 ADSP-2148x 100-LEAD LQFP_EP BOTTOM VIEW GND PAD (LEAD 101) LEAD 1 INDICATOR LEAD 51 LEAD 25 LEAD 50 LEAD 26 Figure 49. 100-Lead LQFP_EP Lead Configuration (Bottom View) Rev. B | Page 59 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 176-LEAD LQFP_EP LEAD ASSIGNMENT Table 60. ADSP-21486 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number) Lead Name NC MS0 NC VDD_INT CLK_CFG1 ADDR0 BOOT_CFG0 VDD_EXT ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 BOOT_CFG1 GND ADDR6 ADDR7 NC NC ADDR8 ADDR9 CLK_CFG0 VDD_INT CLKIN XTAL ADDR10 NC VDD_EXT VDD_INT ADDR11 ADDR12 ADDR17 ADDR13 VDD_INT ADDR18 RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Lead Name VDD_EXT DPI_P08 DPI_P07 VDD_INT DPI_P09 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DPI_P14 DAI_P03 NC VDD_EXT NC NC NC NC VDD_INT NC NC VDD_INT NC NC VDD_INT NC WDTRSTO NC VDD_EXT DAI_P07 DAI_P13 DAI_P19 DAI_P01 DAI_P02 VDD_INT NC NC NC NC NC VDD_EXT VDD_INT DAI_P06 DAI_P05 DAI_P09 Lead No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Lead Name DAI_P10 VDD_INT VDD_EXT DAI_P20 VDD_INT DAI_P08 DAI_P14 DAI_P04 DAI_P18 DAI_P17 DAI_P16 DAI_P12 DAI_P15 VDD_INT DAI_P11 VDD_EXT VDD_INT BOOT_CFG2 VDD_INT AMI_ACK GND THD_M THD_P VDD_THD VDD_INT VDD_INT MS1 VDD_INT WDT_CLKO WDT_CLKIN VDD_EXT ADDR23 ADDR22 ADDR21 VDD_INT ADDR20 ADDR19 VDD_EXT ADDR16 ADDR15 VDD_INT ADDR14 AMI_WR AMI_RD Lead No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Lead Name VDD_INT FLAG0 FLAG1 FLAG2 GND FLAG3 GND GND VDD_EXT GND VDD_INT TRST GND EMU DATA0 DATA1 DATA2 DATA3 TDO DATA4 VDD_EXT DATA5 DATA6 VDD_INT DATA7 TDI NC VDD_EXT DATA8 DATA9 DATA10 TCK DATA11 DATA12 DATA14 DATA13 VDD_INT DATA15 NC NC RESET TMS NC VDD_INT GND *No external connection should be made to this pin. Use as NC only. ** Lead no. 177 is the GND supply (see Figure 50 and Figure 51) for the processor; this pad must be robustly connected to GND. Rev. B | Page 60 of 68 | March 2013 Lead No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159* 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177** ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 61. ADSP-21483, ADSP-21487, ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number) Lead Name SDDQM MS0 SDCKE VDD_INT CLK_CFG1 ADDR0 BOOT_CFG0 VDD_EXT ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 BOOT_CFG1 GND ADDR6 ADDR7 NC NC ADDR8 ADDR9 CLK_CFG0 VDD_INT CLKIN XTAL ADDR10 SDA10 VDD_EXT VDD_INT ADDR11 ADDR12 ADDR17 ADDR13 VDD_INT ADDR18 RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Lead Name VDD_EXT DPI_P08 DPI_P07 VDD_INT DPI_P09 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DPI_P14 DAI_P03 NC VDD_EXT NC NC NC NC VDD_INT NC NC VDD_INT NC NC VDD_INT NC WDTRSTO NC VDD_EXT DAI_P07 DAI_P13 DAI_P19 DAI_P01 DAI_P02 VDD_INT NC NC NC NC NC VDD_EXT VDD_INT DAI_P06 DAI_P05 DAI_P09 Lead No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Lead Name VDD_INT FLAG0 FLAG1 FLAG2 GND FLAG3 GND GND VDD_EXT GND VDD_INT TRST GND EMU DATA0 DATA1 DATA2 DATA3 TDO DATA4 VDD_EXT DATA5 DATA6 VDD_INT DATA7 TDI SDCLK VDD_EXT DATA8 DATA9 DATA10 TCK DATA11 DATA12 DATA14 DATA13 VDD_INT DATA15 SDWE SDRAS RESET TMS SDCAS VDD_INT GND * Lead no. 177 is the GND supply (see Figure 50 and Figure 51) for the processor; this pad must be robustly connected to GND. Rev. B | Lead Name DAI_P10 VDD_INT VDD_EXT DAI_P20 VDD_INT DAI_P08 DAI_P14 DAI_P04 DAI_P18 DAI_P17 DAI_P16 DAI_P12 DAI_P15 VDD_INT DAI_P11 VDD_EXT VDD_INT BOOT_CFG2 VDD_INT AMI_ACK GND THD_M THD_P VDD_THD VDD_INT VDD_INT MS1 VDD_INT WDT_CLKO WDT_CLKIN VDD_EXT ADDR23 ADDR22 ADDR21 VDD_INT ADDR20 ADDR19 VDD_EXT ADDR16 ADDR15 VDD_INT ADDR14 AMI_WR AMI_RD Page 61 of 68 | March 2013 Lead No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Lead No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177* ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 62. Automotive Models ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number) Lead Name SDDQM MS0 SDCKE VDD_INT CLK_CFG1 ADDR0 BOOT_CFG0 VDD_EXT ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 BOOT_CFG1 GND ADDR6 ADDR7 NC NC ADDR8 ADDR9 CLK_CFG0 VDD_INT CLKIN XTAL ADDR10 SDA10 VDD_EXT VDD_INT ADDR11 ADDR12 ADDR17 ADDR13 VDD_INT ADDR18 RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Lead Name VDD_EXT DPI_P08 DPI_P07 VDD_INT DPI_P09 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DPI_P14 DAI_P03 NC VDD_EXT NC NC NC NC VDD_INT NC NC VDD_INT NC NC VDD_INT NC WDTRSTO NC VDD_EXT DAI_P07 DAI_P13 DAI_P19 DAI_P01 DAI_P02 VDD_INT NC NC NC NC NC VDD_EXT VDD_INT DAI_P06 DAI_P05 DAI_P09 Lead No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Lead Name VDD_INT FLAG0 FLAG1 FLAG2 MLBCLK FLAG3 MLBDAT MLBDO VDD_EXT MLBSIG VDD_INT TRST MLBSO EMU DATA0 DATA1 DATA2 DATA3 TDO DATA4 VDD_EXT DATA5 DATA6 VDD_INT DATA7 TDI SDCLK VDD_EXT DATA8 DATA9 DATA10 TCK DATA11 DATA12 DATA14 DATA13 VDD_INT DATA15 SDWE SDRAS RESET TMS SDCAS VDD_INT GND * Lead no. 177 is the GND supply (see Figure 50 and Figure 51) for the processor; this pad must be robustly connected to GND. Rev. B | Lead Name DAI_P10 VDD_INT VDD_EXT DAI_P20 VDD_INT DAI_P08 DAI_P14 DAI_P04 DAI_P18 DAI_P17 DAI_P16 DAI_P12 DAI_P15 VDD_INT DAI_P11 VDD_EXT VDD_INT BOOT_CFG2 VDD_INT AMI_ACK GND THD_M THD_P VDD_THD VDD_INT VDD_INT MS1 VDD_INT WDT_CLKO WDT_CLKIN VDD_EXT ADDR23 ADDR22 ADDR21 VDD_INT ADDR20 ADDR19 VDD_EXT ADDR16 ADDR15 VDD_INT ADDR14 AMI_WR AMI_RD Page 62 of 68 | March 2013 Lead No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Lead No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177* ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Figure 50 shows the top view of the 176-lead LQFP_EP lead configuration. Figure 51 shows the bottom view of the 176-lead LQFP_EP lead configuration. LEAD 176 LEAD 133 LEAD 1 LEAD 132 LEAD 1 INDICATOR ADSP-2148x 176-LEAD LQFP_EP TOP VIEW LEAD 44 LEAD 89 LEAD 45 LEAD 88 Figure 50. 176-Lead LQFP_EP Lead Configuration (Top View) LEAD 133 LEAD 176 LEAD 132 LEAD 1 ADSP-2148x 176-LEAD LQFP_EP BOTTOM VIEW GND PAD (LEAD 177) LEAD 1 INDICATOR LEAD 89 LEAD 44 LEAD 88 LEAD 45 Figure 51. 176-Lead LQFP_EP Lead Configuration (Bottom View) Rev. B | Page 63 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 OUTLINE DIMENSIONS The ADSP-2148x processors are available in 100-lead and 176-lead LQFP_EP RoHS compliant packages. 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 14.20 14.00 SQ 13.80 100 SEATING PLANE 76 1 76 75 100 1 75 PIN 1 EXPOSED PAD 1.45 1.40 1.35 0.20 0.15 0.09 0.15 0.10 0.05 0.08 COPLANARITY 7° 3.5° 0° VIEW A ROTATED 90° CCW TOP VIEW BOTTOM VIEW (PINS DOWN) 25 26 51 50 VIEW A 0.50 BSC LEAD PITCH (PINS UP) 51 26 50 0.27 0.22 0.17 Figure 52. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP1] (SW-100-2) Dimensions shown in millimeters For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 58. Rev. B | Page 64 of 68 | 25 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO “SURFACE-MOUNT DESIGN” IN THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD 1 6.00 REF March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 0.75 0.60 0.45 26.20 26.00 SQ 25.80 1.60 MAX 1.00 REF 24.10 24.00 SQ 23.90 21.50 REF 133 176 132 1 SEATING PLANE 133 176 132 1 PIN 1 EXPOSED PAD 1.45 1.40 1.35 0.20 0.15 0.09 0.15 0.10 0.05 0.08 COPLANARITY 7° 3.5° 0° VIEW A BOTTOM VIEW TOP VIEW (PINS DOWN) 44 45 89 88 (PINS UP) 89 VIEW A 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD Figure 53. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP1] (SW-176-2) Dimensions shown in millimeters For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 60. SURFACE-MOUNT DESIGN The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided in the package. Rev. B | Page 65 of 68 | March 2013 44 45 88 ROTATED 90° CCW 1 6.00 REF 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO “SURFACE-MOUNT DESIGN” IN THIS DATA SHEET. ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 AUTOMOTIVE PRODUCTS The following models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers should review the product Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 63 are available for use in automotive applications. Contact your local ADI account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Table 63. Automotive Products Model1 Notes Temperature Range2 RAM AD21486WBSWZ4xx 3 Processor Instruction Rate (Max) Package Description Package Option 400 MHz 100-Lead LQFP_EP SW-100-2 –40°C to +85°C 5 Mbit AD21488WBSWZ4xx –40°C to +85°C 3 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 AD21488WBSWZ4Bxx –40°C to +85°C 3 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 AD21489WBSWZ4xx –40°C to +85°C 5 Mbit 400 MHz 100-Lead LQFP_EP SW-100-2 AD21489WBSWZ4Bxx –40°C to +85°C 5 Mbit 400 MHz 176-Lead LQFP_EP SW-176-2 1 Z =RoHS compliant part. 2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 18 for junction temperature (TJ) specification which is the only temperature specification. 3 This product contains IP from Dolby, DTS and DTLA. Proper software licenses required. Contact ADI for information. ORDERING GUIDE Model1 ADSP-21483KSWZ-2B ADSP-21483KSWZ-3B ADSP-21483KSWZ-3AB ADSP-21483KSWZ-4B ADSP-21486KSWZ-2A ADSP-21486KSWZ-2B ADSP-21486KSWZ-2AB ADSP-21486KSWZ-2BB ADSP-21486KSWZ-3A ADSP-21486KSWZ-3B ADSP-21486KSWZ-3AB ADSP-21486KSWZ-3BB ADSP-21486KSWZ-4A ADSP-21486KSWZ-4AB ADSP-21487KSWZ-2B ADSP-21487KSWZ-2BB ADSP-21487KSWZ-3B ADSP-21487KSWZ-3BB ADSP-21487KSWZ-4B ADSP-21487KSWZ-4BB ADSP-21487KSWZ-5B ADSP-21487KSWZ-5BB Notes 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3, 4 3, 4 Temperature Range2 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C Rev. B | RAM 3 Mbit 3 Mbit 3 Mbit 3 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit Processor Instruction Rate (Max) 300 MHz 350 MHz 350 MHz 400 MHz 300 MHz 300 MHz 300 MHz 300 MHz 350 MHz 350 MHz 350 MHz 350 MHz 400 MHz 400 MHz 300 MHz 300 MHz 350 MHz 350 MHz 400 MHz 400 MHz 450 MHz 450 MHz Page 66 of 68 | March 2013 Package Description 176-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP Package Option SW-176-2 SW-176-2 SW-100-2 SW-176-2 SW-100-2 SW-176-2 SW-100-2 SW-176-2 SW-100-2 SW-176-2 SW-100-2 SW-176-2 SW-100-2 SW-100-2 SW-176-2 SW-176-2 SW-176-2 SW-176-2 SW-176-2 SW-176-2 SW-176-2 SW-176-2 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Model1 ADSP-21488BSWZ-3A ADSP-21488KSWZ-3A ADSP-21488KSWZ-3A1 ADSP-21488KSWZ-3B ADSP-21488BSWZ-3B ADSP-21488KSWZ-4A ADSP-21488BSWZ-4A ADSP-21488KSWZ-4B ADSP-21488BSWZ-4B ADSP-21488KSWZ-4B1 ADSP-21489KSWZ-3A ADSP-21489BSWZ-3A ADSP-21489KSWZ-3B ADSP-21489BSWZ-3B ADSP-21489KSWZ-4A ADSP-21489BSWZ-4A ADSP-21489KSWZ-4B ADSP-21489BSWZ-4B ADSP-21489KSWZ-5B Notes 5 5 4 Temperature Range2 –40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C RAM 3 Mbit 3 Mbit 3 Mbit 3 Mbit 3 Mbit 3 Mbit 3 Mbit 3 Mbit 3 Mbit 3 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit 5 Mbit Processor Instruction Rate (Max) 350 MHz 350 MHz 350 MHz 350 MHz 350 MHz 400 MHz 400 MHz 400 MHz 400 MHz 400 MHz 350 MHz 350 MHz 350 MHz 350 MHz 400 MHz 400 MHz 400 MHz 400 MHz 450 MHz 1 Package Description 100-Lead LQFP_EP 100-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 100-Lead LQFP_EP 100-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP 176-Lead LQFP_EP Package Option SW-100-2 SW-100-2 SW-100-2 SW-176-2 SW-176-2 SW-100-2 SW-100-2 SW-176-2 SW-176-2 SW-176-2 SW-100-2 SW-100-2 SW-176-2 SW-176-2 SW-100-2 SW-100-2 SW-176-2 SW-176-2 SW-176-2 Z = RoHS compliant part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 18 for junction temperature (TJ) specification, which is the only temperature specification. 3 The ADSP-21483, ADSP-21486, and ADSP-21487 models are available with factory programmed ROM including the latest multichannel audio decoding and post-processing algorithms from Dolby Labs and DTS. ROM contents may vary depending on chip version and silicon revision. Please visit www.analog.com for complete information. 4 See Engineer-to-Engineer Note “Static Voltage Scaling for ADSP-2148x Processors” (EE-357) for operating ADSP-2148x processors at 450 MHz. 5 This product contains a –140 dB sample rate converter. 2 Rev. B | Page 67 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09018-0-3/13(B) Rev. B | Page 68 of 68 | March 2013