ETC W184H

W184
Six Output Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable input to output frequency
• Six 1.25%, 3.75%, or 0% down or center spread outputs
• One non-Spread reference output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 24-pin SSOP (Shrunk Small Outline
Package)
• Outputs may be selectively disabled
SS%
W184
Output
0
Fin ≥ Fout ≥ Fin – 1.25%
Fin + 0.625% ≥ Fin≥ –
0.625%
1
Fin ≥ Fout ≥ Fin – 3.75%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
0
0
8 MHz ≤ FIN ≤ 10 MHz
0
1
10 MHz ≤ FIN ≤ 15 MHz
1
0
15 MHz ≤ FIN ≤ 18 MHz
1
1
18 MHz ≤ FIN ≤ 28 MHz
Key Specifications
Supply Voltages: ...........................................VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz ≤ Fin ≤ 28 MHz
Crystal Reference Range.................... 8 MHz ≤ Fin ≤ 28 MHz
W184-5
Output
Table 3. Output Enable
EN1
EN2
Selectable Spread Percentage: ....................1.25% or 3.75%
0
0
Low
Low
Output Duty Cycle: ............................... 40/60% (worst case)
0
1
Low
Active
Output Rise and Fall Time: .................................. 5 ns (max.)
1
0
Active
Low
1
1
Active
Active
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Simplified Block Diagram
CLK0:4
CLK5
Pin Configuration
3.3 or 5.0V
SSOP
REFOUT
FS2
X1
X2
GND
X1
X2
W184
Spread Spectrum
Outputs
(EMI suppressed)
SS%
EN2
GND
3.3 or 5.0V
Oscillator or
Reference Input
W184
CLK0
VDD
CLK1
CLK2
W184/W184-5
XTAL
Input
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
11
16
15
14
12
13
9
10
SSON#
RESET
FS1
VDD
VDD
NC
EN1
CLK5
VDD
CLK4
GND
CLK3
Spread Spectrum
Outputs
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-07157 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 25, 2001
W184
Pin Definitions
Pin Name
CLK0:5
Pin No.
Pin
Type
Pin Description
9, 11, 12, 13,
15, 17
O
Modulated Frequency Outputs: Frequency modulated copies of the unmodulated input clock (SSON# asserted).
CLKIN or X1
3
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
NC or X2
4
I
Crystal Connection: If using an external reference, this pin must be left unconnected.
SS%
6
I
Modulation Width Selection: When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistors.
Reset
23
I
Modulation Profile Restart: A rising edge on this input restarts the modulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
REFOUT
14
O
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
18, 7
I
Output Enable Select Pins: These pins control the activity of specific output
buffers. Set them to disable unused outputs using Table 3 as a guide.
24
I
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
FS1:2
22, 2
I
Frequency Selection Bit 1 and 2: These pins select the frequency of operation. Refer to Table 1. These pins have internal pull-up resistors.
VDD
10, 16, 20, 21
P
Power Connection: Connected to 3.3V or 5V power supply.
EN1:2
SSON#
Document #: 38-07157 Rev. **
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W184
Overview
The W184 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a lowfrequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation.
Functional Description
The W184 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W184 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum process has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage may be selected to 1.25%
or 3.75% (see Table 1).
A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
VDD
Clock Input
Reference Input
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Σ
VCO
Post
Dividers
CLKOUT
(EMI suppressed)
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Document #: 38-07157 Rev. **
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W184
Spread Spectrum Frequency Timing
Generation
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Typical Clock
Amplitude (dB)
Amplitude (dB)
SSFTG
Spread
Spectrum
Enabled
NonSpread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX.
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07157 Rev. **
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W184
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
TA
Operating Temperature
0 to +70
°C
PD
Power Dissipation
0.5
W
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
Description
IDD
Supply Current
tON
Power Up Time
Test Condition
Min.
Typ.
Max.
Unit
18
32
mA
5
ms
First locked clock cycle after Power
Good
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
IIL
Input Low Current
Note 1
IIH
Input High Current
Note 1
IOL
Output Low Current
@ 0.4V, VDD = 3.3V
15
mA
IOH
Output High Current
@ 2.4V, VDD = 3.3V
15
mA
0.8
2.4
V
V
0.4
2.4
V
V
µA
–50
50
µA
CI
Input Capacitance
All pins except CLKIN
CI
Input Capacitance
CLKIN pin only
RP
Input Pull-Up Resistor
500
kΩ
ZOUT
Clock Output Impedance
25
Ω
6
7
pF
10
pF
Note:
1. Inputs FS1:2, SS% have a pull-up resistor; Input SSON# has a pull-down resistor.
Document #: 38-07157 Rev. **
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W184
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
30
50
mA
5
ms
0.15VDD
V
IDD
Supply Current
tON
Power Up Time
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
IIL
Input Low Current
Note 2
IIH
Input High Current
Note 2
IOL
Output Low Current
@ 0.4V, VDD = 5V
24
mA
IOH
Output High Current
@ 2.4V, VDD = 5V
24
mA
CI
Input Capacitance
All pins except CLKIN
CI
Input Capacitance
CLKIN pin only
RP
Input Pull-Up Resistor
500
kΩ
ZOUT
Clock Output Impedance
25
Ω
First locked clock cycle after
Power Good
0.7VDD
V
0.4
2.4
V
V
µA
–50
50
6
µA
7
pF
10
pF
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
fIN
Input Frequency
Input Clock
8
28
MHz
fOUT
Output Frequency
Spread Off
8
28
MHz
tR
Output Rise Time
VDD, 15-pF load 0.8V–2.4V
2
5
ns
tF
Output Fall Time
VDD, 15-pF load 2.4V–0.8V
2
5
ns
tOD
Output Duty Cycle
15-pF load
40
60
%
tID
Input Duty Cycle
40
60
%
tJCYC
Jitter, Cycle-to-Cycle
300
ps
EMIRED
Harmonic Reduction
tSK
Output to Output Skew
250
fout = 40 MHz, third harmonic
measured, reference board,
15-pF load
8
dB
200
ps
Note:
2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
Document #: 38-07157 Rev. **
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W184
Application Information
placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
R1
Clock Output
24
Logic Input
2
23
Logic Input
Reference Input
3
22
Logic Input
4
5
6
7
8
9
10
11
12
21
20
19
18
17
16
15
14
13
XTAL connection or NC
Logic Input
Logic Input
Clock Output
Clock Output
Clock Output
R1
R1
R1
W184
1
Logic Input
C1
0.1 µF
NC
Logic Input
Clock Output
R1
C1
0.1 µF
Clock Output
R1
C1
0.1 µF
Clock Output
R1
C1
0.1 µF
3.3 or 5V System Supply
FB
C2
10-µF Tantalum
Figure 4. Recommended Circuit Configuration
Ordering Information
Ordering Code
Package
Name
W184
W184-5
Document #: 38-07157 Rev. **
H
Package Type
24-Pin SSOP (209-mil)
Page 7 of 9
W184
Package Diagram
24-Pin Shrink Small Outline Package (SSOP, 209 mils)
Document #: 38-07157 Rev. **
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© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W184
Document Title: W184 Six Output Peak Reducing EMI Solution
Document Number: 38-07157
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110267
12/15/01
SZV
Document #: 38-07157 Rev. **
Description of Change
Change from Spec number: 38-00797 to 38-07157
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