W185 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Six 1.25%, 3.75%, or 0% down or center spread outputs • One non-Spread output of Reference input • Integrated loop filter components • Operates with a 3.3V or 5V supply • Low power CMOS design • Available in 24-pin SSOP (Shrink Small Outline Package) • Outputs may be selectively disabled SS% W185 Output W185-5 Output 0 Fin ≥ Fout ≥ Fin – 1.25% Fin + 0.625% ≥ Fin≥ – 0.625% 1 Fin ≥ Fout ≥ Fin – 3.75% Fin + 1.875% ≥ Fin≥ –1.875% Table 2. Frequency Range Selection FS2 FS1 Frequency Range 0 0 28 MHz ≤ FIN ≤ 38 MHz 0 1 38 MHz ≤ FIN ≤ 48 MHz 1 0 46 MHz ≤ FIN ≤ 60 MHz 1 1 58 MHz ≤ FIN ≤ 75 MHz Key Specifications Supply Voltages: ........................................... VDD = 3.3V±5% or VDD = 5V±10% Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz Crystal Reference Range:................. 28 MHz ≤ Fin ≤ 40 MHz Table 3. Output Enable EN1 EN2 Selectable Spread Percentage: ....................1.25% or 3.75% 0 0 Low Low Output Duty Cycle: ............................... 40/60% (worst case) 0 1 Low Active Output Rise and Fall Time: .................................. 5 ns (max.) 1 0 Active Low 1 1 Active Active Cycle to Cycle Jitter: ....................................... 300 ps (max.) Simplified Block Diagram CLK0:4 Pin Configuration 3.3V or 5.0V SSOP 40MHz max. X2 W185 Spread Spectrum Output (EMI suppressed) W185 SSON# RESET FS1 VDD VDD 19 18 17 16 NC 11 15 14 CLK4 GND 12 13 CLK3 1 2 3 4 5 SS% EN2 GND 6 3.3V or 5.0V Oscillator or Reference Input 24 23 22 21 20 REFOUT FS2 X1 X2 GND CLK0 VDD CLK1 CLK2 W185/W185-5 X1 XTAL Input CLK5 7 8 9 10 EN1 CLK5 VDD Spread Spectrum Output (EMI suppressed) PREMIS is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 25, 2000, rev. *A W185 Pin Definitions Pin Name Pin No. Pin Type Pin Description 9, 11, 12, 13, 15, 17 O Modulated Frequency Outputs: Frequency modulated copies of the unmodulated input clock (SSON# asserted). CLKIN or X1 3 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 4 I Crystal Connection: If using an external reference, this pin must be left unconnected. SS% 6 I Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. Reset 23 I Modulation Profile Restart: A rising edge on this input restarts the modulation pattern at the beginning of its defined path. This pin has an internal pull-down resistor. REFOUT 1 O Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. 18, 7 I Output Enable Select Pins: These pins control the activity of specific output buffers. See Table 3 on page 1. 24 I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. FS1:2 22, 2 I Frequency Selection Bit 1 and 2: These pins select the frequency of operation. Refer to Table 1. These pins have internal pull-up resistors. VDD 10, 16, 20, 21 P Power Connection: Connected to 3.3V or 5V power supply. GND 5, 8, 14 G Ground Connection: This should be connected to the common ground plane. 19 NC CLK0:5 EN1:2 SSON# NC No Connect: This pin should be left floating. 2 W185 times the reference frequency. (Note: For the W184 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Overview The W185 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Functional Description Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage may be selected as either 1.25% or 3.75% (see Table 1). The W185 uses a Phase-Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided. VDD Clock Input Reference Input Freq. Divider Q Phase Detector Σ Charge Pump VCO Modulating Waveform Feedback Divider P PLL GND Figure 1. Functional Block Diagram 3 Post Dividers CLKOUT (EMI suppressed) W185 Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. Spread Spectrum Frequency Timing Generation The output clock is modulated with a waveform depicted in )LJXUH . This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. )LJXUH details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in )LJXUH . As shown in )LJXUH , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) EMI Reduction Typical Clock Amplitude (dB) Amplitude (dB) SSFTG Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) Down Spread Frequency Span (MHz) Center Spread Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN. Figure 3. Typical Modulation Profile 4 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX. W185 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5% Parameter Description Test Condition Min. Typ. Max. Unit 18 32 mA 5 ms IDD Supply Current tON Power Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 1 IIH Input High Current Note 1 IOL Output Low Current @ 0.4V, VDD = 3.3V 15 mA IOH Output High Current @ 2.4V, VDD = 3.3V 15 mA CI Input Capacitance RP Input Pull-Up Resistor 500 kΩ ZOUT Clock Output Impedance 25 Ω First locked clock cycle after Power Good 0.8 2.4 0.4 2.4 µA 50 7 5 V V –50 Note: 1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor. V V µA pF W185 DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description IDD Supply Current tON Power Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage Test Condition Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V First locked clock cycle after Power Good 0.7VDD V 0.4 2.4 V V µA IIL Input Low Current Note 1 IIH Input High Current Note 1 –100 IOL Output Low Current IOH Output High Current @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V CI Input Capacitance RP Input Pull-Up Resistor 500 kΩ ZOUT Clock Output Impedance 25 Ω 50 µA 24 mA 24 mA 7 pF AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10% Symbol Parameter Test Condition Min. Typ. Max. Unit fOSC Internal Xtal Oscillator Frequency Xtal connected to X1, X2 28 40 MHz fIN Input Frequency External reference 28 75 MHz fOUT Output Frequency Spread Off, FS2:1 per Table 2 28 75 MHz tR Output Rise Time 15-pF load 0.8V–2.4V 2 5 ns tF Output Fall Time 15-pF load 2.4 –0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps EMIRED Harmonic Reduction tSK Output to Output Skew 250 fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 dB 300 6 ps W185 creased trace inductance will negate its decoupling capability. The 10-µF decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Application Information Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. Recommended Board Layout VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-µF decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the in- Figure 5 shows a recommended 2-layer board layout. R Reference Output 24 2 23 XTAL Connection or Reference Input 3 22 4 5 6 7 8 9 10 11 12 21 20 19 18 17 16 15 14 13 XTAL Connection or NC R Clock Output R Clock Output Clock Output R W185 1 Logic Input C3 0.1 µF NC C2 0.1 µF Clock Output R C4 0.1 µF Clock Output R Clock Output R C1 0.1 µF 3.3V or 5V System Supply FB C5 10 µF Tantalum Figure 4. Recommended Circuit Configuration C1....C4 = High frequency supply decoupling capacitor (0.1-µF recommended). Xtal Connection or Reference Input C2 Xtal Connection or NC G C3 G G C5 = Common supply low frequency decoupling capacitor (10-µF tantalum recommended). R = Match value to line impedance FB = Ferrite Bead G = Via To GND Plane R G Clock Output R C4 C1 R G G R G G Power Supply Input (3.3V or 5V) FB C5 Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information Ordering Code W185 W185-5 Package Name H Package Type 24-Pin SSOP (209-mil) Document #: 38-00809-A 7 W185 Package Diagram 24-Pin Shrink Small Outline Package (SSOP, 209-mil) 8 7 6 5 4 3 2 REV . D/2 1.00 E 2.36 DIA. PIN 1.00 DIA. 3 2 1 H + 0.20 M E M E/2 INITIAL RELEASE PER DCN#A33907. 01 REVISED PER DCN#D20214. 02 REVISED PER DCN#D20760. 03 REVISED PER DCN#D21151. 04 REVISED PER DCN#D22219. 05 REVISED PER DCN#P60056. I PP b1 OR IG INA TO R HJC YMK E EBA EBA EBA J.B.C. c1 S- P N D 8. 6 b TOP VIEW BOTTOM VIEW + 0.12 e M T E D S b 8 C A2 A 3 MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES). DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982. 3. "T" IS A REFERENCE DATUM. 4. "D" & "E" ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE, MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. 5. 0.076 A1 -D- C 7 SEATING PLANE 4 SEE DETAIL "A" -E- 6. 4 7. 8. .235 MIN SIDE VIEW END VIEW B 9. 0° MIN. R G 0.25 BSC DECIMAL XX± XXX± XXXX± C OC L 5 G SEATING PLANE A FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.07mm AT LEAST MATERIAL CONDITION. CONTROLLING DIMENSION: MILLIMETERS. L1 ANGULAR ± P RO JEC TION D ATE DR AW N MA TE RIAL 6 /1 3 19 91 H. BAUTISTA 6 /1 3 19 91 A1 6 /1 3 19 91 S CAL E RE L EA S ED DO NOT SCALE DRAWING 6 5 6 H.J. CHOI 4 5 PACKAGE OUTLINE, 5.30mm (.209") BODY, SSOP 6 /1 3 19 91 M. BANGLOY E NG 'R S IZ E RE V. 32289 05 SHE E T 2 3 A D WG . N O. 3 4 E X CE LL EN CE IN S EM IC ON DUCTO R A S SE MB L Y A ND TE ST TITL E M. CHAVEZ CH ECK E D FINIS H 7 B An a m In du stria l Co ., LT D. Am kor/A na m P ilip in as, INC. Se o ul, K ore a Ma nil a, Ph ili pp ine s Am kor E le ctron ics Am kor E le ctr on ics Ir ving , TX Cha nd le r, AZ A PP RO V AL S DETAIL 'A' 7 C 10. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS. 11. THIS PACKAGE OUTLINE DRAWING COMPLIES WITH JEDEC SPECIFICATION NO. MO-150 FOR THE LEAD COUNTS SHOWN GAUGE PLANE PARTING LINE 10. 1. 2. -C-T- BASE METAL SECTION G-G NOTES: 12-16° 8 06/13 1991 11/05 1992 11/08 1993 04/26 1994 06/19 1995 03/19 1996 WITH LEAD FINISH c D 8 DA TE 00 I NE HI L 1.00 1 DE S CRIPTIO N 1 of 2 1 2 1 THIS TABLE IN MILLIMETERS S Y M B O L E A A1 A2 b b1 c c1 D E D e H L L1 N OC R COMMON DIMENSIONS NOM. MIN. MAX. 1.86 1.73 0.05 0.13 1.68 1.73 0.25 0.25 0.30 0.09 0.09 0.15 SEE VARIATIONS 5.20 5.30 0.65 BSC 7.65 7.80 0.63 0.75 1.25 REF. SEE VARIATIONS 0° 0.09 4° 0.15 1.99 0.21 1.78 0.38 0.33 0.20 0.16 N O T E 6 N NOTE VARIATIONS MIN. 4 D NOM. MAX. AA AB AC AD AE AF 6.07 6.07 7.07 8.07 10.07 10.07 6.20 6.20 7.20 8.20 10.20 10.20 6.33 6.33 7.33 8.33 10.33 10.33 E 14 16 20 24 28 30 5.38 8,10 10 10 10 4 4 7.90 0.95 5 VARIATION AF 6 IS DESIGNED BUT NOT TOOLED D 8° C C THIS TABLE IN INCHES S Y M B O L A A1 A2 b b1 c c1 D E B e H L L1 N A C O R COMMON DIMENSIONS NOM. MIN. MAX. .068 .073 .002 .005 .066 .068 .010 .010 .012 .004 .004 .006 SEE VARIATIONS .205 .209 .0256 BSC .301 .307 .025 .030 .049 REF. SEE VARIATIONS 0° .004 4° .006 .078 .008 .070 .015 .013 .008 .006 N O T E .212 8,10 10 10 10 4 4 .311 .037 5 6 N NOTE VARIATIONS MIN. 4 D NOM. MAX. AA AB AC AD AE AF .239 .239 .278 .318 .397 .397 .244 .244 .284 .323 .402 .402 .249 .249 .289 .328 .407 .407 14 16 20 24 28 30 B TITLE PACKAGE OUTLINE, 5.30mm (.209") BODY, SSOP 6 8° SIZE 7 6 5 4 3 A REV. 32289 A1 SCALE 8 DWG. NO. 8/1 05 SHEET 2 2 of 2 1 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.