W532 Frequency Multiplying, Peak Reducing EMI Solution Features Table 1. Output Frequency Range Selection • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable frequency range and multiplication factor • Single 1.25% or 5% center spread output • Integrated loop filter components • Operates with a 3.3V or 5V supply • Low power CMOS design • Available in 16-pin SOIC Key Specifications OR2 OR1 Output Range (Multiplication Factor Selection) 0 0 reserved 0 1 15 MHz ≤ FIN ≤ 30 MHz 1 0 30 MHz ≤ FIN ≤ 60 MHz 1 1 60 MHz ≤ FIN ≤ 120 MHz Table 2. Modulation Width Selection MW Output 0 Favg + 0.625% ≥ Fout ≥ Favg – 0.625% 1 Favg + 2.5% ≥ Fout ≥ Favg – 2.5% Supply Voltages: ........................................VDD = 3.3V ±0.3V or VDD = 5V ±10% Frequency Range: .........................15 MHz ≤ Fout ≤ 120 MHz Table 3. Input Frequency Range Selection Cycle to Cycle Jitter: ......................................... 150 ps (typ.) Output Duty Cycle: ............................... 40/60% (worst case) IR2 IR1 Input Range Output Rise and Fall Time ................................... 5 ns (max.) 0 0 reserved Simplified Block Diagram 0 1 15 MHz ≤ FIN ≤ 30 MHz 1 0 30 MHz ≤ FIN ≤ 60 MHz 1 1 60 MHz ≤ FIN ≤ 120 MHz Pin Configuration 3.3V or 5.0V SOIC X1 XTAL Input X2 W532 3.3V or 5.0V Oscillator or Reference Input 1 2 3 4 5 16 15 14 13 12 VDD GND IR1^ IR2^ AGND ^OR2 *SSON# 6 11 GND 7 10 9 VDD W532 Spread Spectrum Output (EMI suppressed) X1 X2 AVDD *OR1 NC 8 SSOUT MW* Notes: 1. ^ pins have internal pull-up 2. * pins have internal pull-down X1 W532 Spread Spectrum Output (EMI suppressed) PREMIS is a trademark of Cypress Semiconductor. Cypress Semiconductor Corporation Document #: 38-07253 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 28, 2002 W532 Pin Definitions Pin No. Pin Type SSOUT 12 O Output Modulated Frequency: Frequency modulated signal. Frequency of the output is selected as shown in Table 1. CLKIN or X1 1 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 2 I Crystal Connection: Input connection for an external crystal. If using an external reference signal, this pin must be left unconnected. SSON# 8 I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. MW 9 I Modulation Width Selection: When Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal (see Table 2). IR1:2 14, 13 I Reference Frequency Selector: Logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. OR1:2 4, 7 I Output Frequency Selection Bits: These pins select the frequency of operation for the output. Refer to Table 1. OR1: DOWN - OR2: UP. VDD 3, 10, 16 P Power Connection: Connected to 3.3V or 5V power supply. GND 6, 11, 15 G Ground Connection: Connect all ground pins to the common ground plane. 5 NC Pin Name NC Document #: 38-07253 Rev. *A Pin Description No Connect: Leave this pin floating. Page 2 of 8 W532 Overview The W532 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. Functional Description The W532 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (IR1:2, OR1:2 pins), the frequency range can be set (see Table 1 and Table 3). Spreading percentage is set with pin MW as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump Σ VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Conceptual Block Diagram Document #: 38-07253 Rev. *A Page 3 of 8 W532 Spread Spectrum Frequency Timing Generation Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter ± XMOD% in the frequency spread selection table. The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX – XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. SSON# Pin An internal pull-down resistor defaults the chip into spread spectrum mode. When the SSON# pin is asserted (active LOW) the spreading feature is enabled. Spreading feature is disabled when SSON# is set HIGH (VDD). 5dB/div SSFTG Amplitude (dB) Typical Clock 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 100% 80% 60% 40% 20% 0% –20% –40% –60% –80% –100% 10% Frequency Shift Figure 2. Typical Clock and SSFTG Comparison Time Figure 3. Modulation Waveform Profile Document #: 38-07253 Rev. *A Page 4 of 8 W532 Absolute Maximum Ratings[3] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit V VDD, VIN Voltage on any Pin with Respect to GND –0.5 to +7.0 TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 or –40 to +85 °C TB Ambient Temperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W DC Electrical Characteristics: 0°C < TA < 70°C or –40°C to +85°C, VDD = 3.3V ±0.3V Parameter Description Test Condition Min. Typ. Max. Unit 18 32 mA 5 ms 0.8 V IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 4 IIH Input High Current Note 4 IOL Output Low Current @ 0.4V, VDD = 3.3V 15 mA IOH Output High Current @ 2.4V, VDD = 3.3V 15 mA CI Input Capacitance RP Input Pull-Up Resistor 150 kΩ ZOUT Clock Output Impedance 25 Ω First locked clock cycle after Power Good 2.4 V 0.4 V 2.4 V –50 µA 50 7 µA pF Note: 3. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 4. Inputs OR2 and IR1:2 have a pull-up resistor, Inputs SSON# OR1 and MW have a pull-down resistor. Document #: 38-07253 Rev. *A Page 5 of 8 W532 DC Electrical Characteristics: 0°C < TA < 70°C or –40°C to +85°C, VDD = 5V ±10% Parameter Description Test Condition Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 4 IIH Input High Current Note 4 IOL Output Low Current @ 0.4V, VDD = 5V 24 mA IOH Output High Current @ 2.4V, VDD = 5V 24 mA CI Input Capacitance RP Input Pull-Up Resistor 150 kΩ ZOUT Clock Output Impedance 25 Ω First locked clock cycle after Power Good 0.7VDD V 0.4 2.4 V V µA –50 50 7 µA pF AC Electrical Characteristics: TA = 0°C to +70°C or –40°C to +85°C, VDD = 3.3V ±0.3V or 5V±10% Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 14 120 MHz fOUT Output Frequency Spread Off 13 120 MHz tR Output Rise Time VDD, 15-pF load, 0.8–2.4V 2 5 ns tF Output Fall Time VDD, 15-pF load, 2.4–0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps 150 Ordering Information Ordering Code Package Name Package Type Temperature Range W532 G 16-Pin Plastic SOIC (300-mil) Commercial (0° – 70°) W532 GI 16-Pin Plastic SOIC (300-mil) Industrial (–40° – 85°) Document #: 38-07253 Rev. *A Page 6 of 8 W532 Package Diagram 16-Pin Small Outline Integrated Circuit (SOIC, 300-mil) Document #: 38-07253 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W532 Document Title: W532 Frequency Multiplying, Peak Reducing EMI Solution Document Number: 38-07253 ECN NO. Issue Date Orig. of Change ** 110518 01/07/02 SZV Change from Spec number: 38-01061 to 38-07253 *A 122695 12/28/02 RBI Add power up requirements to maximum ratings information. REV. Document #: 38-07253 Rev. *A Description of Change Page 8 of 8