SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product FREQUENCY TABLE (MHz) PRODUCT FEATURES ® ® Supports Pentium , Pentium II, M2,& K6 CPUs. Designed to support SiS5591/2 and MVP3 logic. 4 CPU & 2 (Sync./ Async.) AGP clocks Up to 12 SDRAM clocks for 3 DIMMs. 6 (Sync./ Async.) PCI clocks. Optional common or mixed supply mode: (VDD = VDDPCI = VDDCPU = 3.3V) or (VDD = VDDPCI = 3.3V, VDDCPU = 2.5V) < 250ps skew among CPU or SDRAM clocks. < 250ps skew among PCI clocks. 2 I C 2-Wire serial interface Programmable registers featuring: - Jumperless frequency selection - enable/disable each output pin - mode as tri-state, test, or normal Power Management Capability. 48 MHz for USB support Internal Crystal Load Capacitors. 48-pin SSOP package Spread Spectrum Technology for EMI reduction SD S2 S1 S0 CPU PCI AGP SDRAM 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 60 66.8 50 75 75 83.3 90 100 30 33.4 25 37.5 32 32 30 33.3 60 66.8 50 64 64 64 60 66.6 60 66.8 50 64 64 64 60 66.6 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 60 66.8 50 75 75 83.3 90 100 30 33.4 25 37.5 32 32 30 33.3 60 66.8 50 64 64 64 60 66.6 60 66.8 50 75 75 83.3 90 100 BLOCK DIAGRAM REF XIN REF0 REF1 XOUT VDDCPU SD_Sel# CS# S2 S1 dly PLL1 S0 MODE SDATA SCLK B 4 B 6 B B 2 12 CPU (0:3) PCI (F, 0:4) AGP (1:2) SDRAM(0:11) 48 MHz PLL2 CONNECTION DIAGRAM VDD REF0/CS# VSS XIN XOUT VDDPCI PCI_F/S1 FCI0/S2 VSS PCI1 PCI2 PCI3 PCI4 VDDPCI AGP1 VSS SDRAM11 SDRAM10 VDDSD2 SDRAM9 SDRAM8 VSS SDATA SCLK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD AGP2 REF1/SD_SEL# VSS CPU0 CPU1 VDDCPU CPU2 CPU3 VSS SDRAM0 SDRAM1 VDDSD0 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDSD1 SDRAM6 SDRAM7 VSS 48MHZ/S0 24 MHZ/MODE 24 MHz INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 1 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product PIN DESCRIPTION Pin Number Pin Name PWR I/O 4 Xin VDD I 5 Xout PCI_F VDD VDDPCI O O S1 PCI0 VDD VDDPCI I O S2 VDD I 10, 11, 12, 13 15, 47 44, 43, 41, 40 PCI (1:4) AGP(1:2) CPU(0:3) VDDPCI VDD VDDCPU O O O 38, 37, 35,34, 32, 31, 29, 28, 21, 20, 18, 17 SDRAM(0:11) VDDSD(0:2) O REF0 VDD O IF MODE=1 this pin becomes a buffered reference of the crystal. CS# VDD I SD_Sel# VDD I REF1 48 MHz VDD VDDSD1 O I/O If MODE=0 then this pin controls CPU clock outputs by enabling (set to a logic 1) or disabling (set to a logic 0). This is a bidirectional pin. During power up, this pin is an input “SD_Sel” for selecting the SDRAM frequency (see page1, and app note on page 12). If SD_Sel# is high (default), the SDRAM frequency is same as CPU. If it is low, the SDRAM frequency is same as AGP. When the power reaches the rail, (see fig.1, page 3), This pin becomes a 14.318 MHz reference clock output. This is a bidirectional pin. During power up, this pin is an input for frequency selection S0 control bit (see page1, and app note on page 12) and sets the bit to its initial state. After a fixed period of time (see S0 24 MHz VDDSD1 I* O fig.1, page 3), this pin becomes a 48 MHz frequency clock. This is a bidirectional pin. During power up, this pin is an input that enables (0) or disables (1) the power management shared pin (2, (see app note on page 12) and sets the bit to its initial state). After MODE VDD I 23 24 3, 9, 16, 22, 27, 33, 39, 45 1,48 SDATA SCLK VSS VDD VDD - I I P a fixed period of time (see fig.1, page 3), this pin becomes a 24 MHz frequency clock. 2 Serial Data for I C 2-wire control interface. Has internal pull-up. 2 Serial Clock of I C 2-wire control interface. Has internal pull-up. Ground pins. VDD - P Power supply pins for analog circuit, core logic and reference clock buffers, and AGP clocks. 6, 14 36, 30, 19 42 VDDPCI VDDSD0,1,2 VDDCPU - P P P 3.3 volt power for PCI clocks. 3.3 volt power for SDRAM clocks. 3.3 or 2.5 volt power for CPU clocks. 7 8 TYPE Description These pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (Typ. 14.318 MHz). Xin may also serve as input for an externally generated reference signal. in which case Pin 5 is left unconnected This is a bidirectional pin. During power up, this pin is an input for frequency selection S1 control bit (see page1, and app note on page 12) and sets the bit to its initial state. When the power reaches the rail (see fig.1, page 3), this pin becomes a low skew PCI clock output. This is a bidirectional pin. During power up, this pin is an input for frequency selection S2 control bit (see page1, and app note on page 12) and sets the bit to its initial state. When the power reaches the rail( see fig.1, page 3), this pin becomes a low skew PCI clock output. Low skew PCI output clocks. Powered by VDDPCI Accelerated Graphics Port output clocks. See frequency table page1. Low skew (<250 pS) clock outputs for host frequencies such as CPU, AGP, Chipset, Cache. Powered by VDDCPU. Synchronous DRAM DIM clocks. They are powered by VDDSD0 thru VDDSD2. See VDDSD power pin description. 2 46 26 25 *NOTE: Require external 10K ohm pull-up resistors or 10K ohm pull down resistors for programming. µF) should be placed as close as possible to each power (Vdd) pin. If these bypass A bypass capacitor (0.1µ capacitors are not close to the pins their high frequency filtering characteristic will be canceled by the lead inductances of the traces. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 2 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product SPECTRUM SPREAD CLOCKING Center Spread Amplitude (dB) Without Spectrum Spread With Spectrum Spread Center F Min Frequency(MHz) F Max Spectrum Analysis SPECTRUM SPREADING SELECTION TABLE Rested Frequency in MHz desired (actual) 50 (50.11) 60 (60.00) 66.6 (66.82) 75 (75.00) 83.3 (83.52) 100 (100.23) Center Spreading F Min 49.62 59.75 66.39 74.78 83.16 99.59 SSW=1 F Center F Max 49.97 50.32 60.10 60.45 66.74 67.09 75.13 75.48 83.51 83.86 99.94 100.29 Spread +/- 0.70% +/- 0.58% +/- 0.52% +/- 0.47% +/- 0.42% +/- 0.35% INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 F Min 49.28 59.41 66.05 74.43 82.82 99.24 F Center 49.97 60.10 66.74 75.13 83.51 99.94 SSW=0 F Max 50.66 60.79 67.43 75.83 84.20 100.64 Rev.1.7 Spread +/- 1.38% +/- 1.15% +/- 1.04% +/- 0.93% +/- 0.83% +/- 0.70% 8/14/98 Page 3 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product POWER UP BIDIRECTIONAL PIN TIMING VDD Power Supply PCI_F / S1 PCI0 / S2 48 MHz / S0 24 MHz / MODE Ref1 / SD_Sel# toggle , outputs Hi-Z (tristate), inputs Fig.1 POWER MANAGEMENT FUNCTIONS When MODE=0, pin 2 is an input CS# (CPU_STOP#), (when MODE=1, this functions are not available). A particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. The IMISG745 CPU(0:3) clocks may be disabled according to the following table in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. The CPU clocks transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# CPU OTHER CLKs XTAL & VCOs 0 LOW RUNNING RUNNING 1 RUNNING RUNNING RUNNING 2 Please note that all clocks can be asynchronously enabled or stopped via the 2-wire I C control interface. In this case all clocks are stopped in the low state. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 4 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product 2-WIRE I2C CONTROL INTERFACE The 2-wire control interface implements a write only slave interface. The IMISG745 cannot be read back. Subaddressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2wire control interface allows each clock output to be individually enabled or disabled. During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The IMISG745 will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The IMISG745 will not respond to any other control interface conditions. Previously set control registers are retained. SERIAL CONTROL REGISTERS NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) “Command Code “ byte, and 2) “Byte Count” byte. Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged. After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1, Byte 2, ...) will be valid and acknowledged. Byte 0: Frequency, Function Select Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 1 0 0 Pin# * * * * * * Description SSW bit. Selects Spread Spectrum width. 0 = Wide; 1 = Narrow. See table on page 3 S2 (for frequency table selection by software via I2C) S1 (for frequency table selection by software via I2C) S0 (for frequency table selection by software via I2C) 2 enables freq. Selection by hardware (set to 0) or software I C (set to 1) Reserved Bit 1 Bit 0 1 1 Tri-State 1 0 Normal (with Spread Spectrum On) mode 0 1 Test Mode 0 0 Normal (No Spread Spectrum) mode INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 5 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product SERIAL CONTROL REGISTERS (Cont.) Function Table Function Description Tri-State Normal CPU Hi-Z see table PCI Hi-Z see table Outputs SDRAM Hi-Z CPU Ref Hi-Z 14.318 AGP Hi-Z 14.318 Notes: 1. Tclk is a test clock over driven on the Xin input during test mode. Byte 1: CPU, SIO, USB Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 x 1 1 1 1 Pin# 26 25 40 41 43 44 Description 48 MHz enable/Stopped 24 MHz enable/Stopped 0 = Reserved for IMI TEST. 1 = normal operation. Reserved CPUCLK3 enable/Stopped CPUCLK2 enable/Stopped CPUCLK1 enable/Stopped CPUCLK0 enable/Stopped Byte 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x 1 1 1 1 1 1 1 Pin# 7 15 13 12 11 10 8 Description Reserved PCI_F enable/Stopped AGP1 enable/Stopped PCI4 enable/Stopped PCI3 enable/Stopped PCI2 enable/Stopped PCI1 enable/Stopped PCI0 enable/Stopped INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 6 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product SERIAL CONTROL REGISTERS (Cont.) Byte 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped ) Bit 7 6 5 4 3 2 1 @Pup 1 1 1 1 1 1 1 Pin# 28,29,31,32 34,35,37,38 - 0 1 - Description SDRAM(4:7) enable/Stopped Reserved Reserved Reserved SDRAM(0:3) enable/Stopped Reserved Reserved Reserved Byte 4: Additional SDRAM Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x x x x 1 1 1 1 Pin# 17,18,20,21 - Description Reserved Reserved Reserved Reserved SDRAM(8:11) enable/Stopped Reserved Reserved Reserved Byte 5: Peripheral Control (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x x x 1 x x x 1 Pin# 47 46 2 Description Reserved Reserved Reserved AGP2 enable/Stopped Reserved Reserved REF1 / SD_Sel# enable/Stopped REF0 / CS# enable/Stopped INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 7 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product MAXIMUM RATINGS Voltage Relative to VSS: -0.3V Voltage Relative to VDD: 0.3V Storage Temperature: -65ºC to + 150ºC Ambient Temperature: 0ºC to +70ºC Maximum Power Supply: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: 7V VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Type Max Units Conditions Input Low Voltage VIL - - 0.8 Vdc - Input High Voltage VIH 2.0 - - Vdc - Input Low Current IIL -66 µA Input High Current IIH 5 µA Tri-State leakage Current Ioz - - 10 µA Dynamic Supply Current Idd - - 116 mA CPU = 66.6 MHz, PCI = 33.3 MHz Static Supply Current Isdd - - 200 µA - Short Circuit Current ISC 25 - - mA 1 output at a time - 30 seconds VDD = VDDSD* = VDDPCI =3.3V ±5%, VDDCPU = 2.5 + 5%, TA = 0ºC to +70ºC SWITCHING CHARACTERISTICS Characteristic Symbol Min Type Max Units - 45 50 55 % Measured at 1.5V tOFF 1 - 4 ns 15 pf Load Measured at 1.5V Skew (CPU-CPU), (CPUAGP)*), (PCI-PCI), (SDRAM-SDRAM) tSKEW1 - - 250 ps 15 pf Load Measured at 1.5V Skew (CPU-SDRAM) tSKEW2 - - 500 ps 15 pf Load Measured at 1.5V ∆Period Adjacent Cycles ∆P - - +250 ps - Jitter Spectrum 20 dB Bandwidth from Center BWJ 500 KHz Output Duty Cycle CPU/SDRAM to PCI Offset Conditions VDD = VDDSD* = VDDPCI =3.3V ±5%, VDDCPU = 2.5 + 5%, TA = 0ºC to +70ºC Note 1: Ring Back must not enter this range. * In synchronous mode only. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 8 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product TB4_V BUFFER CHARACTERISTICS FOR CPU (0:3) Characteristic Symbol Min Type Pull-Up Current Min IOHmin 13 Pull-Up Current Max IOHmax Pull-Down Current Min IOLmin Pull-Down Current Max Max Units Conditions - 20 mA Vout = VDD - .5V 22 - 37 mA Vout = 1.25V 18 - 23 mA Vout = 0.4V IOLmax 50 - 61 mA Vout = 1.5V Rise/Fall Time Min Between 0.4 V and 2.0 V TRFmin 0.4 - - nS 10 pF Load Rise/Fall Time Max Between 0.4 V and 2.0 V TRFmax - - 2.0 nS 20 pF Load VDD = VDDSD* = VDDPCI =3.3V ±5%, VDDCPU = 2.5 + 5%, TA = 0ºC to +70ºC TB4 BUFFER CHARACTERISTICS FOR PCICLK(0:4,F), SDRAM(0:11), and REF0 Characteristic Symbol Min Type Max Units Pull-Up Current Min IOHmin 18 Pull-Up Current Max IOHmax Pull-Down Current Min Pull-Down Current Max Conditions - 23 mA Vout = VDD - .5V 44 - 64 mA Vout = 1.5V IOLmin 18 - 25 mA Vout = 0.4V IOLmax 50 - 70 mA Vout = 1.5V Rise/Fall Time Min Between 0.4 V and 2.4 V TRFmin 0.5 - - nS 15 pF Load Rise/Fall Time Max Between 0.4 V and 2.4 V TRFmax - - 2.0 nS 30 pF Load VDD = VDDSD* = VDDPCI =3.3V ±5%, VDDCPU = 2.5 + 5%, TA = 0ºC to +70ºC TB5 BUFFER CHARACTERISTICS FOR 24M, 48M and REF1 Characteristic Symbol Min Type Pull-Up Current Min IOHmin 13 Pull-Up Current Max IOHmax Pull-Down Current Min IOLmin Pull-Down Current Max Rise/Fall Time Max Between 0.4 V and 2.4 V Max Units Conditions - 17 mA Vout = VDD - .5V 30 - 40 mA Vout = 1.5V 13 - 19 mA Vout = 0.4V IOLmax 32 - 44 mA Vout = 1.5V TRF - - 2.0 nS 20 pF Load VDD = VDDSD* = VDDPCI =3.3V ±5%, VDDCPU = 2.5 + 5%, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 9 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product CRYSTAL AND REFERENCE OSCILLATOR PARAMETERS Characteristic Symbol Min Type Max Units Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM Calibration note 1 TS - - +/- 100 PPM Stability (Ta -10 to +60C) note 1 TA - - 5 PPM Aging (first year @ 25C) note 1 Mode Pin Capacitance OM CP - 36 - DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 20 - pF Effective Series resistance (ESR) R1 - - 40 Ohms Power Dissipation DL - - 0.10 mW pF Conditions Parallel Resonant Capacitance of XIN and Xout pins to ground (each) the crystals rated load. note 1 note 1 crystals internal package Shunt Capacitance CO -8 pF capacitance (total) For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore = 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore = 18.0 pF the total parasitic capacitance would therefore be = 20.0 pF. Note 1: It is recommended but not mandatory that a crystal meets these specifications. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 10 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product APPLICATION NOTE FOR SELECTION ON BIDIRECTIONAL PINS Vdd Pins 7, 8, 25, 26 and 46 are Power up bidirectional pins and are used for selecting different functions in this device (see Pin description, Page 2). During power-up of the device, these pins are in input mode (see Fig1, page4), therefore, they are considered input select pins internal to the IC, these pins have a large value pull-up each (250KΩ), therefore, a selection “1” is the default. If the system uses a slow power supply (over 5ms settling time), then it is recommended to use an external Pullup (Rup) in order to insure a high selection. In this case, the designer may choose one of two configurations, see FIG.3A and Fig. 3B. Rd Load Bidirectional JP1 JUMPER FIG.3A Rdn 5K Fig. 3A represents an additional pull up resistor 50KΩ connected from the pin to the power line, which allows a faster pull to a high level. If a selection “0” is desired, then a jumper is placed on JP1 to a 5KΩ resistor as implemented as shown in Fig. 3A. Please note the selection resistors (Rup, and Rdn) are placed before the Damping resistor (Rd) close to the pin. Fig. 3B represents a single resistor 10KΩ connected to a 3 way jumper, JP2. When a “1” selection is desired, a jumper is placed between leads1 and 3. When a “0” selection is desired, a jumper is placed between leads 1 and 2. Rup 50K IMISG745 Vdd IMISG745 JP2 3 Way Jumper Rsel 10K Rd Load Bidirectional FIG.3B If the system power supply is fast (less than 5ms settling time), then FIG3A only applies and Pull up Rup resistor is not necessary. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 11 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product PCB LAYOUT SUGGESTION IMISG745 Via to VDD Island 1 VCC Via to GND plane FB1 Via to VCC plane 1 48 2 47 3 46 C22 4 45 22µF 5 44 6 43 7 42 8 41 + C1 C6 C14 C19 VCC2 FB2 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 17 33 18 31 19 30 C48 FB3 C42 + VCC3 C22 22µF C36 32 20 29 21 28 22 27 23 26 24 25 C30 + C22 22µF This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach but C1, C6, C14, C19, C30, C36, C42, and C48 (all are 0.1µf) should always be used and placed as close as possible to their VDD pins. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 12 of 13 SG745 I2C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support. Approved Product PACKAGE DRAWING AND DIMENSIONS 48 PIN SSOP OUTLINE DIMENSIONS INCHES SYMBOL C L H E D a A2 A MIN NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.20 0.31 0.41 A2 0.085 0.090 0.095 2.16 2.29 2.41 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 .008 0.010 0.127 0.20 0.254 D 0.620 0.625 0.637 15.75 15.88 16.18 E 0.291 0.295 0.299 7.39 7.49 7.59 e A1 e B MILLIMETERS 0.0256 BSC 0.640 BSC H 0.395 0.408 0.420 10.03 10.36 10.67 L 0.024 0.030 0.040 0.61 0.76 1.02 a 0º 4º 8º 0º 4º 8º ORDERING INFORMATION Part Number Package Type IMISG745BYB 48 PIN SSOP Note: Production Flow Commercial, 0ºC to +70ºC The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI SG745BYB Date Code, Lot # IMISG745BYB Flow B = Commercial, 0ºC to + 70ºC Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.7 8/14/98 Page 13 of 13