Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 SST32HF32A1 32Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM (x16) MCP ComboMemories Preliminary Specifications FEATURES: • ComboMemories organized as: – 2M x16 Flash + 1024K x16 PSRAM • Single 2.7-3.3V Read and Write Operations • Concurrent Operation – Read from or Write to PSRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) for Flash or PSRAM Read – Standby Current: 60 µA (typical) • Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks • Erase-Suspend/Erase-Resume Capabilities • Security-ID Feature – SST: 128 bits; User: 128 bits • Hardware Block-Protection/WP# Input Pin – Bottom Block-Protection (bottom 32 KWord) for SST32HF32A1 • Fast Read Access Times: – Flash: 70 ns – PSRAM: 70 ns • Latched Address and Data for Flash • Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Package Available – 63-ball LFBGA (8mm x 10mm x 1.4mm) – 62-ball LFBGA (8mm x 10mm x 1.4mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST32HF32A1 ComboMemory devices integrate a CMOS flash memory bank with a CMOS PseudoSRAM (PSRAM) memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high-performance SuperFlash technology. Featuring high-performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 µsec. To protect against inadvertent flash write, the SST32HF32A1 devices contain on-chip hardware and software data protection schemes. The SST32HF32A1 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HF32A1 devices consist of two independent memory banks with respective bank enable signals. The flash and PSRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The PSRAM bank enable signal, BES# selects the PSRAM bank. The flash memory bank enable signal, ©2005 Silicon Storage Technology, Inc. S71260-01-000 5/05 1 BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HF32A1 provide the added functionality of being able to simultaneously read from or write to the PSRAM bank while erasing or programming in the flash memory bank. The PSRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the PSRAM bank can be accessed for Read or Write. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Concurrent Read/Write Operation The SST32HF32A1 devices are suited for applications that use both flash memory and PSRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF32A1 devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST32HF32A1 inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST32HF32A1 provide the unique benefit of being able to read from or write to PSRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from PSRAM, while altering the data in flash. See Figure 26 for a flowchart. The following table lists all valid states. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase PSRAM Read Write The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. Flash Read Operation The Read operation of the SST32HF32A1 devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 6 for further details. Device Operation The SST32HF32A1 use BES1#, BES2 and BEF# to control operation of either the flash or the PSRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the PSRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and PSRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. ©2005 Silicon Storage Technology, Inc. S71260-01-000 2 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Flash Word-Program Operation Erase-Suspend/Erase-Resume Commands The flash memory bank of the SST32HF32A1 devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs last. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 10 µs. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. During the command sequence, WP# should be statically held high or low. Any SDP commands loaded during the internal Program operation will be ignored. The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Flash Chip-Erase Operation The SST32HF32A1 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. Flash Sector/Block-Erase Operation The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF32A1 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines AMS-A11 are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines AMS-A15 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 12 and 13 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored, WP# should be statically held high or low. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 5 for the command sequence, Figure 10 for timing diagram, and Figure 25 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Write Operation Status Detection The SST32HF32A1 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. ©2005 Silicon Storage Technology, Inc. S71260-01-000 3 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TABLE 1: WRITE OPERATION STATUS The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Status DQ7 DQ6 DQ2 Normal Standard Operation Program DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Read from Erase-Suspended Sector/Block 1 1 Toggle Read from Non- Erase-Suspended Sector/Block Data Data Data Program DQ7# Toggle EraseSuspend Mode Flash Data# Polling (DQ7) N/A T1.0 1260 Note: DQ7 and DQ2 require a valid address when reading status information. When the SST32HF32A1 flash memory banks are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 22 for a flowchart. Flash Memory Data Protection The SST32HF32A1 flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the flash Write operation. This prevents inadvertent writes during power-up or power-down. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 22 for a flowchart. ©2005 Silicon Storage Technology, Inc. S71260-01-000 4 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Hardware Block Protection PSRAM Read The SST32HF32A1 support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address is 000000H-007FFFH. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. The PSRAM Read operation of the SST32HF32A1 is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. BES1# and BES2 are used for PSRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. Hardware Reset (RST#) PSRAM Write The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 17). The PSRAM Write operation of the SST32HF32A1 is controlled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the PSRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Product Identification Flash Software Data Protection (SDP) The Product Identification mode identifies the devices as the SST32HF32A1 and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and PSRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 4 and 5 for software operation, Figure 14 for the software ID entry and read timing diagram and Figure 23 for the ID entry command sequence flowchart. The SST32HF32A1 provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of threebyte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF32A1 devices are shipped with the software data protection permanently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. TABLE 2: PRODUCT IDENTIFICATION Manufacturer’s ID Address Data 0000H BFH 0001H 235BH Device ID SST32HF32A1 T2.1 1260 ©2005 Silicon Storage Technology, Inc. S71260-01-000 5 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Product Identification Mode Exit/Reset To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. This command may also be used to reset the device to Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 5 for software command codes, Figure 15 for timing waveform and Figure 23 for a flowchart. The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 5 for more details. Security ID Design Considerations The SST32HF32A1 devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired. SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. FUNCTIONAL BLOCK DIAGRAM Address Buffers PSRAM UBS# AMS-A0 LBS# BES1# BES2 BEF# OE1# WE1# WP# RESET# Control Logic I/O Buffers Address Buffers & Latches Notes: 1. For LS package only: SuperFlash Memory DQ15 - DQ8 DQ7 - DQ0 1260 B1.1 WE# = WEF# and/or WES# OE# = OEF# and/or OES# ©2005 Silicon Storage Technology, Inc. S71260-01-000 6 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TOP VIEW (balls facing down) SST32HF32A1 8 NC A20 A11 A15 A14 A16 A8 A10 A9 A13 7 A12 VSSF NC NC DQ15 WES# DQ14 DQ7 6 WEF# NC DQ13 DQ6 DQ4 DQ5 VSSS RST# DQ12 BES2 VDDS VDDF 5 4 WP# NC DQ10 DQ2 DQ3 A19 DQ11 DQ9 DQ8 DQ0 DQ1 LBS# UBS# OES# 2 1 NC A18 A17 A7 A6 NC A5 A4 A0 A3 A2 A1 BES1# BEF# VSSF OEF# NC NC 1260 62-tfbga LS P1.4 3 A B C D E F G H J K FIGURE 1: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM X 10MM) TOP VIEW (balls facing down) 8 7 NC NC NC VSS NC A15 NC NC A16 A11 A12 A13 A14 NC DQ15 DQ7 DQ14 NC A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 6 WE# BES2 A20 DQ4 VDDS NC WP# RST# NC DQ3 VDDF DQ11 4 3 LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2 A6 A5 A4 VSS OE# DQ0 DQ8 NC A3 A2 A1 BEF# BES1# NC 2 A7 1 NC A0 1260 63-tfbga LFS P2.2 5 A B C D E F G H J K FIGURE 2: PIN ASSIGNMENTS FOR 63-BALL LFBGA (8MM X 10MM) ©2005 Silicon Storage Technology, Inc. S71260-01-000 7 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TABLE 3: PIN DESCRIPTION Symbol Pin Name Functions AMS1 to A0 Address Inputs To provide flash address, AMS-A0. To provide PSRAM address, AMS-A0 DQ15-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low BES1# PSRAM Memory Bank Enable To activate the PSRAM memory bank when BES1# is low BES2 PSRAM Memory Bank Enable To activate the PSRAM memory bank when BES2 is high OEF#2 Output Enable To gate the data output buffers for Flash2 only OES#2 Output Enable To gate the data output buffers for PSRAM2 only WEF#2 Write Enable To control the Write operations for Flash2 only WES#2 Write Enable To control the Write operations for PSRAM2 only OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations UBS# Upper Byte Control (PSRAM) To enable DQ15-DQ8 LBS# Lower Byte Control (PSRAM) To enable DQ7-DQ0 WP# Write Protect To protect and unprotect sectors from Erase or Program operation RST# Reset To Reset and return the device to Read mode VSSF2 Ground Flash2 only VSSS2 Ground PSRAM2 only VSS Ground VDDF VDDS Power Supply (Flash) 2.7-3.3V Power Supply to Flash only Power Supply (PSRAM) 2.7-3.3V Power Supply to PSRAM only NC No Connection Unconnected pins T3.1 1260 1. AMS = Most Significant Address AMS = A20 for SST32HF32A1 2. LS package only ©2005 Silicon Storage Technology, Inc. S71260-01-000 8 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TABLE 4: OPERATIONAL MODES SELECTION1 BES22 OE#3 WE#3 LBS# UBS# DQ0-7 DQ8-15 VIH X X X X X HIGH-Z HIGH-Z X VIL X X X X VIL VIH VIH VIH X X HIGH-Z HIGH-Z VIL VIH X X VIH VIH VIH X VIH VIH X X HIGH-Z HIGH-Z X VIL VIL VIH X X DOUT DOUT VIH VIL X X DIN DIN VIH VIL X X X X VIL VIH Mode BEF# BES1# Full Standby VIH Output Disable VIH VIL Flash Read Flash Write Flash Erase PSRAM Read PSRAM Write Product Identification4 VIL VIL VIL VIH VIH VIL VIH X X VIL VIH X X VIL VIH X X VIL VIL VIH VIL VIH VIH X X VIL X VIL VIL VIH VIL VIL DOUT DOUT VIH VIL HIGH-Z DOUT VIL VIH DOUT HIGH-Z VIL VIL DIN DIN VIH VIL HIGH-Z DIN VIL VIH DIN HIGH-Z X X Manufacturer’s ID5 Device ID5 T4.1 1260 1. X can be VIL or VIH, but no other value. 2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time 3. OE# = OEF# and OES# WE# = WEF# and WES# for LS package only 4. Software mode only 5. With AMS-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0=0, SST32HF32A1 Device ID = 235BH, is read with A0=1. ©2005 Silicon Storage Technology, Inc. S71260-01-000 9 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TABLE 5: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAAH 55H SAX4 30H 4 Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H ID5 5555H AAH 2AAAH 55H 5555H 88H User Security ID Word-Program 5555H AAH 2AAAH 55H 5555H A5H WA6 Data User Security ID Program Lock-Out 5555H AAH 2AAAH 55H 5555H 85H XXH6 0000H Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H Exit9,10 5555H AAH 2AAAH 55H 5555H F0H XXH F0H Query Sec Software ID /Sec ID Exit Software ID Exit9,10 /Sec ID Exit 50H 10H T5.1 1260 1. Address format A14-A0 (Hex). Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST32HF32A1. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A20 for SST32HF32A1 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000010H to 000017H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST32HF32A1 Device ID = 235BH, is read with A0=1. AMS = Most significant address AMS = A20 for SST32HF32A1 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H. ©2005 Silicon Storage Technology, Inc. S71260-01-000 10 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. VDD = VDDF and VDDS 2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information. 3. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Extended Ambient Temp VDD 0°C to +70°C 2.7-3.3V -20°C to +85°C 2.7-3.3V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 19 and 20 ©2005 Silicon Storage Technology, Inc. S71260-01-000 11 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V) Limits Symbol Parameter IDD Active VDD Current Min Max Units Address input = VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open Test Conditions Read OE#=VIL, WE#=VIH Flash 18 mA BEF#=VIL, BES1#=VIH, or BES2=VIL PSRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH 40 mA Concurrent Operation Write1 BEF#=VIH, BES1#=VIL , BES2=VIH WE#=VIL Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH PSRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH ISB Standby VDD Current 110 µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC IRT Reset VDD Current 30 µA Reset=VSS±0.3V ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage V VDD=VDD Max VIHC Input High Voltage (CMOS) V VDD=VDD Max VOLF Flash Output Low Voltage V IOL=100 µA, VDD=VDD Min VOHF Flash Output High Voltage V IOH=-100 µA, VDD=VDD Min VOLS PSRAM Output Low Voltage V IOL =1 mA, VDD=VDD Min VOHS PSRAM Output High Voltage V IOH =-500 µA, VDD=VDD Min 0.7 VDD VDD-0.3 0.2 VDD-0.2 0.4 2.2 T6.1 1260 1. IDD active while Erase or Program is in progress. TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs T7.0 1260 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 12 pF T8.0 1260 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: FLASH RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR 1 ILTH1 Data Retention Latch Up JEDEC Standard 78 T9.0 1260 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. S71260-01-000 12 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications AC CHARACTERISTICS TABLE 10: PSRAM READ CYCLE TIMING PARAMETERS Symbol Parameter Min 70 Max Units TRCS Read Cycle Time TAAS Address Access Time 70 ns TBES Bank Enable Access Time 70 ns TOES Output Enable Access Time 35 ns TBYES UBS#, LBS# Access Time 70 ns TBLZS1 BES# to Active Output 0 ns TOLZS1 Output Enable to Active Output 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 ns TBHZS 1 BES# to High-Z Output TOHZS1 TBYHZS Output Disable to High-Z Output 1 TOHS 0 UBS#, LBS# to High-Z Output Output Hold from Address Change ns 25 ns 25 ns 35 ns 10 ns T10.1 1260 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: PSRAM WRITE CYCLE TIMING PARAMETERS Symbol Parameter Min TWCS Write Cycle Time 70 Max Units TBWS Bank Enable to End-of-Write 60 ns TAWS Address Valid to End-of-Write 60 ns TASTS Address Set-up Time 0 ns TWPS Write Pulse Width 60 ns TWRS Write Recovery Time 0 ns TBYWS UBS#, LBS# to End-of-Write 60 ns TODWS Output Disable from WE# Low TOEWS Output Enable from WE# High 0 ns TDSS Data Set-up Time 30 ns TDHS Data Hold from Write Time 0 ns 30 ns ns T11.1 1260 ©2005 Silicon Storage Technology, Inc. S71260-01-000 13 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V Symbol Parameter Min TRC Read Cycle Time 70 TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time TCLZ1 BEF# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 BEF# High to High-Z Output TOHZ1 OE# High to High-Z Output TOH1 Output Hold from Address Change TRP 1 TRHR1 TRY 1,2 Max Units ns 35 ns ns ns 20 ns 20 ns 0 ns RST# Pulse Width 500 ns RST# High before Read 50 ns RST# Pin Low to Read Mode 20 µs T12.1 1260 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations. TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Word-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and BEF# Setup Time 0 ns TCH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 ns TIDA 1 Min Max Units 10 µs Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T13.0 1260 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. S71260-01-000 14 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TRCS ADDRESSES AMSS-0 TOHS TAAS BES1# TBES BES2 TBES TBLZS TBHZS TOES OE# TOLZS TOHZS TBYES UBS#, LBS# TBYLZS TBYHZS DQ15-0 DATA VALID 1260 F03.0 Note: AMSS = Most Significant PSRAM Address AMSS = A19 for SST32HF32A1 FIGURE 3: PSRAM READ CYCLE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71260-01-000 15 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TWCS ADDRESSES AMSS3-0 TASTS TWPS TWRS WE# TAWS TBWS BES1# BES2 TBWS TBYWS UBS#, LBS# TOEWS TODWS DQ15-8, DQ7-0 TDSS TDHS VALID DATA IN NOTE 2 NOTE 2 1260 F04.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance. If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant PSRAM Address AMSS = A19 for SST32HF32A1 FIGURE 4: PSRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 ©2005 Silicon Storage Technology, Inc. S71260-01-000 16 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TWCS ADDRESSES AMSS3-0 TWPS TWRS WE# TBWS BES1# TBWS BES2 TAWS TASTS TBYWS UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE 2 TDHS VALID DATA IN NOTE 2 1260 F05.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant PSRAM Address AMSS = A19 for SST32HF32A1 FIGURE 5: PSRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 ©2005 Silicon Storage Technology, Inc. S71260-01-000 17 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TAA TRC ADDRESS AMS-0 TCE BEF# TOE OE# TOHZ TOLZ VIH WE# TCLZ HIGH-Z DQ15-0 TCHZ TOH HIGH-Z DATA VALID DATA VALID 1260 F06.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH BEF# TCS DQ15-0 XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) 1260 F07.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence X can be VIL or VIH, but no other value FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71260-01-000 18 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TCP BEF# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1260 F08.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence X can be VIL or VIH, but no other value FIGURE 8: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM ADDRESSES AMSF-0 TCE BEF# TOES TOEH OE# TOE WE# DQ7 Data Data# Data# Data 1260 F09.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71260-01-000 19 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications ADDRESSES AMSF-0 TCE BEF# TOES TOE TOEH OE# WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1260 F10.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555 BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 1260 F11.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13) X can be VIL or VIH, but no other value. FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71260-01-000 20 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA BAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 SW0 SW1 SW2 SW3 SW4 SW5 1260 F12.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13.) BAX = Block Address WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence X can be VIL or VIH, but no other value. FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71260-01-000 21 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 1260 F13.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13.) SAX = Sector Address WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence X can be VIL or VIH, but no other value. FIGURE 13: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71260-01-000 22 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications THREE-WORD SEQUENCE FOR SOFTWARE ID ENTRY 5555 ADDRESS A14-0 2AAA 5555 0000 0001 BEF# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 00BF SW0 SW1 SW2 MFG ID DEVICE ID 1260 F14.0 Note: X can be VIL or VIH, but no other value. Device ID - See Table 2 on page 5 FIGURE 14: SOFTWARE ID ENTRY AND READ THREE-WORD SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 DQ15-0 XXAA 2AAA 5555 XX55 XXF0 TIDA BEF# OE# TWP WE# TWHP 1260 F15.0 SW0 SW1 SW2 Note: X can be VIL or VIH, but no other value. FIGURE 15: SOFTWARE ID EXIT AND RESET ©2005 Silicon Storage Technology, Inc. S71260-01-000 23 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications THREE-BYTE SEQUENCE FOR SEC ID ENTRY ADDRESS AMSF-0 5555 2AAA 5555 BEF# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 1260 F16.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF32A1 WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 16: FLASH SEC ID ENTRY ©2005 Silicon Storage Technology, Inc. S71260-01-000 24 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications RST# TRP BEF#/OE# TRHR 1260 F17.0 FIGURE 17: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS) TRP RST# TRY BEF#/OE# End-of-Write Detection (Toggle-Bit) 1260 F18.0 FIGURE 18: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION) ©2005 Silicon Storage Technology, Inc. S71260-01-000 25 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1260 F19.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1260 F20.0 FIGURE 20: A TEST LOAD EXAMPLE ©2005 Silicon Storage Technology, Inc. S71260-01-000 26 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Start Write data: XXAAH Address: 5555H Write data: XX55H Address: 2AAAH Write data: XXA0H Address: 5555H Write Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1260 F21.0 Note: X can be VIL or VIH, but no other value FIGURE 21: WORD-PROGRAM ALGORITHM ©2005 Silicon Storage Technology, Inc. S71260-01-000 27 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Read word Read DQ7 Wait TBP, TSCE, or TBE Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1260 F22.0 FIGURE 22: WAIT OPTIONS ©2005 Silicon Storage Technology, Inc. S71260-01-000 28 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Sec ID Query Entry Command Sequence Software Product ID Entry Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX88H Address: 5555H Load data: XX90H Address: 5555H Wait TIDA Wait TIDA Read Sec ID Read Software ID 1260 F23.0 X can be VIL or VIH, but no other value FIGURE 23: SEC ID/SOFTWARE ID COMMAND FLOWCHARTS ©2005 Silicon Storage Technology, Inc. S71260-01-000 29 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Software ID Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XXF0H Address: 5555H Return to normal operation Wait TIDA Return to normal operation X can be VIL or VIH, but no other value 1260 F24.0 FIGURE 24: SOFTWARE ID/SEC ID COMMAND FLOWCHARTS ©2005 Silicon Storage Technology, Inc. S71260-01-000 30 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1260 F25.0 Note: X can be VIL or VIH, but no other value. FIGURE 25: ERASE COMMAND SEQUENCE ©2005 Silicon Storage Technology, Inc. S71260-01-000 31 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications Concurrent Operation Load SDP Command Sequence Flash Program/Erase Initiated Wait for End of Write Indication Read or Write SRAM End Wait Flash Operation Completed End Concurrent Operation 1260 F26.0 FIGURE 26: CONCURRENT OPERATION FLOWCHART ©2005 Silicon Storage Technology, Inc. S71260-01-000 32 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications PRODUCT ORDERING INFORMATION Device SST32HFxxxx Speed - XXX Suffix1 - XX Suffix2 - XXX X Environmental Attribute E1 = non-Pb Package Modifier FS = 63 ball positions S = 62 ball positions Package Type L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Hardware Block Protection 1 = Bottom Boot Block PSRAM Density A = 16 Mbit Flash Density 32 = 32 Mbit Voltage H = 2.7-3.3V Product Series 32 = MPF+ + PSRAM ComboMemory 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. Valid combinations for SST32HF32A1 SST32HF32A1-70-4C-LS SST32HF32A1-70-4C-LSE SST32HF32A1-70-4C-LFS SST32HF32A1-70-4C-LFSE SST32HF32A1-70-4E-LS SST32HF32A1-70-4E-LSE SST32HF32A1-70-4E-LFS SST32HF32A1-70-4E-LFSE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2005 Silicon Storage Technology, Inc. S71260-01-000 33 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications PACKAGING DIAGRAMS TOP VIEW BOTTOM VIEW 10.00 ± 0.20 7.20 0.80 8 8 7 7 6 6 5 5 8.00 ± 0.20 4 4 5.60 3 3 2 2 1 1 0.40 ± 0.05 (62X) 0.80 K J H G F E D C B A A B C D E F G H J K A1 CORNER A1 CORNER SIDE VIEW 1.30 ± 0.10 1mm 0.12 SEATING PLANE Note: 1. 2. 3. 4. 0.32 ± 0.05 Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. All linear dimensions are in millimeters. Coplanarity: 0.12 mm 62-lfbga-LS-8x10-400mic-4 Ball opening size is 0.32 mm (± 0.05 mm) 62-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM SST PACKAGE CODE: LS ©2005 Silicon Storage Technology, Inc. S71260-01-000 34 5/05 Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 Preliminary Specifications BOTTOM VIEW TOP VIEW 7.20 10.0 ± 0.1 0.80 8 8 7 7 6 6 5 5 8.0 ± 0.1 4 4 5.60 3 3 2 2 1 1 0.40 ± 0.05 (63X) 0.80 K J H G F E D C B A A B C D E F G H J K A1 CORNER A1 CORNER 1.3 ± 0.1 SIDE VIEW 1mm 0.12 SEATING PLANE Note: 0.32 ± 0.05 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size: 0.32 mm (± 0.05 mm) 63-lfbga-LFS-8x10-400mic-1 63-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM SST PACKAGE CODE: LFS TABLE 14: REVISION HISTORY Number Description 00 • 01 • Date Initial Release Jun 2004 Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz Table 6 on page 12 • Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on page 11. • Added RoHS compliance information on page 1 and page 33 • Changes to the “Product Ordering Information” on page 33 – Removed all 90 ns information and associated MPNs – Added non-Pb MPNs for all devices – Removed SST32HF64A1/B1 commercial temperature devices and MPNs – Moved SST32HF64A1/B1 extended temperature MPNs to S71299 data sheet May 2005 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2005 Silicon Storage Technology, Inc. S71260-01-000 35 5/05