W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY* 256MB – 2x16Mx64 DDR SDRAM UNBUFFERED FEATURES DESCRIPTION DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) The W3EG6433S is a 2x16Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of sixteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.2V JEDEC 184 pin DIMM package Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. • JD3 PCB height: 30.48 (1.20") NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES DDR333@CL=2.5 DDR266 @CL=2 DDR266 @CL=2 DDR266 @CL=2.5 Clock Speed 166MHz 133MHz 133MHz 133MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2-3-3 2.5-3-3 November 2005 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 PRELIMINARY PIN CONFIGURATION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 NC NC VCC November 2005 Rev. 2 PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL NC A0 NC VSS NC BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DQM0 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DQM1 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 NC VSS DQ21 A11 DM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3 A3 D30 VSS DQ31 NC NC VCCQ CK0 CK0# PIN NAMES PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 A0-A11 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0, CK1, CK2 CK0#CK1#, CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 NC SYMBOL VSS NC A10 NC VCCQ NC VSS DQ36 DQ37 VCC DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# CS1# DM5 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DQM6 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD 2 Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-in-mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM No Connect White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DM0 DQS4 DM4 DM# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS DM# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS1 DM1 CS# DQS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS5 DM5 CS# DQS DM# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS DM# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS2 DM2 CS# DQS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS6 DM6 CS# DQS DM# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS DM# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS3 DM3 CS# DQS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS7 DM7 CS# DQS DM# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS DM# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM# CS# DQS I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DDR SDRAMs VCCSPD SPD VCC/VCCQ DDR SDRAMs DDR SDRAMs Serial PD SCL DDR SDRAMs CK0/1/2 VREF DDR SDRAMs VSS DDR SDRAMs CK0/1/2# Card Edge SDA WP A0 A1 A2 SA0 SA1 SA2 R=120Ω *DDR SDRAMs *DDR SDRAMs DDR SDRAMs DDR SDRAMs BA0 - BA1 BA0-BA1 : DDR SDRAMs * Clock Wiring A0 - A11 A0-A11 : DDR SDRAMs RAS# RAS#: DDR SDRAMs CAS# CAS# : DDR SDRAMs CKE0/1 WE# CKE : DDR SDRAMs WE#: DDR SDRAMs Clock Input DDR SDRAMs *CK0/CK0# 4 DDR SDRAMs *CK1/CK1# 6 DDR SDRAMs *CK2/CK2# 6 DDR SDRAMs Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown. 3. DQ, DQS, DM#/DQS# resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS#, CAS#, WE# resistors: 3 Ohms + 5%. *Clock Net Wiring November 2005 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V TSTG -55 to +150 °C Power Dissipation PD 24 W Short Circuit Current IOS 50 mA Storage Temperature Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended perating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C) Parameter Symbol Min Max Unit Supply Voltage (for device with a nominal VCC of 2.5V) VCC 2.3 2.7 V I/O Supply Voltage VCCQ 2.3 2.7 V I/O Reference Voltage VREF 0.49*VCCQ 0.51*VCCQ V 1 I/OTermination Voltage VTT VREF-0.04 VREF+0.04 V 2 Input Logic High Voltage VIH VREF + 0.15 VCCQ + 0.3 V VIL -0.3 VREF -0.15 V VIN(DC) -0.3 VCCQ + 0.3 V Input Logic Low Voltage Input Voltage Level, CK and CK# Inputs Note Input Differential Voltage, CK and CK# Inputs VID(DC) 0.36 VCCQ + 0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 uA Input leakage current II -2 2 Output leakage current IOZ -5 5 Output High Current(Normal strengh driver); VOUT = VTT = 0.84V IOH -16.8 uA Output High Current(Normal strengh driver); VOUT = VTT = 0.84V IOL 16.8 uA Output High Current(Half strengh driver); VOUT = VTT = 0.45V VOH -9 uA Output High Current(Half strengh driver); VOUT = VTT = 0.45V VOL 9 uA uA NOTES: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. November 2005 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 PRELIMINARY CAPACITANCE TA = 25°C. f = 1MHz, VCC = 2.5V Parameter Symbol Max Unit CIN1 81 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 81 pF Input Capacitance (CKE0, CKE1, CKE2) CIN3 50 pF Input Capacitance (CLK0, CLK1, CLK2) CIN4 34 pF Input Capacitance (CS0#, CS1#) CIN5 50 pF Input Capacitance (DMO ~ DM7) CIN6 12 pF Input Capacitance (BA0-BA1) CIN7 81 pF Data input/output capacitance (DQ0-DQ63)(DQS) COUT 12 pF Data input/output capacitance (CB0-CB7) COUT - pF Input Capacitance (A0-A11) November 2005 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR333@CL=2.5 Max DDR266@CL=2 Max DDR266@CL=2/2.5 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 680 640 640 mA Operating Current IDD1 One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 880 800 800 mA Precharge PowerDown Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 24 24 24 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 200 180 180 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 240 200 200 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 360 320 320 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 1,120 960 960 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 1,160 1,000 1,000 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 1,320 1,240 1,240 mA Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 16 16 16 mA 2,400 2,000 2,000 mA NOTES: • Module IDD was calculated on the basis of component IDD and can be different measured according to dq hearing cap. • IDD specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. November 2005 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC Characteristics Parameter 335 262 263 265 (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5) Symbol Min Row cycle time tRC 60 60 65 65 ns Refresh row cycle time tRFC 72 75 75 75 ns Row active time tRAS 42 RAS to CAS delay tRCD 18 15 20 20 ns Row precharge time tRP 18 15 20 20 ns Row active to Row active delay tRRD 12 15 15 15 ns Write recovery time tWR 15 15 15 15 ns Last data in to Read command tWTD 1 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 1 tCK tCK 7.5 12 7.5 12 7.5 12 10 12 ns 6 12 7.5 12 7.5 12 7.5 12 ns Clock cycle time CL=2.0 CL=2.5 Max Min 70K 45 Max 120K Min 45 Max 120K Min 45 Max 120K Units ns Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK Notes tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to output data edge tDQSQ - 0.45 - 0.5 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 0.2 tCK 12 3 DQS falling edge from Ck rising-hold time tDSH 0.2 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 DQS-in cycle time tDSC 0.9 Address and Control Input setup time (fast) tIS 0.75 0.9 0.9 0.9 ns i,5.7~9 Address and Control Input hold time (fast) tIH 0.75 0.9 0.9 0.9 ns i,5.7~9 Address and Control Input setup time (slow) tIS 0.8 1.0 1.0 1.0 ns i,6~9 Address and Control Input setup time (slow) tIH 0.8 Data-out high impedence time from CK/CK tHZ 0.35 1.1 0.9 0.35 1.1 1.0 +0.7 0.9 1.0 +0.75 -0.75 1.0 +0.75 -0.75 tCK 1.1 +0.75 +0.75 -0.75 +0.75 tCK ns i,6~9 ns 1 ns 1 Data-out high impedence time from CK/CK tLZ -0.7 tSL(I) 0.5 0.5 0.5 0.5 V/ns Input Slew Rate (for I/O pins) tSL(IO) 0.5 0.5 0.5 0.5 V/ns 7 +0.75 0.9 Input Slew Rate (for input only pins) November 2005 Rev. 2 +0.7 0.35 1.1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC Characteristics Parameter Symbol 335 262 263 265 (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5) Min Max Min Max Min Max Min Max Units Notes Output Slew Rate (x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 V/ns Output Slew Rate Matching Ratio (rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5 ns Mode register set cycle time tMRD 12 15 15 15 ns j, k DQ & DM setup time to DQS tDS 0.5 0.5 0.5 0.5 ns j, k DQ & DM hold time to DQS tDH 0.45 0.5 0.5 0.5 ns 8 Control & Address input pulse width tIPW 2.2 2.2 2.2 2.2 ns 8 DQ & DM input pulse width tDIPW 1.75 1.75 1.75 1.75 ns Power down exit time tRDEX 6 7.5 7.5 7.5 ns Exit self refresh to non-Read command tXSRD 75 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 200 tCK Refreash interval time tREFI us 4 Output DQS valid window tQH tHP-tQHS - tHP-tQHS - tHP-tQHS - tHP-tQHS ns 11 Clock half period tQH tCLmin or tchmin - tCLmin or tchmin - tCLmin or tchmin - tCLmin or tchmin ns 10, 11 0.75 ns 11 0.6 tCK 2 tCK 13 15.6 15.6 0.55 15.6 0.75 15.6 0.75 Data hold skew factor tQHS DQS write postamble time tWPST 0.4 Active to Read with Auto precharge command tRAP 18 20 20 20 Autoprecharge write recovery & Precharge time tXSNR tWR/tCK + tRP/tCK) tWR/tCK + tRP/tCK) tWR/tCK + tRP/tCK) tWR/tCK + tRP/tCK) November 2005 Rev. 2 0.6 0.4 8 0.6 0.4 0.6 0.4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 PRELIMINARY Notes 1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 9. Slew Rate is measured between VOH(ac) and VOL(ac). 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH. For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 11. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 12. 5. For command/address input slew rate ≥ 1.0 V/ns. tDQSQ Consists of data pin skew and output pattern effects and p-channel to n-channel variation of the output drivers for any given cycle. 6. For command/address input slew rate ≥ 0.5 V/ns and > 1.0 V/ns 13. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266 at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks 7. For CK & CK# slew rate ≥ 1.0 V/ns. 8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. November 2005 Rev. 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY ORDERING INFORMATION FOR JD3 Part Number Speed CAS Latency tRCD tRP Height* W3EG6433S335JD3 166MHz/333Mb/s 2.5 3 3 30.48 (1.20") W3EG6433S263JD3 133MHz/266Mb/s 2 2 2 30.48 (1.20") W3EG6433S263JD3 133MHz/266Mb/s 2 3 3 30.48 (1.20") W3EG6433S265JD3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 2.54 (0.100) 3.99 (0.157 (2x)) 30.48 (1.20) MAX 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 3.99 (0.157) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) November 2005 Rev. 2 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY ORDERING INFORMATION FOR D3 Part Number Speed CAS Latency tRCD tRP Height* W3EG6433S335D3 166MHz/333Mb/s 2.5 3 3 30.48 (1.20") W3EG6433S262D3 133MHz/266Mb/s 2 2 2 30.48 (1.20") W3EG6433S263D3 133MHz/266Mb/s 2 3 3 30.48 (1.20") W3EG6433S265D3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 2.54 (0.100) 3.99 (0.157 (2x)) 30.48 (1.20) MAX 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 3.99 (0.157) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) November 2005 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-D3 -JD3 White Electronic Designs PRELIMINARY Document Title 256MB – 2x16Mx64 DDR SDRAM UNBUFFERED Revision History Rev # History Release Date Status Rev 1 1.1 Created Datasheet 12-04 Preliminary 5-05 Preliminary 11-05 Preliminary 1.2 Added lead-free and RoHS notes 1.3 Added AC specs 1.4 Moved from Advanced to Preliminary Rev 2 2.1 Added JEDEC standard PCB 2.2 D3 option is "NOT RECOMMENDED FOR NEW DESIGNS" 2.3 Added lead-free and RoHS notes 2.4 Added source control notes 2.5 Added industrial temperature options Rev 3 3.1 Update AC, IDD and cap specs 3.2 Add 333MH speed November 2005 Rev. 2 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com