WEDC W3EG7218S202BD4

White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL
FEATURES
DESCRIPTION
Double-data-rate architecture
DDR200 and DDR266
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
The W3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of nine
16Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
•
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Package height options:
AD4: 35.5mm (1.38") and
BD4: 31.75mm (1.25")
OPERATING FREQUENCIES
November 2004
Rev. 1
DDR266 @CL=2
DDR266 @CL=2.5
DDR200 @CL=2
Clock Speed
133MHz
133MHz
100MHz
CL-tRCD-tRP
2-2-2
2.5-3-3
2-2-2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
VREF
VREF
VSS
VSS
DQ0
DQ4
DQ1
DQ5
VCC
VCC
DQS0
DQM0
DQ2
DQ6
VSS
VSS
DQ3
DQ7
DQ8
DQ12
VCC
VCC
DQ9
DQ13
DQS1
DQM1
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VCC
VCC
CK0
VCC
CK0#
VSS
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VCC
VCC
DQS2
DQM2
DQ18
DQ22
November 2004
Rev. 1
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
VSS
VSS
DQ19
DQ23
DQ24
DQ28
VCC
VCC
DQ25
DQ29
DQS3
DQM3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VCC
VCC
CB0
CB4
CB1
CB5
VSS
VSS
DQS8
DQM8
CB2
CB6
VCC
VCC
CB3
CB7
NC
NC
VSS
VSS
NC
VSS
NC
VCC
VCC
VCC
NC
CKE0
NC
NC
NC
A11
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A9
AB
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VCC
VCC
A10/AP
BA1
RA0
RAS#
WE#
CAS#
CS0
NC
NC
NC
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VCC
VCC
DQS4
DQM4
DQ34
DQ38
VSS
VSS
DQ35
DQ39
DQ40
DQ44
VCC
VCC
DQ41
DQ45
DQS5
DQM5
VSS
VSS
PIN NAMES
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
DQ42
DQ46
DQ43
DQ47
VCC
VCC
VCC
NC
VSS
NC
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VCC
VCC
DQS6
DQM6
DQ50
DQ54
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VCC
VCC
DQ57
DQ61
DQS7
DQM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VCC
VCC
SDA
SA0
SCL
SA1
VCCSPD
SA2
VCCID
NC
2
A0-A11
Address input (Multiplexed)
BA0-BA1
Bank Select Address
DQ0-DQ63
Data Input/Output
CB0-CB7
Check bits
DQS0-DQS8
Data Strobe Input/Output
CK0
Clock Input
CK0#
Clock Input
CKE0
Clock Enable Input
CS0#
Chip Select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
DQM0-DQM8 Data-In Mask
VCC
Power Supply (2.5V)
VCCQ
Power Supply for DQS (2.5V)
VSS
Ground
VREF
Power Supply for Reference
VCCSPD
Serial EEPROM Power Supply
(2.3V to 3.6V)
SDA
Serial Data I/O
SCL
Serial Clock
SA0-SA2
Address in EEPROM
VCCID
VCC Identification Flag
NC
No Connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DQS4
DQM0
DQM4
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS5
DQM1
DQM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2
DQS6
DQM2
DQM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS3
DQS7
DQM3
DQM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS8
DQM8
BA0, BA1
A0-A11
RAS#
CAS#
CKE0
WE#
PLL
SERIAL PD
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
BA0, BA1
A0-A11
RAS#
VDDSPD
SPD/EEPROM
VDD
DDR SDRAMS
VREF
DDR SDRAMS
VSS
DDR SDRAMS
CAS#
CKE0
WE#
Note: All resistor values are 22Ω unless otherwise indicated
November 2004
Rev. 1
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 1
120
CK0
CK0#
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to VSS
VIN, VOUT
– 0.5 ~ 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
–1.0 ~ 3.6
V
Storage Temperature
Units
TSTG
– 55 ~ +150
°C
Power Dissipation
PD
9
W
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VCC
2.3
2.7
V
Supply Voltage
VCCQ
2.3
2.7
V
Reference Voltage
VREF
1.15
1.35
V
Termination Voltage
VTT
1.15
1.35
V
Input High Voltage
VIH
VREF + 0.15
VCCQ + 0.3
V
Input Low Voltage
VIL
– 0.3
VREF – 0.15
V
Output High Voltage
VOH
VTT+ 0.76
—
V
Output Low Voltage
VOL
—
VTT – 0.76
V
Symbol
Max
Unit
Input Capacitance (A0-A11)
CIN1
29
pF
Input Capacitance (RAS#,CAS#,WE#)
CIN2
29
pF
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (CKE0,CKE1)
CIN3
29
pF
Input Capacitance (CK0,CK0#)
CIN4
5.5
pF
Input Capacitance (CS0#,CS1#)
CIN5
29
pF
Input Capacitance (DQM0-DQM8)
CIN6
8
pF
Input Capacitance (BA0-BA1)
CIN7
29
pF
Data input/output Capacitance (DQ0-DQ63)(DQS)
COUT
8
pF
Data input/output Capacitance (CB0-CB7)
COUT
8
pF
November 2004
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)
Parameter
DDR266
@CL=2.5
DDR200
@CL=2
Max
Max
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; (MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address and control
inputs changing once every two cycles. tRC=tRC(MIN); tCK=tCK
1125
990
990
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2;
tRC=tRC(MIN);tCK=tCK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
1215
1080
1080
mA
Precharge PowerDown Standby Current
IDD2P
All device banks idle; Power-down mode; tCK=tCK(MIN);
CKE=(low)
27
27
27
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high;
Address and other control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS and DM.
405
405
405
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode; tCK(MIN);
CKE=(low)
225
225
225
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
450
450
450
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; tCK=tCK(MIN); IOUT = 0mA.
1260
1170
1170
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
1260
1125
1125
mA
Auto Refresh Current
IDD5
tRC=tRC(MIN)
2385
1980
1980
mA
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto precharge with
tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change
only during Active Read or Write commands
November 2004
Rev. 1
Symbol Conditions
DDR266
@CL=2
5
27
27
27
mA
3195
2970
2970
mA
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White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1.
Typical Case : VCC=2.5V, T=25°C
1.
Typical Case : VCC=2.5V, T=25°C
2.
Worst Case : VCC=2.7V, T=10°C
2.
Worst Case : VCC=2.7V, T=10°C
3.
Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3.
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4.
Timing Patterns :
4.
Timing Patterns :
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
November 2004
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
262
PARAMETER
265/202
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Access window of DQs from CK/CK#
tAC
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
26
CL = 2.5
tCK (2.5)
7.5
13
7.5
13
ns
40, 45
CL = 2
tCK (2)
7.5
13
10
13
ns
40, 45
tDH
0.5
ns
23, 27
Clock cycle time
DQ and DM input hold time relative to DQS
0.5
NOTES
DQ and DM input setup time relative to DQS
tDS
0.5
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.60
DQS input high pulse width
tDQSH
0.35
DQS input low pulse width
tDQSL
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
Write command to first DQS latching transition
tDQSS
0.75
DQS falling edge to CK rising - setup time
tDSS
0.2
DQS falling edge from CK rising - hold time
tDSH
0.2
Half clock period
tHP
Data-out high-impedance window from CK/CK#
tHZ
ns
16, 37
Data-out low-impedance window from CK/CK#
tLZ
-0.75
-0.75
ns
16, 37
Address and control input hold time (slow slew rate)
tIHS
0.90
1.1
ns
12
Address and control input setup time (slow slew rate)
tISS
0.90
1.1
ns
12
Address and Control input pulse width (for each input)
tIPW
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
15
15
ns
November 2004
Rev. 1
7
+0.75
-0.75
+0.75
0.35
0.35
tCK
0.5
1.25
0.75
0.6
ns
1.25
tCK
0.2
tCK
tCH, tCL
+0.75
22, 23
tCK
0.2
tCH, tCL
ns
tCK
ns
+0.75
30
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)
AC CHARACTERISTICS
PARAMETER
262
265/202
MAX
MIN
UNITS
NOTES
ns
22, 23
SYMBOL
MIN
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP - tQHS
MAX
Data Hold Skew Factor
tQHS
ACTIVE to PRECHARGE command
tRAS
40
ACTIVE to READ with Auto precharge command
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
65
ns
AUTO REFRESH command period
tRFC
75
75
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
38
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
38
tHP - tQHS
0.75
120,000
40
0.75
ns
120,000
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
15
15
ns
DQS write preamble
tWPRE
0.25
0.25
tCK
DQS write preamble setup time
tWPRES
0
DQS write postamble
tWPST
0.4
Write recovery time
tWR
15
15
ns
Internal WRITE to READ command delay
tWTR
1
1
tCK
Data valid output window (DVW)
0
0.6
0.4
tQH - tDQSQ
na
0.6
tQH - tDQSQ
31, 48
43
ns
18, 19
tCK
17
ns
22
REFRESH to REFRESH command interval
tREFC
140.6
140.6
µs
21
Average periodic refresh interval
tREFI
15.6
15.6
µs
21
Terminating voltage delay to VDD
tVTD
0
0
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
tCK
November 2004
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
17. The intent of the Don’t Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high [above VIHDC (MIN)] then it must not transition low (below
VIHDC) prior to tDQSH (MIN).
18. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maximum absolute value
for tRAS.
21. The refresh period 64ms. This equates to an average refresh rate of 15.625µs
128MB. However, an AUTO REFRESH command must be asserted at least once
every 140.6µs 128MB; burst refreshing or posting by the DRAM controller greater
than eight refresh cycles is not allowed.
22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ,
and tQH (tQH = tHP - tQHS). The data valid window derates in direct porportion with
the clock duty cycle and a practical data valid window can be derived, as shown in
Figure 7, Derating Data Valid Window. The clock is allowed a maximum duty cycle
variation of 45/55, beyond which functionality is uncertain. The data valid window
derating curves are provided below for duty cycles ranging between 50/50 and
45/55.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
26. JEDEC specifies CK and CK# input slew rate must be ≤ 1V/ns (2V/ns
differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.
If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps
must be added to tDS and tDH for each 100 mv/ns reduction in slew rate. If slew
rate exceeds 4 V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5
V/ns.
28. VCC must not vary more than 4 percent if CKE is not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device
CK and CK# inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not allowed to be issued until
tRAS(min) can be satisfied prior to the internal precharge command being issued.
32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9V, which ever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either - 300mV or 2.2V, whichever is more positive.
VTT
Output
(VOUT)
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
50
50Ω
Reference
Point
30pF
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may
not exceed ±2 percent of the DC value. Thus, from VCCQ/2, Vref is allowed ±25mV
for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest VREF bypass capacitor.
VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF.
IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265
with the outputs open.
Enables on-chip refresh and address counters.
IDD specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS, f
= 100 MHz, TA = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing
must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew
rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For -335, slew rates must be 0.5 V/ns.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period
before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.
The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
tHZ and tLZ transitions occur in the same access time windows as data valid
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
November 2004
Rev. 1
9
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White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 8, Pull-Down Characteristics.
b. The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, Pull-Down Characteristics.
c. The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 9, Pull-Up Characteristics
d. The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 9, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.
f. The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
35. VIH overshoot: VIH(MAX) = VCCQ + 1.5V for a pulse width !5 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a
pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
36. VCC and VCCQ must track each other.
37. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
November 2004
Rev. 1
38. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
39. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are
0Vs, provided a minimum of 42 0 of series resistance is used between the VTT
supply and the input pin.
40. The part operates below the slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41. Random addressing changing and 50 percent of data changing at every transfer.
42. Random addressing changing and 100 percent of data changing at every transfer.
43. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
44. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
45. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles.
46. Leakage number reflects the worst case leakage possible through the module pin,
not what each memory device contributes.
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
48. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR AD4
Part Number
Speed
Height*
W3EG7218S262AD4
133MHz/266Mbps, CL=2
35.05 (1.38")
W3EG7218S265AD4
133MHz/266Mbps, CL=2.5
35.05 (1.38")
W3EG7218S202AD4
100MHz/200Mbps, CL=2
35.05 (1.38")
PACKAGE DIMENSIONS FOR AD4
67.56
(2.66) MAX.
2.0
(0.079)
3.81
(0 .150) MAX.
3.98 ± 0.1
(0.157 ± 0.004)
35.05
(1.38) MAX.
20
(0.787)
P1
2.31
(0.091) REF.
4.19
(0.165)
1.80
(0.071)
3.98
(0.157) MIN.
47.40
(1.866)
1.0 ± 0.1
(0.039 ± 0.004)
11.40
(0.449)
* All dimensions are in MILLIMETERS AND (INCHES)
November 2004
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR BD4
Part Number
Speed
Height*
W3EG7218S262BD4
133MHz/266Mbps, CL=2
31.75 (1.25")
W3EG7218S265BD4
133MHz/266Mbps, CL=2.5
31.75 (1.25")
W3EG7218S202BD4
100MHz/200Mbps, CL=2
31.75 (1.25")
PACKAGE DIMENSIONS FOR BD4
3.81
(0.150) MAX.
67.56
(2.666) MAX
3.98 ± 0.1
(0.157 ± 0.004)
31.75
(1.25)
20
(0.787)
2.31
(0.091) REF.
4.19
(0.165)
1.80
(0.071)
3.98
(0.157) MIN.
47.40
(1.866)
1.0 ± 0.1
(0.039 ± 0.004)
11.40
(0.449)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
November 2004
Rev. 1
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7218S-AD4
-BD4
White Electronic Designs
PRELIMINARY
Document Title
128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL
Revision History
Rev #
History
Release Date
Status
Rev A
Created
7-23-03
Advanced
0.1 Data sheet spec updates
9-04
Preliminary
11-04
Preliminary
Rev 0
0.2 Changed datasheet from Advanced to Preliminary
0.3 Added “BD4” package optionr
Rev 1
November 2004
Rev. 1
1.1 Updated new IDD and CAP specs
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com