White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4, 5, or 6 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array (PBGA), 18 x 20mm Write latency = Read latency - 1* tCK • 1.0mm pitch Commercial, Industrial and Military Temperature Ranges Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture Organized as 32M x 72 4-bit prefetch architecture Weight: W3H32M72E-XSBX - 2.5 grams typical DLL for alignment of DQ and DQS transitions with clock signal BENEFITS Four internal banks for concurrent operation (Per DDR2 SDRAM Die) 65% SPACE SAVINGS vs. FPBGA Reduced part count 54% I/O reduction vs FPBGA Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Reduced trace lengths for lower parasitic capacitance Adjustable data – output drive strength Suitable for hi-reliability applications Single 1.8V ±0.1V supply Upgradable to 64M x 72 density (contact factory for information) * This product is under development, is not qualified or characterized and is subject to change without notice. FIGURE 1 – DENSITY COMPARISONS Actual Size W3H32M72E-XSBX CSP Approach (mm) 11.0 11.0 11.0 11.0 11.0 90 FBGA 90 FBGA 90 FBGA 90 FBGA 90 FBGA 18 S A V I N G S 20 19.0 White Electronic Designs W3H32M72E-XSBX Area 5 x 209mm2 = 1,045mm2 360mm2 65% I/O Count 5 x 90 balls = 450 balls 208 Balls 54% White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM CS# WE# RAS# CAS# CKE ODT A0-12 BA0-1 CK0 CS# WE# RAS# CAS# CKE ODT A0-12 BA0-1 DQ0 ¥ CK CK0# CK# LDM0 LDM U0 UDM0 UDM LDQS0 LDQS LDQS0# LDQS# UDQS0 UDQS UDQS0# UDQS# CK1 ¥ ¥ ¥ ¥ ¥ DQ15 CS# WE# RAS# CAS# CKE ODT A0-12 DQ0 BA0-1 ¥ CK UDM1 UDM LDQS1 LDQS ¥ ¥ ¥ ¥ ¥ LDQS1# LDQS# DQ15 UDQS1 UDQS UDQS1# UDQS# CK1# CK# LDM1 LDM U1 DQ0 ¥ ¥ ¥ ¥ ¥ ¥ DQ15 DQ16 ¥ ¥ ¥ ¥ ¥ ¥ DQ31 CS# WE# RAS# CAS# CKE ODT A0-12 BA0-1 DQ0 DQ32 ¥ ¥ ¥ ¥ ¥ ¥ UDM2 UDM LDQS2 LDQS ¥ ¥ ¥ ¥ ¥ ¥ LDQS2# LDQS# DQ15 DQ47 UDQS2 UDQS UDQS2# UDQS# CS# WE# RAS# CAS# CKE ODT A0-12 DQ0 BA0-1 DQ48 CK2 CK CK2# CK# LDM2 LDM U2 UDM3 UDM LDQS3 LDQS ¥ ¥ ¥ ¥ ¥ ¥ LDQS3# LDQS# DQ15 DQ63 UDQS3 UDQS UDQS3# UDQS# CS# WE# RAS# CAS# CKE ODT A0-12 DQ0 BA0-1 DQ64 CK3 CK CK3# CK# LDM3 LDM U3 LDQS4 LDQS LDQS4# LDQS# ¥ ¥ ¥ ¥ ¥ ¥ UDQS4 UDQS DQ8 UDQS4# UDQS# CK4 CK CK4# CK# LDM4 LDM U4 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ DQ71 Note: UDQS4 and UDQS4# require a 10 KΩ pull up resistor. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* FIGURE 3 – PIN CONFIGURATION TOP VIEW 1 A 2 3 4 5 6 7 8 9 10 11 VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS B VCC VSS NC NC NC NC NC NC NC VSS VCC C VSS NC NC NC NC NC NC DQ34 CK3 CK3# VSS D DQ35 DQ51 NC NC NC NC DQ50 DQ53 DQ37 CK2# CK2 E DQ52 DQ36 DQ33 NC DNU** DNU DQ39 LDQS2 LDQS3 DQ48 DQ32 F LDM3 LDM2 DQ49 DQ43 DQ59 DNU DQ55 DQ58 DQ42 LDQS2# LDQS3# G DQ38 DQ54 DQ60 DQ57 UMD2 VSS DQ63 DQ56 DQ40 DQ61 DQ45 H UMD3 DQ44 DQ41 DQ46 DQ62 VCC UDQS2# DQ47 UDQS2 UDQS3 UDQS3# J VCC A6 A10 A9 VCC VSS VCC A3 A12 DNU* VCC K VSS A0 A11 VCC VSS VREF VSS VCC A1 BA1 VSS L VCC A2 A4 A8 VCC VSS VCC BA0 A5 A7 VCC M UDQS1# UDQS1 UDQS0 DQ15 UDQS0# VCC DQ30 DQ14 DQ9 DQ12 UMD1 N DQ13 DQ29 DQ8 DQ24 DQ31 VSS UDM0 DQ25 DQ28 DQ22 DQ6 P LDQS1# LDQS0# DQ10 DQ26 DQ23 ODT DQ27 DQ11 DQ17 LDM0 LDM1 R DQ0 DQ16 LDQS1 LDQS0 DQ7 LDQS4# UDQS4 UDQS4# DQ1 DQ4 DQ20 T CK0 CK0# DQ5 DQ21 DQ18 LDQS4 DQ71 CKE WE# DQ19 DQ3 U VSS CK1# CK1 DQ2 RAS# CAS# DQ64 DQ70 DQ65 DQ68 VSS V VCC VSS CK4# CK4 CS# DQ66 DQ69 LDM4 DQ67 VSS VCC W VSS VCC VSS VCC VCC VSS Vcc VCC VSS VCC VSS * Pin J10 is reserved for signal A13 on 128Mx72 and higher densities. ** Pin E5 is reserved for signal BA2 on 64Mx72 and higher densities. Note: UDQS4 and UDQS4# require a 10 KΩ pull up resistor. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* TABLE 1 – BALL DESCRIPTIONS Symbol Type Description ODT Input On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command. CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once VCC is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered. LDM, UDM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4 BA0–BA1 Input Bank address inputs: BA0–BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA1 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Continued on next page White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* TABLE – 1 BALL DESCRIPTIONS (continued) Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA1–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD MODE command. A0-A12 Input DQ0-71 I/O Data input/output: Bidirectional data bus UDQS, UDQS# I/O Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edgealigned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. LDQS, LDQS# I/O Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edgealigned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. VCC Supply Power Supply: 1.8V ±0.1V VCCQ Supply DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity VREF Supply SSTL_18 reference voltage. VSS Supply Ground NC - No connect: These balls should be left unconnected. - Future use; Row address bits A14 and A15 are reserved for 8Gb and 16Gb densities. BA2 is reserved for 4Gb device. DNU White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* DESCRIPTION The 2Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 2,147,483,648 bits. Each of the five ships in the MCP are internally configured as 4-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. The 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the 2Gb DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A self refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18compatible. GENERAL NOTES A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. There are strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The 2Gb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. • The functionality and the timing specifications discussed in this data sheet are for the DLLenabled mode of operation. • Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, each chip is divided into 2 bytes, the lower byte and upper byte. For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS. Note that the there is no upper byte for U4 and therefore no UDM4. • Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. INITIALIZATION DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for power up and initialization and is shown in Figure 4 on page 8. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write. 1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* low level must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ, VREF, and VTT are between their minimum and maximum values as stated in Table20): A. ±0.3V with respect to VCCQ/2 during supply ramp time; VCCQ ≥ VREF must be met at all times • Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN) is achieved must be no greater than 500ms (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping is complete (when VCCQ crosses VCC (MIN)), Table20 specifications apply. • VCC, VCCQ are driven from a single power converter output 2. For a minimum of 200µs after stable power nd clock (CK, CK#), apply NOP or DESELECT commands and take CKE HIGH. 3. Wait a minimum of 400ns, then issue a PRECHARGE ALL command. 4. Issue an LOAD MODE command to the EMR(2). (To issue an EMR(2) command, provide LOW to BA0, provide HIGH to BA1.) 5. Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3) command, provide HIGH to BA0 and BA1.) 6. Issue an LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and E9 can be set to “0” or “1”; Micron recommends setting them to “0.” 7. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1, and BA0.) CKE must be HIGH the entire time. 8. Issue PRECHARGE ALL command. 9. Issue two or more REFRESH commands, followed by a dummy WRITE. • VTT is limited to 0.95V MAX • VREF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp time • VCCQ ≥ VREF at all times B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping, for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses VCC [MIN]). Once supply voltage ramping is complete, Table20 specifications apply. • Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms from when VCC ramps from 300mV to VCC (MIN) • Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is ramping, current can be supplied from VCC through the device to VCCQ • VREF must track VCCQ/2, VREF must be within White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* FIGURE 4 – POWER-UP AND INITIALIZATION Notes appear on page 9 VCC VCCQ t VTD1 VTT1 VREF T0 Ta0 tCK Tc0 Tb0 Tg 0 Tf 0 Te0 Td0 Th 0 Ti 0 Tk 0 Tj 0 Tl 0 Tm 0 CK# CK tCL tCL See not e 3 SSTL_18 LVCM OS CKE LOW LEVEL8 LOW LEVEL8 OD T NOP2 COM M A ND PRE LM LM LM LM PRE A 10 = 1 CODE CODE CODE CODE A 10 = 1 REF REF LM LM LM VA LID3 CODE CODE CODE VA LID DM 7 A DDRESS9 DQS7 Hi g h -Z DQ 7 Hi g h -Z RTT Hi g h -Z T = 200µ s (M IN) Po w er -u p : VCC an d st ab l e cl o ck (CK, CK#) DON’ T CA RE T = 400n s (M IN) t M RD t RPA EM R(2) t M RD t M RD t M RD t RPA EM R w i t h DLL ENA BLE5 EM R(3) t RFC t M RD t M RD t M RD See not e 4 M R w /o EM R w i t h DLL RESET OCD Def au l t 10 200 cycl es o f CK3 M R w it h DLL RESET In dicat es a b r eak i n t i m e scal e t RFC EM R w i t h OCD Exi t 11 No r m al Op er at i o n White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* NOTES: 1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF, and VTT are between their minimum and maximum values as stated in DC Operating Conditions table): A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications apply. • VCC, VCCQ are driven from a single power converter output • VTT is limited to 0.95V MAX • VREF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp time. • VCCQ ≥ VREF at all times B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping, for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses VCC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table specifications apply. • Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms from when VCC ramps from 300mV to VCC (MIN) • Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is ramping, current can be supplied from VCC through the device to VCCQ • VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp time; VCCQ ≥ VREF must be met at all times • Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN) is achieved must be no greater than 500ms 2. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT commands and take CKE HIGH. Wait a minimum of 400ns, then issue a PRECHARGE ALL command/ Issue an LOAD MODE command to the EMR(2). (To issue an EMR(2) command, provide LOW to BA0, provide HIGH to BA1.) 5. Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3) command, provide HIGH to BA0 and BA1.) 6. Issue an LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and E9 can be set to “0” or “1”; Micron recommends setting them to “0.” 7. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1, and BA0.) CKE must be HIGH the entire time. 8. Issue PRECHARGE ALL command. 9. Issue two or more REFRESH commands, followed by a dummy WRITE. 10. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). 11. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and E9 to “1,” and then setting all other desired parameters. 12. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to “0,” and then setting all other desired parameters. 13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). 14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7,E8, and E9 to “1,” and then setting all other desired parameters. 15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to “0,” and then setting all other desired parameters. The DDR2 SDRAM is now initialized and ready for normal operation 200 clocks after DLL RESET (in step 7). 3. 4. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* MODE REGISTER (MR) FIGURE 5 – MODE REGISTER (MR) DEFINITION The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CL, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 5. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0–M14) must be programmed when the command is issued. BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 15 14 13 12 11 10 01 PD MR WR 9 8 7 6 5 4 3 2 1 0 DLL TM CAS# Latency BT Burst Length M7 Mo de M12 PD mode 0 Fast Exit The mode register is programmed via the LM command (bits BA1–BA0 = 0, 0) and other bits (M12–M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is selfclearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. (Normal) Test M8 DLL Reset 0 Reserved 0 1 Reserved 0 1 0 4 0 1 1 8 No 1 0 0 Reserved (Low Power) 1 Yes 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 0 0 0 Reserved 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 Reserved 1 1 1 Reserved Mo de Register Definition M15 M14 Burst length is defined by bits M0–M3, as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length dete rmines the maximum number of column locations that can be accessed for a given READ or WRITE command. 0 0 0 M11 M10 M9 WRITE RECOVERY BURST LENGTH 0 Slow Exit 1 The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time tMRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. Mode Register (Mx) M2 M1 M0 Burst Length 0 Normal 1 Address Bus Mode Register (MR) 0 0 0 1 Extended Mode Register (EMR) 1 0 Extended Mode Register (EMR2) 1 1 Extended Mode Register (EMR3) M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency (CL) 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Reserved Note: 1. Not used on this part BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* DLL RESET TABLE 2 – BURST DEFINITION Burst Length Starting Column Address 4 8 DLL RESET is defined by bit M8, as shown in Figure 5. Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. Order of Accesses Within a Burst Type = Sequential Type = Interleaved A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 1 1 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. WRITE RECOVERY Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 5. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last data burst. WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9–M11. The user is required to program the value of WR, which is calculated by dividing t WR (in ns) by tCK (in ns) and rounding up a non integer value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. POWER-DOWN MODE Active power-down (PD) mode is defined by bit M12, as shown in Figure 5. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. OPERATING MODE The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 5. When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is ‘1.’ When bit M12 = 0, standard active PD mode or “fast-exit” active PD mode is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode or “slowexit” active PD mode is enabled. The tXARD parameter is used for slow-exit active PD exit timing. The DLL can be enabled, but “frozen” during active PD mode since the exitto-READ command timing is relaxed. The power difference expected between PD normal and PD low-power mode is defined in the ICC table. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* CAS LATENCY (CL) The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 5. CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending on the speed grade option being used. DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. Examples of CL = 3 and CL = 4 are shown in Figure 6; both assume AL = 0. If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n+m (this assumes AL = 0). DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. FIGURE 6 – CAS LATENCY (CL) CK# T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK COMMAND DQS, DQS# DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 3 (AL = 0) CK# T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK COMMAND DQS, DQS# DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 4 (AL = 0) Burst length = 4 Posted CAS# additive latency (AL) = 0 Shown with nominal t AC, t DQSCK, and t DQSQ TRANSITIONING DATA DON’T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* EXTENDED MODE REGISTER (EMR) The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These functions are controlled via the bits shown in Figure 7. The EMR is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. FIGURE 7 – EXTENDED MODE REGISTER DEFINITION BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 15 14 13 MRS 12 11 10 9 8 7 5 4 3 A1 A0 2 1 0 02 out RDQS DQS# OCD Program Rtt Posted CAS# Rtt ODS DLL E12 Outputs 0 Enabled 1 Disabled 0 No 1 Yes Enable 1 Disable Extended Mode Register (Ex) E0 DLL Enable 0 Enable (Normal) Rtt Disabled 1 Disable (Test/Debug) 0 0 0 1 75Ω 1 0 150Ω E1 1 1 50Ω 0 Full Strength (18 Ω target) 1 Reduced Strength (40 Ω target) E10 DQS# Enable 0 Address Bus E6 E2 Rtt (nominal) E11 RDQS Enable Output Drive Strength E5 E4 E3 Poste d CAS# Add itive Laten cy (AL) E9 E8 E7 OCD Operation E15 E14 6 A2 1 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 0 0 0 OCD Not Supported 0 0 1 Reserved 1 0 1 Reserved 0 1 0 Reserved 1 1 0 Reserved 1 0 0 Reserved 1 1 1 Reserved 1 1 1 OCD default state 1 Mo de Register Set Mode Register Set (MR S) 0 0 0 1 Extended Mode Register (EMR S) 1 0 Extended Mode Register (EMR S2) 1 1 Extended Mode Register (EMR S3) Note: 1. During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before initialization is finished, as detailed in the initialization procedure. 2.. E13 (A13) is not used on this device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* DLL ENABLE/DISABLE OUTPUT ENABLE/DISABLE The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 7. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using an LM command. The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, thus removing output buffer current. The output disable feature is intended to be used during ICC characterization of read current. ON-DIE TERMINATION (ODT) The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH operation. ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure 7. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 50Ω ,75Ω, and 150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is elected by enabling switch “sw1,” which enables all R1 values that are 150Ω each, enabling an effective resistance of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values of 100Ω enabling effective resistance of 50Ω Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued, to allow time for the internal clock to synchronize with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. OUTPUT DRIVE STRENGTH The output drive strength is defined by bit E1, as shown in Figure 7. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 60 percent of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or point-to-point environments. The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge powerdown modes of operation. ODT must be turned off prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until issuing the EMR command to enable the ODT feature, at which point the ODT ball will determine the RTT(EFF) value. Any time the EMR enables the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See “ODT Timing” section for ODT timing diagrams. DQS# ENABLE/DISABLE The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single ended mode and the DQS# ball is disabled. When disabled, DQS# should be left floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* POSTED CAS ADDITIVE LATENCY (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical application using this feature would set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is controlled by the sum of AL and CL; RL = AL+CL. Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 x tCK. FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EMR2 01 01 01 01 01 01 01 01 01 01 01 01 M15 M14 Mode Register Definition 0 0 Mo de Register (MR) 0 1 Extended Mo de Register (EMR) 1 0 Extended Mo de Register (EMR2) 1 1 Extended Mo de Register (EMR3) A1 A0 1 1 0 0 01 Address Bus Extended Mo de Register (Ex) E7 High Temperature Self Refresh rate enable 0 1 Commer cial-Temperature default Industrial-Temperature option; use if T C exceeds 85°C Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to "0." A13 is not used in this device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 15 14 13 12 11 10 9 8 7 6 5 4 3 EMR3 01 01 01 01 01 01 01 01 01 01 01 M15 M14 2 01 A1 A0 1 01 0 01 Address Bus Extended Mo de Register (Ex) Mode Register Definition 0 0 Mo de Register (MR) 0 1 Extended Mo de Register (EMR) 1 0 Extended Mo de Register (EMR2) 1 1 Extended Mo de Register (EMR3) Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to "0." A13 is not used in this device. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. EXTENDED MODE REGISTER 2 The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved, as shown in Figure 8. The EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. COMMAND TRUTH TABLES The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-to-bank commands. EMR2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. EXTENDED MODE REGISTER 3 The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently, all bits in EMR3 are reserved, as shown in Figure 9. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* TABLE 3 – TRUTH TABLE - DDR2 COMMANDS Notes appear on page 9 CKE Function Previous Cycle Current Cycle CS# RAS# CAS# WE# BA1 BA0 LOAD MODE H H L L L L BA REFRESH H H L L L H X X X X SELF-REFRESH Entry H L X X X X X X X X 7 X X L X 2 X H X L L L H H X X X L H H H L L H L A12 A11 A10 A9-A0 Notes OP Code 2 SELF-REFRESH Exit L H Single bank precharge H H All banks PRECHARGE H H L L H L X Bank activate H H L L H L BA WRITE H H L L H L BA Column Address L Column Address 2, 3 WRITE with auto precharge H H L H L L BA Column Address H Column Address 2, 3 READ H H L H L H BA Column Address L Column Address 2, 3 READ with auto precharge H H L H L H BA Column Address H Column Address 2, 3 Row Address NO OPERATION H X L H H H X X X X Device DESELECT H X H X X X X X X X POWER-DOWN entry H L X X X X 4 POWER-DOWN exit L H X X X X 4 H X X X L H H H H X X X L H H H Note: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. 2. Bank addresses (BA) BA0–BA12 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed. 3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. 4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details. 6. “X” means “H or L” (but a defined logic level). 7. Self refresh exit is asynchronous. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 17 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. NO OPERATION (NOP) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD LOAD MODE (LM) The mode registers are loaded via inputs BA1–BA0, and A12–A0. BA1–BA0 determine which mode register will be programmed. See “Mode Register (MR)”. The LM command can only be issued when all banks are idle, and a subsequent execute able command cannot be issued until tMRD is met. FIGURE 10 – ACTIVE COMMAND BANK/ROW ACTIVATION CK# ACTIVE COMMAND CK The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA1–BA0 inputs selects the bank, and the address provided on inputs A12–A0 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. CKE CS# RAS# CAS# ACTIVE OPERATION WE# Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. ADDRESS Row BANK ADDRESS Bank After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be DON’T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 18 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* READ COMMAND The READ command is used to initiate a burst read access to an active row. The value on the BA1–BA0 inputs selects the bank, and the address provided on inputs A0–i (where i = A9) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. FIGURE 11 – READ COMMAND READ OPERATION CK# READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. CK CKE CS# During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). RAS# CAS# WE# ADDRESS DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the read preamble (tRPRE). The LOW state on DQS and HIGH state on DQS# coincident with the last data-out element is known as the read postamble (tRPST). Col ENABLE AUTO PRECHARGE A10 DISABLE BANK ADDRESS Bank DON’T CARE Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 19 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* WRITE COMMAND The WRITE command is used to initiate a burst write access to an active row. The value on the BA1–BA0 inputs selects the bank, and the address provided on inputs A0–9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. The time between the WRITE command and the first rising DQS edge is WL ± tDQSS. Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as ± tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The first data element from the new burst is applied after the last element of a completed burst. The new WRITE command should be issued x cycles after the first WRITE command, where x equals BL/2. WRITE OPERATION DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 4. WRITE bursts are initiated with a WRITE command, as shown in Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE (with auto precharge disabled) using BL = 8 operation might be interrupted and truncated ONLY by another WRITE burst as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not to be interrupted or truncated with any command except another WRITE command. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. tWT starts at the end of the data burst, regardless of the data mask condition. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 20 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* FIGURE 12 – WRITE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# CA ADDRESS EN AP A10 DIS AP BANK ADDRESS BA DON’T CARE Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge. TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE From Command (Bank n) WRITE with Auto Precharge Minimum Delay (With Concurrent Auto Precharge) To Command (Bank m) t Units READ OR READ w/AP (CL-1) + (BL/2) + WTR t CK WRITE or WRITE w/AP (BL/2) t CK 1 t CK PRECHARGE or ACTIVE White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* PRECHARGE COMMAND The PRECHARGE command, illustrated in Figure 13, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. FIGURE 13 – PRECHARGE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# PRECHARGE OPERATION ADDRESS Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA1–BA0 select the bank. Otherwise BA1–BA0 are treated as “Don’t Care.” ALL BANKS A10 ONE BANK BA0, BA1 When all banks are to be precharged, inputs BA1–BA0 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. BA DON’T CARE Note: BA = bank address (if A10 is LOW; otherwise "Don't Care"). issued). The differential clock should remain stable and meet tCKE specifications at least 1 x tCK after entering self refresh mode. All command and address input signals except CKE are “Don’t Care” during self refresh. SELF REFRESH COMMAND The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable and meet tCK specifications at least 1 x tCK prior to CKE going back HIGH. Once CKE is HIGH (tCLE(MIN) has been satisfied with four clock registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOP or DESELECT commands for 200 clock cycles before applying any other command. The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including VREF) must be maintained at valid levels upon entry/exit and during SELF REFRESH operation. The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a READ command can be Note: Self refresh not available at military temperature.. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 22 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VREF VTT Min 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 0.50 x VCCQ VREF Max 1 .9 1 .9 0.51 x VCCQ VREF + 0.04 Unit V V V V Notes 1 4 2 3 Notes: 1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC track with VCC. ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCQ VIN, VOUT TSTG TCASE IL IOZ IVREF Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on any pin relative to VSS Storage temperature Device operating temperature Command/Address, RAS#, CAS#, WE#, CS#, CKE CK, CK# DM Input leakage current; Any input 0V<VIN<VCC; VREF input 0V<VIN<0.95V; Other pins not under test = 0V Output leakage current; 0V<VOUT<VCCQ; DQs and ODT are disable VREF leakage current; VREF = Valid VREF level DQ, DQS, DQS# MIN -1.0 -0.5 -0.5 -55 -55 MAX 2.3 2.3 2.3 125 125 U nit V V V °C °C -25 25 µA -10 -5 10 5 µA µA -5 5 µA -18 18 µA INPUT/OUTPUT CAPACITANCE TA = 25°C, f = 1MHz, VCC = VCCQ = 1.8V Parameter Symbol Max Unit CIN1 TBD pF Input capacitance CK, CK# CIN2 TBD pF Input capacitance DM, DQS, DQS# CIN3 TBD pF Input capacitance DQ0 - 71 COUT TBD pF Input capacitance (A0 - A12, BA0 - BA1 ,CS#, RAS#,CAS#,WE#, CKE, ODT) White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 23 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit Input High (Logic 1) Voltage VIH(DC) VREF + 0.1 25 VCCQ + 0.300 V Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 VIH(AC) VREF + 0.250 — V AC Input High (Logic 1) Voltage DDR2-667 VIH(AC) VREF + 0.200 — V AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL(AC) — VREF - 0.250 V AC Input Low (Logic 0) Voltage DDR2-667 VIL(AC) — VREF - 0.200 V White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 24 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* DDR2 ICC SPECIFICATIONS AND CONDITIONS VCC = 1.8V ±0.1V; -55°C ≤ TA ≤ 125°C Symbol 533 CL4 400 CL3 Units ICC0 Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Proposed Conditions 550 550 mA ICC1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W 675 650 mA ICC2P Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 25 25 mA ICC2Q Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 225 200 mA ICC2N Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 250 225 mA Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 150 125 mA ICC3P Slow PDN Exit MRS(12) = 1 50 50 mA 300 250 mA 1,025 800 mA 975 775 mA 1,050 1,000 mA 25 25 mA 1,700 1,700 mA ICC3N Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING ICC4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING ICC4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W ICC5 Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING ICC6 Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING ICC7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing conditions Normal White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 25 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* AC TIMING PARAMETERS -55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V Parameter Data Clock Clock cycle time Data Strobe 533Mbs CL4 400Mbs CL3 Min Max Min Max Symbol Unit CL=4 tCK(4) 3,750 8,000 5,000 8,000 CL=3 ps tCK(3) 5,000 8,000 5,000 8,000 ps CK high-level width tCH 0.48 0.52 0.48 0.59 tCK CK low-level width tCL 0.48 0.52 0.48 0.59 tCK Half clock period tHP MIN (tCH, tCL) DQ output access time from CK/CK# tAC -500 Data-out high impedance window from CK/CK# tHZ Data-out low-impedance window from CK/CK# tLZ tAC(MN) DQ and DM input setup time relative to DQS tDS 100 DQ and DM input hold time relative to DQS tQH 225 275 DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 Data hold skew factor tQHS DQ-DQS hold, DQS to first DQ to go nonvalid, per access tHQ tHP - tQHS tHP - tQHS Data valid output window (DVW) tDVW tQH - tDQSQ tQH - tDQSQ ns DQS input high pulse width tDQSH 0.35 0.35 tCK MIN (tCH, tCL) +500 -600 tAC(MAX) tAC(MAX) tAC(MN) ps +600 ps tAC(MAX) ps tAC(MAX) ps 150 400 tCK 450 ps ps DQS input low pulse width tDQSL 0.35 DQS output access time fromCK/CK# tDQSCK -450 0.35 DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK O DQS-DQ skew, DOS to last DQ valid, per group, per access tDQSQ 350 ps DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK DQS write preamble setup time tWPRES 0 0 ps DQS write preamble tWPRE 0.25 0.25 tCK DQS write postamble tWPST Write command to first DQS latching transition tDQSS +450 -500 300 0.4 0.6 0.4 tCK +500 0.6 WL-TDQSS WL+TDQSS WL-TDQSS WL+TDQSS Ps tCK tCK White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 26 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* AC TIMING PARAMETERS (continued) -55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V Parameter Address and control input pulse width for each input Address and control input setup time Power-Down ODT Self Refresh Command and Address Address and control input hold time Symbol tIPW tISa tISb tIHa tIHb tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK, CK# uncertainty REFRESH to Active or Refresh to Refresh command interval Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ Exit self refresh timing reference ODT tum-on delay ODT turn-on ODT turn-off delay ODT tum-off tDELAY tRFC tREFI tXSNR tXSRD tlSXR tAOND tACN tAOFD tAOF ODT tum-on (power-down mode) tAONPD ODT turn-off (power-down mode) tAOFPD ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command CKE minimum high/low time tANPD tAXPD tXARD tXARDS tXP tCKE 533Mbs CL4 Min 0.6 500 250 500 375 2 55 10 15 50 40 7.5 15 tWR + tRP 7.5 15 tRP + tCK 2 tIS +tIH + tCK 105 Max 70,000 70,000 7.8 400Mbs CL3 Min 0.6 600 350 600 475 2 55 10 15 50 40 7.5 15 tWR + tRP 10 15 tRP + tCK 2 tIS +tIH + tCK 105 Unit Max 70,000 70,000 7.8 tRPC(MIN) + 10 tRFC(MIN) + 10 200 200 tIS tIS 2 2 2 2 tAC(MIN) tAC(MAX) + 1000 tAC(MIN) tAC(MAX) + 1000 2.5 2.5 2.5 2.5 tAC(MIN) tAC(MAX) + tAC(MIN) tAC(MAX) + 600 600 tAC(MIN) + 2 x tCK + tAC(MIN) + 2 x tCK + 2000 tAC(MAX) + 1000 2000 tAC(MAX) + 1000 tAC(MIN) + 2 x tCK + 2 x tCK + tAC(MIN) + 2000 tAC(MAX) + 1000 2000 tAC(MAX) + 1000 3 3 8 8 2 2 6-AL 6-AL 2 2 3 3 tCK ps ps ps ps ps ns ns ns ns ns ns ns ns ns ns ns tCK ns ns ns ns tCK ps tCK ps tCK ps ps ps tCK tCK tCK tCK tCK tCK White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 27 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA) BOTTOM VIEW 208 x Ø 0.60 (0.024) NOM 11 10 9 8 7 6 5 4 3 2 1 A B C D E F 18.0 (0.709) NOM H J K L M 1.0 (0.039) NOM 20.15 (0.793) MAX G N P R T U V W 1.0 (0.039)NOM 0.50 (0.020) NOM 10.0 (0.394) NOM 18.15 (0.715) MAX 3.20 (0.126) MAX All linear dimensions are millimeters and parenthetically in inches White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 28 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* ORDERING INFORMATION W 3H 32M 72 E - XXX SB X WHITE ELECTRONIC DESIGNS CORP. DDR2 SDRAM CONFIGURATION, 32M x 72 1.8V Power Supply DATA RATE (Mbs) 400 = 400Mbs CL3 533 = 533Mbs CL4 667 = 667Mbs(2) CL5 Blank = No data rate specified for ES product(1) PACKAGE: ES = Non Qualified Product (1) SB = 208 Plastic Ball Grid Array (PBGA) DEVICE GRADE: M = Military -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C Blank = No temperature specified for ES product(1) Note 1: W3H32M72E-ESSB is the only available product until completion of qualification. 2: Data rate of 667Mbs is advanced, contact factory for future availability. White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 29 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H32M72E-XSBX PRELIMINARY* Document Title 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial Release September 2005 Advanced Rev 1 Changes (Pg. 1, 3, 6) November 2005 Advanced February 2006 Preliminary 1.1 Add pinout Rev 2 Change (Pg. All) 2.1 Change status to Preliminary 2.2 Add additional functional information White Electronic Designs Corp. reserves the right to change products or specifications without notice. February 2006 Rev. 2 30 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com